tg3: Add EEE support

This patch adds Energy Efficient Ethernet (EEE) support for the 5718
device ID and the 57765 B0 asic revision.

Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

1 files changed, 32 insertions, 1 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 99fc30680217..8342190df0ff 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -1091,7 +1091,26 @@
 #define  CPMU_MUTEX_GNT_DRIVER           0x00001000
 #define TG3_CPMU_PHY_STRAP              0x00003664
 #define TG3_CPMU_PHY_STRAP_IS_SERDES     0x00000020
-/* 0x3664 --> 0x3800 unused */
+/* 0x3664 --> 0x36b0 unused */
+
+#define TG3_CPMU_EEE_MODE               0x000036b0
+#define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET   0x00000008
+#define TG3_CPMU_EEEMD_LPI_ENABLE        0x00000080
+#define TG3_CPMU_EEEMD_LPI_IN_TX         0x00000100
+#define TG3_CPMU_EEEMD_LPI_IN_RX         0x00000200
+#define TG3_CPMU_EEEMD_EEE_ENABLE        0x00100000
+/* 0x36b4 --> 0x36b8 unused */
+
+#define TG3_CPMU_EEE_LNKIDL_CTRL        0x000036bc
+#define  TG3_CPMU_EEE_LNKIDL_PCIE_NL0    0x01000000
+#define  TG3_CPMU_EEE_LNKIDL_UART_IDL    0x00000004
+/* 0x36c0 --> 0x36d0 unused */
+
+#define TG3_CPMU_EEE_CTRL               0x000036d0
+#define TG3_CPMU_EEE_CTRL_EXIT_16_5_US   0x0000019d
+#define TG3_CPMU_EEE_CTRL_EXIT_36_US     0x00000384
+#define TG3_CPMU_EEE_CTRL_EXIT_20_1_US   0x000001f8
+/* 0x36d4 --> 0x3800 unused */
 
 /* Mbuf cluster free registers */
 #define MBFREE_MODE                     0x00003800
@@ -2082,6 +2101,8 @@
 #define MII_TG3_DSP_TAP1                0x0001
 #define  MII_TG3_DSP_TAP1_AGCTGT_DFLT   0x0007
 #define MII_TG3_DSP_AADJ1CH0            0x001f
+#define MII_TG3_DSP_CH34TP2             0x4022
+#define MII_TG3_DSP_CH34TP2_HIBW01      0x0010
 #define MII_TG3_DSP_AADJ1CH3            0x601f
 #define  MII_TG3_DSP_AADJ1CH3_ADCCKADJ  0x0002
 #define MII_TG3_DSP_EXP1_INT_STAT       0x0f01
@@ -2148,6 +2169,14 @@
 #define MII_TG3_TEST1_TRIM_EN           0x0010
 #define MII_TG3_TEST1_CRC_EN            0x8000
 
+/* Clause 45 expansion registers */
+#define TG3_CL45_D7_EEEADV_CAP          0x003c
+#define TG3_CL45_D7_EEEADV_CAP_100TX    0x0002
+#define TG3_CL45_D7_EEEADV_CAP_1000T    0x0004
+#define TG3_CL45_D7_EEERES_STAT         0x803e
+#define TG3_CL45_D7_EEERES_STAT_LP_100TX        0x0002
+#define TG3_CL45_D7_EEERES_STAT_LP_1000T        0x0004
+
 
 /* Fast Ethernet Tranceiver definitions */
 #define MII_TG3_FET_PTEST               0x17
@@ -2992,9 +3021,11 @@ struct tg3 {
 #define TG3_PHYFLG_BER_BUG              0x00008000
 #define TG3_PHYFLG_SERDES_PREEMPHASIS   0x00010000
 #define TG3_PHYFLG_PARALLEL_DETECT      0x00020000
+#define TG3_PHYFLG_EEE_CAP              0x00040000
 
         u32                             led_ctrl;
         u32                             phy_otp;
+        u32                             setlpicnt;
 
 #define TG3_BPN_SIZE                    24
         char                            board_part_number[TG3_BPN_SIZE];