diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2007-10-08 02:28:35 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2007-10-10 19:54:45 -0400 |
commit | d30cdd28fba556143a4bb0d1a6097ebcc2891477 (patch) | |
tree | 00a6548cbd6cdf13a88427c66c520456444c3a6b /drivers/net/tg3.h | |
parent | 795d01c523dd9f22acc70fe86ed30e605e00024d (diff) |
[TG3]: Add 5784 and 5764 support.
This patch adds the support for 5784 and 5764 devices.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 79ce68cf836b..d8e829f6fcb2 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -108,6 +108,7 @@ | |||
108 | #define CHIPREV_ID_5752_A1 0x6001 | 108 | #define CHIPREV_ID_5752_A1 0x6001 |
109 | #define CHIPREV_ID_5714_A2 0x9002 | 109 | #define CHIPREV_ID_5714_A2 0x9002 |
110 | #define CHIPREV_ID_5906_A1 0xc001 | 110 | #define CHIPREV_ID_5906_A1 0xc001 |
111 | #define CHIPREV_ID_5784_A0 0x5784000 | ||
111 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) | 112 | #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) |
112 | #define ASIC_REV_5700 0x07 | 113 | #define ASIC_REV_5700 0x07 |
113 | #define ASIC_REV_5701 0x00 | 114 | #define ASIC_REV_5701 0x00 |
@@ -122,6 +123,7 @@ | |||
122 | #define ASIC_REV_5787 0x0b | 123 | #define ASIC_REV_5787 0x0b |
123 | #define ASIC_REV_5906 0x0c | 124 | #define ASIC_REV_5906 0x0c |
124 | #define ASIC_REV_USE_PROD_ID_REG 0x0f | 125 | #define ASIC_REV_USE_PROD_ID_REG 0x0f |
126 | #define ASIC_REV_5784 0x5784 | ||
125 | #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) | 127 | #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8) |
126 | #define CHIPREV_5700_AX 0x70 | 128 | #define CHIPREV_5700_AX 0x70 |
127 | #define CHIPREV_5700_BX 0x71 | 129 | #define CHIPREV_5700_BX 0x71 |
@@ -843,7 +845,13 @@ | |||
843 | #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 | 845 | #define RCVLSC_MODE_ATTN_ENABLE 0x00000004 |
844 | #define RCVLSC_STATUS 0x00003404 | 846 | #define RCVLSC_STATUS 0x00003404 |
845 | #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 | 847 | #define RCVLSC_STATUS_ERROR_ATTN 0x00000004 |
846 | /* 0x3408 --> 0x3800 unused */ | 848 | /* 0x3408 --> 0x3600 unused */ |
849 | |||
850 | /* CPMU registers */ | ||
851 | #define TG3_CPMU_CTRL 0x00003600 | ||
852 | #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200 | ||
853 | #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400 | ||
854 | /* 0x3604 --> 0x3800 unused */ | ||
847 | 855 | ||
848 | /* Mbuf cluster free registers */ | 856 | /* Mbuf cluster free registers */ |
849 | #define MBFREE_MODE 0x00003800 | 857 | #define MBFREE_MODE 0x00003800 |
@@ -1023,7 +1031,10 @@ | |||
1023 | #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 | 1031 | #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100 |
1024 | #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 | 1032 | #define RDMAC_MODE_LNGREAD_ENAB 0x00000200 |
1025 | #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 | 1033 | #define RDMAC_MODE_SPLIT_ENABLE 0x00000800 |
1034 | #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800 | ||
1026 | #define RDMAC_MODE_SPLIT_RESET 0x00001000 | 1035 | #define RDMAC_MODE_SPLIT_RESET 0x00001000 |
1036 | #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000 | ||
1037 | #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000 | ||
1027 | #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 | 1038 | #define RDMAC_MODE_FIFO_SIZE_128 0x00020000 |
1028 | #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 | 1039 | #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000 |
1029 | #define RDMAC_STATUS 0x00004804 | 1040 | #define RDMAC_STATUS 0x00004804 |
@@ -2315,6 +2326,7 @@ struct tg3 { | |||
2315 | #define PHY_ID_BCM5755 0xbc050cc0 | 2326 | #define PHY_ID_BCM5755 0xbc050cc0 |
2316 | #define PHY_ID_BCM5787 0xbc050ce0 | 2327 | #define PHY_ID_BCM5787 0xbc050ce0 |
2317 | #define PHY_ID_BCM5756 0xbc050ed0 | 2328 | #define PHY_ID_BCM5756 0xbc050ed0 |
2329 | #define PHY_ID_BCM5784 0xbc050fa0 | ||
2318 | #define PHY_ID_BCM5906 0xdc00ac40 | 2330 | #define PHY_ID_BCM5906 0xdc00ac40 |
2319 | #define PHY_ID_BCM8002 0x60010140 | 2331 | #define PHY_ID_BCM8002 0x60010140 |
2320 | #define PHY_ID_INVALID 0xffffffff | 2332 | #define PHY_ID_INVALID 0xffffffff |