[PATCH] tg3: add 5714/5715 support

Add complete support for 5714/5715. These chips are very similar to
5780 so the changes are very trivial. A TG3_FLG2_5780_CLASS flag is
added to identify these chips.

Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

1 files changed, 9 insertions, 2 deletions

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 2e733c60bfa4..456ef2b3d0ef 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -137,6 +137,7 @@
 #define   ASIC_REV_5750                  0x04
 #define   ASIC_REV_5752                  0x06
 #define   ASIC_REV_5780                  0x08
+#define   ASIC_REV_5714                  0x09
 #define  GET_CHIP_REV(CHIP_REV_ID)      ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX                0x70
 #define   CHIPREV_5700_BX                0x71
@@ -531,6 +532,8 @@
 #define  MAC_SERDES_CFG_EDGE_SELECT      0x00001000
 #define MAC_SERDES_STAT                 0x00000594
 /* 0x598 --> 0x5b0 unused */
+#define SERDES_RX_CTRL                  0x000005b0      /* 5780/5714 only */
+#define  SERDES_RX_SIG_DETECT            0x00000400
 #define SG_DIG_CTRL                     0x000005b0
 #define  SG_DIG_USING_HW_AUTONEG         0x80000000
 #define  SG_DIG_SOFT_RESET               0x40000000
@@ -1329,6 +1332,8 @@
 #define  GRC_LCLCTRL_CLEARINT           0x00000002
 #define  GRC_LCLCTRL_SETINT             0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN        0x00000008
+#define  GRC_LCLCTRL_USE_SIG_DETECT     0x00000010      /* 5714/5780 only */
+#define  GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020      /* 5714/5780 only */
 #define  GRC_LCLCTRL_GPIO_INPUT3        0x00000020
 #define  GRC_LCLCTRL_GPIO_OE3           0x00000040
 #define  GRC_LCLCTRL_GPIO_OUTPUT3       0x00000080
@@ -2175,6 +2180,7 @@ struct tg3 {
                                         TG3_FLG2_MII_SERDES)
 #define TG3_FLG2_PARALLEL_DETECT        0x01000000
 #define TG3_FLG2_ICH_WORKAROUND         0x02000000
+#define TG3_FLG2_5780_CLASS             0x04000000
 
         u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ         3
@@ -2222,6 +2228,7 @@ struct tg3 {
 #define PHY_ID_BCM5705                  0x600081a0
 #define PHY_ID_BCM5750                  0x60008180
 #define PHY_ID_BCM5752                  0x60008100
+#define PHY_ID_BCM5714                  0x60008340
 #define PHY_ID_BCM5780                  0x60008350
 #define PHY_ID_BCM8002                  0x60010140
 #define PHY_ID_INVALID                  0xffffffff
@@ -2246,8 +2253,8 @@ struct tg3 {
          (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
          (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
          (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
-         (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5780 || \
-         (X) == PHY_ID_BCM8002)
+         (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
+         (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM8002)
 
         struct tg3_hw_stats             *hw_stats;
         dma_addr_t                      stats_mapping;