diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2009-09-01 09:20:17 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-09-02 03:44:06 -0400 |
| commit | a1b950d56de3c72bea3343f54de24c43fb7dc74e (patch) | |
| tree | f54f22cec072bbc17ec963ddc3e832ccf4db7bc0 /drivers/net/tg3.h | |
| parent | f6eb9b1fc1411d22c073f5264e5630a541d0f7df (diff) | |
tg3: Add 5717 NVRAM detection routines
This patch adds NVRAM detection routines for the 5717.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index 5994476a2508..ea57a3a4372c 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
| @@ -1027,8 +1027,10 @@ | |||
| 1027 | #define TG3_CPMU_HST_ACC 0x0000361c | 1027 | #define TG3_CPMU_HST_ACC 0x0000361c |
| 1028 | #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 | 1028 | #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000 |
| 1029 | #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 | 1029 | #define CPMU_HST_ACC_MACCLK_6_25 0x00130000 |
| 1030 | /* 0x3620 --> 0x3630 unused */ | 1030 | /* 0x3620 --> 0x362c unused */ |
| 1031 | 1031 | ||
| 1032 | #define TG3_CPMU_STATUS 0x0000362c | ||
| 1033 | #define TG3_CPMU_STATUS_PCIE_FUNC 0x20000000 | ||
| 1032 | #define TG3_CPMU_CLCK_STAT 0x00003630 | 1034 | #define TG3_CPMU_CLCK_STAT 0x00003630 |
| 1033 | #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 | 1035 | #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000 |
| 1034 | #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 | 1036 | #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 |
| @@ -1692,6 +1694,25 @@ | |||
| 1692 | #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 | 1694 | #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002 |
| 1693 | #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 | 1695 | #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001 |
| 1694 | #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 | 1696 | #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001 |
| 1697 | #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001 | ||
| 1698 | #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003 | ||
| 1699 | #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001 | ||
| 1700 | #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003 | ||
| 1701 | #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000 | ||
| 1702 | #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002 | ||
| 1703 | #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001 | ||
| 1704 | #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003 | ||
| 1705 | #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000 | ||
| 1706 | #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002 | ||
| 1707 | #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001 | ||
| 1708 | #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003 | ||
| 1709 | #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000 | ||
| 1710 | #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002 | ||
| 1711 | #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001 | ||
| 1712 | #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003 | ||
| 1713 | #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000 | ||
| 1714 | #define FLASH_5717VENDOR_ST_25USPT 0x03400002 | ||
| 1715 | #define FLASH_5717VENDOR_ST_45USPT 0x03400001 | ||
| 1695 | #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 | 1716 | #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000 |
| 1696 | #define FLASH_5752PAGE_SIZE_256 0x00000000 | 1717 | #define FLASH_5752PAGE_SIZE_256 0x00000000 |
| 1697 | #define FLASH_5752PAGE_SIZE_512 0x10000000 | 1718 | #define FLASH_5752PAGE_SIZE_512 0x10000000 |