diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2009-04-20 02:57:41 -0400 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2009-04-21 04:41:01 -0400 |
| commit | 33466d938f43ab65312466ba5472b9c6ee200cce (patch) | |
| tree | a84a6f6de32b2269006e70f5d4d04732940c8746 /drivers/net/tg3.h | |
| parent | df259d8cba7d7880dc04d34c7a6e0ce15fbc9644 (diff) | |
tg3: Prevent send BD corruption
On rare occasions, send BD corruptions can occur. This patch
fixes the problem by increasing the L1 entry threshold to 4
milliseconds.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
| -rw-r--r-- | drivers/net/tg3.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index afbabf283c51..f1016cb1a89a 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
| @@ -1697,6 +1697,8 @@ | |||
| 1697 | 1697 | ||
| 1698 | #define PCIE_PWR_MGMT_THRESH 0x00007d28 | 1698 | #define PCIE_PWR_MGMT_THRESH 0x00007d28 |
| 1699 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 | 1699 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 |
| 1700 | #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 | ||
| 1701 | #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 | ||
| 1700 | 1702 | ||
| 1701 | 1703 | ||
| 1702 | /* OTP bit definitions */ | 1704 | /* OTP bit definitions */ |