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authorMatt Carlson <mcarlson@broadcom.com>2010-08-02 07:26:05 -0400
committerDavid S. Miller <davem@davemloft.net>2010-08-02 18:46:32 -0400
commitf08aa1a8b8ff0738d42936c3ac8c5516848bca02 (patch)
treea2924ae50bd60a00c08cbdf11591a2938902293b /drivers/net/tg3.h
parent6ee7c0a0a5003abd4afd724f5c2f654fe7328c0a (diff)
tg3: Add phy-related preprocessor constants
This patch replaces some instances of hardcoded phy register values with preprocessor equivalents. Reviewed-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r--drivers/net/tg3.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 53b6def942bc..d40c380802b0 100644
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -2057,8 +2057,9 @@
2057#define MII_TG3_EXT_STAT 0x11 /* Extended status register */ 2057#define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2058#define MII_TG3_EXT_STAT_LPASS 0x0100 2058#define MII_TG3_EXT_STAT_LPASS 0x0100
2059 2059
2060#define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
2060#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ 2061#define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2061 2062#define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */
2062#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */ 2063#define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2063 2064
2064#define MII_TG3_DSP_TAP1 0x0001 2065#define MII_TG3_DSP_TAP1 0x0001
@@ -2066,6 +2067,7 @@
2066#define MII_TG3_DSP_AADJ1CH0 0x001f 2067#define MII_TG3_DSP_AADJ1CH0 0x001f
2067#define MII_TG3_DSP_AADJ1CH3 0x601f 2068#define MII_TG3_DSP_AADJ1CH3 0x601f
2068#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002 2069#define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2070#define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2069#define MII_TG3_DSP_EXP8 0x0f08 2071#define MII_TG3_DSP_EXP8 0x0f08
2070#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001 2072#define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2071#define MII_TG3_DSP_EXP8_AEDW 0x0200 2073#define MII_TG3_DSP_EXP8_AEDW 0x0200