diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2009-08-25 06:07:27 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-08-26 18:47:47 -0400 |
commit | 255ca311b650caece3ec4f78b88ef298664d561f (patch) | |
tree | cf26fdfb0fb9f5fba78bb59a82f37abb132d4b62 /drivers/net/tg3.h | |
parent | 521e6b90dd3f0392062845d7ef13e6e41bb99d8a (diff) |
tg3: Prevent tx BD corruption
This patch prevents a tx BD corruption bug by preventing the device from
powering down the PLL from L1 if the link speed is 10Mbps or 100Mbps.
The same bits are also used to prevent a system hang during chip reset
resulting from a complicated set of events that ultimately leads to
PCIe block register corruption.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Reviewed-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.h')
-rw-r--r-- | drivers/net/tg3.h | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h index c613cbb40c2d..bb8591ea3300 100644 --- a/drivers/net/tg3.h +++ b/drivers/net/tg3.h | |||
@@ -866,6 +866,7 @@ | |||
866 | #define RCVLPC_STATSCTRL_ENABLE 0x00000001 | 866 | #define RCVLPC_STATSCTRL_ENABLE 0x00000001 |
867 | #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 | 867 | #define RCVLPC_STATSCTRL_FASTUPD 0x00000002 |
868 | #define RCVLPC_STATS_ENABLE 0x00002018 | 868 | #define RCVLPC_STATS_ENABLE 0x00002018 |
869 | #define RCVLPC_STATSENAB_ASF_FIX 0x00000002 | ||
869 | #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 | 870 | #define RCVLPC_STATSENAB_DACK_FIX 0x00040000 |
870 | #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 | 871 | #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000 |
871 | #define RCVLPC_STATS_INCMASK 0x0000201c | 872 | #define RCVLPC_STATS_INCMASK 0x0000201c |
@@ -1704,7 +1705,12 @@ | |||
1704 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 | 1705 | #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00 |
1705 | #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 | 1706 | #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00 |
1706 | #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 | 1707 | #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000 |
1707 | /* 0x7d2c --> 0x7e70 unused */ | 1708 | /* 0x7d2c --> 0x7d54 unused */ |
1709 | |||
1710 | #define TG3_PCIE_LNKCTL 0x00007d54 | ||
1711 | #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008 | ||
1712 | #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080 | ||
1713 | /* 0x7d58 --> 0x7e70 unused */ | ||
1708 | 1714 | ||
1709 | #define TG3_PCIE_EIDLE_DELAY 0x00007e70 | 1715 | #define TG3_PCIE_EIDLE_DELAY 0x00007e70 |
1710 | #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f | 1716 | #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f |
@@ -2650,6 +2656,7 @@ struct tg3 { | |||
2650 | #define TG3_FLG3_PHY_ENABLE_APD 0x00001000 | 2656 | #define TG3_FLG3_PHY_ENABLE_APD 0x00001000 |
2651 | #define TG3_FLG3_5755_PLUS 0x00002000 | 2657 | #define TG3_FLG3_5755_PLUS 0x00002000 |
2652 | #define TG3_FLG3_NO_NVRAM 0x00004000 | 2658 | #define TG3_FLG3_NO_NVRAM 0x00004000 |
2659 | #define TG3_FLG3_TOGGLE_10_100_L1PLLPD 0x00008000 | ||
2653 | 2660 | ||
2654 | struct timer_list timer; | 2661 | struct timer_list timer; |
2655 | u16 timer_counter; | 2662 | u16 timer_counter; |