diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2010-08-02 07:25:57 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2010-08-02 18:46:27 -0400 |
commit | c885e824699f49bc3758a0dec760e189cd774e79 (patch) | |
tree | 28d730a3720231119fbff9999333e243a35295a6 /drivers/net/tg3.c | |
parent | 774ee7525ff94e597844c9f7f6a48938906df698 (diff) |
tg3: Create TG3_FLG3_5717_PLUS flag
This patch creates a TG3_FLG3_5717_PLUS flag to collectively describe
the set of changes in the ASIC that will apply to all future chip
revisions.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 72 |
1 files changed, 22 insertions, 50 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 12a2dd77c367..7892b0034c4f 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -7075,9 +7075,7 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
7075 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && | 7075 | if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && |
7076 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && | 7076 | tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 && |
7077 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | 7077 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
7078 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | 7078 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { |
7079 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 && | ||
7080 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) { | ||
7081 | val = tr32(0x7c00); | 7079 | val = tr32(0x7c00); |
7082 | 7080 | ||
7083 | tw32(0x7c00, val | (1 << 25)); | 7081 | tw32(0x7c00, val | (1 << 25)); |
@@ -7750,9 +7748,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7750 | if (err) | 7748 | if (err) |
7751 | return err; | 7749 | return err; |
7752 | 7750 | ||
7753 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 7751 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
7754 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
7755 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | ||
7756 | val = tr32(TG3PCI_DMA_RW_CTRL) & | 7752 | val = tr32(TG3PCI_DMA_RW_CTRL) & |
7757 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | 7753 | ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
7758 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) | 7754 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) |
@@ -7915,9 +7911,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7915 | BDINFO_FLAGS_DISABLED); | 7911 | BDINFO_FLAGS_DISABLED); |
7916 | } | 7912 | } |
7917 | 7913 | ||
7918 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 7914 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
7919 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
7920 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | ||
7921 | val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) | | 7915 | val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) | |
7922 | (TG3_RX_STD_DMA_SZ << 2); | 7916 | (TG3_RX_STD_DMA_SZ << 2); |
7923 | else | 7917 | else |
@@ -7934,9 +7928,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7934 | tp->rx_jumbo_pending : 0; | 7928 | tp->rx_jumbo_pending : 0; |
7935 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); | 7929 | tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx); |
7936 | 7930 | ||
7937 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 7931 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
7938 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
7939 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | ||
7940 | tw32(STD_REPLENISH_LWM, 32); | 7932 | tw32(STD_REPLENISH_LWM, 32); |
7941 | tw32(JMB_REPLENISH_LWM, 16); | 7933 | tw32(JMB_REPLENISH_LWM, 16); |
7942 | } | 7934 | } |
@@ -8626,9 +8618,7 @@ static int tg3_test_interrupt(struct tg3 *tp) | |||
8626 | * Turn off MSI one shot mode. Otherwise this test has no | 8618 | * Turn off MSI one shot mode. Otherwise this test has no |
8627 | * observable way to know whether the interrupt was delivered. | 8619 | * observable way to know whether the interrupt was delivered. |
8628 | */ | 8620 | */ |
8629 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 8621 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
8630 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
8631 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | ||
8632 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { | 8622 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8633 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; | 8623 | val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE; |
8634 | tw32(MSGINT_MODE, val); | 8624 | tw32(MSGINT_MODE, val); |
@@ -8671,9 +8661,7 @@ static int tg3_test_interrupt(struct tg3 *tp) | |||
8671 | 8661 | ||
8672 | if (intr_ok) { | 8662 | if (intr_ok) { |
8673 | /* Reenable MSI one shot mode. */ | 8663 | /* Reenable MSI one shot mode. */ |
8674 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 8664 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
8675 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
8676 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | ||
8677 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { | 8665 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8678 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; | 8666 | val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE; |
8679 | tw32(MSGINT_MODE, val); | 8667 | tw32(MSGINT_MODE, val); |
@@ -8968,11 +8956,8 @@ static int tg3_open(struct net_device *dev) | |||
8968 | goto err_out2; | 8956 | goto err_out2; |
8969 | } | 8957 | } |
8970 | 8958 | ||
8971 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | 8959 | if (!(tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
8972 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 && | 8960 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) { |
8973 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 && | ||
8974 | (tp->tg3_flags2 & TG3_FLG2_USING_MSI) && | ||
8975 | (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) { | ||
8976 | u32 val = tr32(PCIE_TRANSACTION_CFG); | 8961 | u32 val = tr32(PCIE_TRANSACTION_CFG); |
8977 | 8962 | ||
8978 | tw32(PCIE_TRANSACTION_CFG, | 8963 | tw32(PCIE_TRANSACTION_CFG, |
@@ -12987,6 +12972,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12987 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) | 12972 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) |
12988 | tp->pdev_peer = tg3_find_peer(tp); | 12973 | tp->pdev_peer = tg3_find_peer(tp); |
12989 | 12974 | ||
12975 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | ||
12976 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
12977 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | ||
12978 | tp->tg3_flags3 |= TG3_FLG3_5717_PLUS; | ||
12979 | |||
12990 | /* Intentionally exclude ASIC_REV_5906 */ | 12980 | /* Intentionally exclude ASIC_REV_5906 */ |
12991 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 12981 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
12992 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | 12982 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
@@ -12994,9 +12984,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
12994 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | 12984 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
12995 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 12985 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
12996 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | 12986 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
12997 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 12987 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
12998 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
12999 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | ||
13000 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; | 12988 | tp->tg3_flags3 |= TG3_FLG3_5755_PLUS; |
13001 | 12989 | ||
13002 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || | 12990 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || |
@@ -13026,9 +13014,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13026 | } | 13014 | } |
13027 | 13015 | ||
13028 | /* Determine TSO capabilities */ | 13016 | /* Determine TSO capabilities */ |
13029 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 13017 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
13030 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
13031 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | ||
13032 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; | 13018 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; |
13033 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | 13019 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
13034 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 13020 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
@@ -13064,9 +13050,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13064 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; | 13050 | tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; |
13065 | } | 13051 | } |
13066 | 13052 | ||
13067 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 13053 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
13068 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
13069 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | ||
13070 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; | 13054 | tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX; |
13071 | tp->irq_max = TG3_IRQ_MAX_VECS; | 13055 | tp->irq_max = TG3_IRQ_MAX_VECS; |
13072 | } | 13056 | } |
@@ -13081,9 +13065,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13081 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | 13065 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; |
13082 | } | 13066 | } |
13083 | 13067 | ||
13084 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 13068 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
13085 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
13086 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | ||
13087 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; | 13069 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; |
13088 | 13070 | ||
13089 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | 13071 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
@@ -13284,9 +13266,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13284 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || | 13266 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || |
13285 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || | 13267 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 || |
13286 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || | 13268 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || |
13287 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 13269 | (tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) |
13288 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
13289 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | ||
13290 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; | 13270 | tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT; |
13291 | 13271 | ||
13292 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). | 13272 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). |
@@ -13365,9 +13345,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13365 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && | 13345 | !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) && |
13366 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && | 13346 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 && |
13367 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && | 13347 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 && |
13368 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 && | 13348 | !(tp->tg3_flags3 & TG3_FLG3_5717_PLUS)) { |
13369 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5719 && | ||
13370 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) { | ||
13371 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 13349 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
13372 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || | 13350 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 || |
13373 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 13351 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || |
@@ -13704,9 +13682,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
13704 | #endif | 13682 | #endif |
13705 | #endif | 13683 | #endif |
13706 | 13684 | ||
13707 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 13685 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
13708 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
13709 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | ||
13710 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; | 13686 | val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT; |
13711 | goto out; | 13687 | goto out; |
13712 | } | 13688 | } |
@@ -13917,9 +13893,7 @@ static int __devinit tg3_test_dma(struct tg3 *tp) | |||
13917 | 13893 | ||
13918 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); | 13894 | tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl); |
13919 | 13895 | ||
13920 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 13896 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) |
13921 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
13922 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) | ||
13923 | goto out; | 13897 | goto out; |
13924 | 13898 | ||
13925 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | 13899 | if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
@@ -14117,9 +14091,7 @@ static void __devinit tg3_init_link_config(struct tg3 *tp) | |||
14117 | 14091 | ||
14118 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) | 14092 | static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) |
14119 | { | 14093 | { |
14120 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 || | 14094 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) { |
14121 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | ||
14122 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { | ||
14123 | tp->bufmgr_config.mbuf_read_dma_low_water = | 14095 | tp->bufmgr_config.mbuf_read_dma_low_water = |
14124 | DEFAULT_MB_RDMA_LOW_WATER_5705; | 14096 | DEFAULT_MB_RDMA_LOW_WATER_5705; |
14125 | tp->bufmgr_config.mbuf_mac_rx_low_water = | 14097 | tp->bufmgr_config.mbuf_mac_rx_low_water = |