diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2011-01-25 10:58:48 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-01-25 22:38:16 -0500 |
commit | 4d163b75e979833979cc401ae433cb1d7743d57e (patch) | |
tree | ab01299fe86ee6566c742f056a00ebc859160a8e /drivers/net/tg3.c | |
parent | b4495ed88b782febddfa5bb99c87d75724520ecf (diff) |
tg3: Fix 5719 A0 tx completion bug
The 5719 A0 has a bug that manifests itself as if the chipset were
reordering memory writes. The best known way to solve this problem is
to turn off LSO and jumbo frames.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index b944cc64a409..d6d081716af0 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -8108,8 +8108,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
8108 | /* Program the jumbo buffer descriptor ring control | 8108 | /* Program the jumbo buffer descriptor ring control |
8109 | * blocks on those devices that have them. | 8109 | * blocks on those devices that have them. |
8110 | */ | 8110 | */ |
8111 | if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && | 8111 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0 || |
8112 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) { | 8112 | ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && |
8113 | !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))) { | ||
8113 | /* Setup replenish threshold. */ | 8114 | /* Setup replenish threshold. */ |
8114 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); | 8115 | tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8); |
8115 | 8116 | ||
@@ -13329,7 +13330,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13329 | } | 13330 | } |
13330 | 13331 | ||
13331 | /* Determine TSO capabilities */ | 13332 | /* Determine TSO capabilities */ |
13332 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) | 13333 | if (tp->pci_chip_rev_id == CHIPREV_ID_5719_A0) |
13334 | ; /* Do nothing. HW bug. */ | ||
13335 | else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) | ||
13333 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; | 13336 | tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3; |
13334 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || | 13337 | else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) || |
13335 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) | 13338 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) |
@@ -13380,7 +13383,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
13380 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; | 13383 | tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG; |
13381 | } | 13384 | } |
13382 | 13385 | ||
13383 | if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) | 13386 | if ((tp->tg3_flags3 & TG3_FLG3_5717_PLUS) && |
13387 | tp->pci_chip_rev_id != CHIPREV_ID_5719_A0) | ||
13384 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; | 13388 | tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG; |
13385 | 13389 | ||
13386 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || | 13390 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |