aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.c
diff options
context:
space:
mode:
authorMichael Chan <mchan@broadcom.com>2005-07-25 15:29:19 -0400
committerDavid S. Miller <davem@davemloft.net>2005-07-25 15:29:19 -0400
commit4cf78e4fb678807e3f8265c9e9031a84f5c601f0 (patch)
treee5acc4451c7e9f59125119174b05ca95c652c2df /drivers/net/tg3.c
parent6b6a93c6876ea1c530d5d3f68e3678093a27fab0 (diff)
[TG3]: add 5780 basic support
Add 5780 PCI IDs, chip IDs, and other basic support. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c53
1 files changed, 48 insertions, 5 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 54640686e983..b01f6a07e5e7 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -221,6 +221,10 @@ static struct pci_device_id tg3_pci_tbl[] = {
221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 221 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F, 222 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,
223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,
227 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
224 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781, 228 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,
225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 229 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
226 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX, 230 { PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
@@ -508,6 +512,9 @@ static void tg3_switch_clocks(struct tg3 *tp)
508 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL); 512 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
509 u32 orig_clock_ctrl; 513 u32 orig_clock_ctrl;
510 514
515 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
516 return;
517
511 orig_clock_ctrl = clock_ctrl; 518 orig_clock_ctrl = clock_ctrl;
512 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | 519 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
513 CLOCK_CTRL_CLKRUN_OENABLE | 520 CLOCK_CTRL_CLKRUN_OENABLE |
@@ -1145,6 +1152,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1145 CLOCK_CTRL_ALTCLK | 1152 CLOCK_CTRL_ALTCLK |
1146 CLOCK_CTRL_PWRDOWN_PLL133); 1153 CLOCK_CTRL_PWRDOWN_PLL133);
1147 udelay(40); 1154 udelay(40);
1155 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
1156 /* do nothing */
1148 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && 1157 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1149 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) { 1158 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1150 u32 newbits1, newbits2; 1159 u32 newbits1, newbits2;
@@ -4056,7 +4065,30 @@ static int tg3_chip_reset(struct tg3 *tp)
4056 val &= ~PCIX_CAPS_RELAXED_ORDERING; 4065 val &= ~PCIX_CAPS_RELAXED_ORDERING;
4057 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val); 4066 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4058 4067
4059 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE); 4068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
4069 u32 val;
4070
4071 /* Chip reset on 5780 will reset MSI enable bit,
4072 * so need to restore it.
4073 */
4074 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4075 u16 ctrl;
4076
4077 pci_read_config_word(tp->pdev,
4078 tp->msi_cap + PCI_MSI_FLAGS,
4079 &ctrl);
4080 pci_write_config_word(tp->pdev,
4081 tp->msi_cap + PCI_MSI_FLAGS,
4082 ctrl | PCI_MSI_FLAGS_ENABLE);
4083 val = tr32(MSGINT_MODE);
4084 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4085 }
4086
4087 val = tr32(MEMARB_MODE);
4088 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4089
4090 } else
4091 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4060 4092
4061 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) { 4093 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4062 tg3_stop_fw(tp); 4094 tg3_stop_fw(tp);
@@ -5683,7 +5715,8 @@ static int tg3_reset_hw(struct tg3 *tp)
5683 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK); 5715 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
5684 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK); 5716 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
5685 5717
5686 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) 5718 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
5719 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))
5687 limit = 8; 5720 limit = 8;
5688 else 5721 else
5689 limit = 16; 5722 limit = 16;
@@ -8928,6 +8961,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8928 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW) 8961 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
8929 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0; 8962 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
8930 8963
8964 /* Find msi capability. */
8965 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8966 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
8967
8931 /* Initialize misc host control in PCI block. */ 8968 /* Initialize misc host control in PCI block. */
8932 tp->misc_host_ctrl |= (misc_ctrl_reg & 8969 tp->misc_host_ctrl |= (misc_ctrl_reg &
8933 MISC_HOST_CTRL_CHIPREV); 8970 MISC_HOST_CTRL_CHIPREV);
@@ -8943,7 +8980,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8943 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; 8980 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
8944 8981
8945 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 8982 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8946 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) 8983 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
8984 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8947 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS; 8985 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
8948 8986
8949 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || 8987 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
@@ -9305,8 +9343,9 @@ static int __devinit tg3_get_device_address(struct tg3 *tp)
9305#endif 9343#endif
9306 9344
9307 mac_offset = 0x7c; 9345 mac_offset = 0x7c;
9308 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 && 9346 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
9309 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) { 9347 !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||
9348 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
9310 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID) 9349 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
9311 mac_offset = 0xcc; 9350 mac_offset = 0xcc;
9312 if (tg3_nvram_lock(tp)) 9351 if (tg3_nvram_lock(tp))
@@ -9620,6 +9659,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
9620 9659
9621 /* Set bit 23 to enable PCIX hw bug fix */ 9660 /* Set bit 23 to enable PCIX hw bug fix */
9622 tp->dma_rwctrl |= 0x009f0000; 9661 tp->dma_rwctrl |= 0x009f0000;
9662 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
9663 /* 5780 always in PCIX mode */
9664 tp->dma_rwctrl |= 0x00144000;
9623 } else { 9665 } else {
9624 tp->dma_rwctrl |= 0x001b000f; 9666 tp->dma_rwctrl |= 0x001b000f;
9625 } 9667 }
@@ -9803,6 +9845,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp)
9803 case PHY_ID_BCM5705: return "5705"; 9845 case PHY_ID_BCM5705: return "5705";
9804 case PHY_ID_BCM5750: return "5750"; 9846 case PHY_ID_BCM5750: return "5750";
9805 case PHY_ID_BCM5752: return "5752"; 9847 case PHY_ID_BCM5752: return "5752";
9848 case PHY_ID_BCM5780: return "5780";
9806 case PHY_ID_BCM8002: return "8002/serdes"; 9849 case PHY_ID_BCM8002: return "8002/serdes";
9807 case 0: return "serdes"; 9850 case 0: return "serdes";
9808 default: return "unknown"; 9851 default: return "unknown";