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authorMatt Carlson <mcarlson@broadcom.com>2009-11-02 09:24:02 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-03 02:39:00 -0500
commitf40386c8452f9eead9c5906bfffaaf59f3dc748f (patch)
tree9b58866117c15dc257e39a448829f472eaad02ce /drivers/net/tg3.c
parent92c6b8d16a36df3f28b2537bed2a56491fb08f11 (diff)
tg3: Fix disappearing 57780 devices
Under certain power saving conditions, 57780 asic rev devices might disappear from the system. The fix is to disallow the PCIe PLL from powering down. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c24
1 files changed, 2 insertions, 22 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a7a582e37469..b3c5d74022f2 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -3243,15 +3243,6 @@ relink:
3243 pci_write_config_word(tp->pdev, 3243 pci_write_config_word(tp->pdev,
3244 tp->pcie_cap + PCI_EXP_LNKCTL, 3244 tp->pcie_cap + PCI_EXP_LNKCTL,
3245 newlnkctl); 3245 newlnkctl);
3246 } else if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) {
3247 u32 newreg, oldreg = tr32(TG3_PCIE_LNKCTL);
3248 if (tp->link_config.active_speed == SPEED_100 ||
3249 tp->link_config.active_speed == SPEED_10)
3250 newreg = oldreg & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3251 else
3252 newreg = oldreg | TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
3253 if (newreg != oldreg)
3254 tw32(TG3_PCIE_LNKCTL, newreg);
3255 } 3246 }
3256 3247
3257 if (current_link_up != netif_carrier_ok(tp->dev)) { 3248 if (current_link_up != netif_carrier_ok(tp->dev)) {
@@ -7180,15 +7171,9 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7180 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS); 7171 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7181 7172
7182 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR); 7173 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7183 }
7184 7174
7185 if (tp->tg3_flags3 & TG3_FLG3_TOGGLE_10_100_L1PLLPD) { 7175 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7186 val = tr32(TG3_PCIE_LNKCTL); 7176 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7187 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG)
7188 val |= TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7189 else
7190 val &= ~TG3_PCIE_LNKCTL_L1_PLL_PD_DIS;
7191 tw32(TG3_PCIE_LNKCTL, val);
7192 } 7177 }
7193 7178
7194 /* This works around an issue with Athlon chipsets on 7179 /* This works around an issue with Athlon chipsets on
@@ -12951,11 +12936,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
12951 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) 12936 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
12952 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB; 12937 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
12953 12938
12954 if ((tp->pci_chip_rev_id == CHIPREV_ID_57780_A1 &&
12955 tr32(RCVLPC_STATS_ENABLE) & RCVLPC_STATSENAB_ASF_FIX) ||
12956 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0)
12957 tp->tg3_flags3 |= TG3_FLG3_TOGGLE_10_100_L1PLLPD;
12958
12959 err = tg3_mdio_init(tp); 12939 err = tg3_mdio_init(tp);
12960 if (err) 12940 if (err)
12961 return err; 12941 return err;