diff options
author | Stephen Hemminger <shemminger@vyatta.com> | 2008-04-16 19:37:28 -0400 |
---|---|---|
committer | Jeff Garzik <jgarzik@redhat.com> | 2008-05-22 14:12:30 -0400 |
commit | 855e1111f3806905b410b745e696fec4f5dac724 (patch) | |
tree | 935763b5e9190f30433ef534d5410d1d3d1301b8 /drivers/net/tg3.c | |
parent | 92fbc1c146d1d358c1ecc4e38361089ff929a02c (diff) |
tg3: remove unneeded semicolons
Remove extraneous semicolons after switch and conditional statements.
Signed-off-by: Stephen Hemminger <shemminger@vyatta.com>
Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 07b3f77e7626..ae11c6724766 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -1480,7 +1480,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) | |||
1480 | "requested.\n", | 1480 | "requested.\n", |
1481 | tp->dev->name, state); | 1481 | tp->dev->name, state); |
1482 | return -EINVAL; | 1482 | return -EINVAL; |
1483 | }; | 1483 | } |
1484 | 1484 | ||
1485 | power_control |= PCI_PM_CTRL_PME_ENABLE; | 1485 | power_control |= PCI_PM_CTRL_PME_ENABLE; |
1486 | 1486 | ||
@@ -1906,7 +1906,7 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 | |||
1906 | *speed = SPEED_INVALID; | 1906 | *speed = SPEED_INVALID; |
1907 | *duplex = DUPLEX_INVALID; | 1907 | *duplex = DUPLEX_INVALID; |
1908 | break; | 1908 | break; |
1909 | }; | 1909 | } |
1910 | } | 1910 | } |
1911 | 1911 | ||
1912 | static void tg3_phy_copper_begin(struct tg3 *tp) | 1912 | static void tg3_phy_copper_begin(struct tg3 *tp) |
@@ -2018,7 +2018,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp) | |||
2018 | case SPEED_1000: | 2018 | case SPEED_1000: |
2019 | bmcr |= TG3_BMCR_SPEED1000; | 2019 | bmcr |= TG3_BMCR_SPEED1000; |
2020 | break; | 2020 | break; |
2021 | }; | 2021 | } |
2022 | 2022 | ||
2023 | if (tp->link_config.duplex == DUPLEX_FULL) | 2023 | if (tp->link_config.duplex == DUPLEX_FULL) |
2024 | bmcr |= BMCR_FULLDPLX; | 2024 | bmcr |= BMCR_FULLDPLX; |
@@ -2716,7 +2716,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |||
2716 | default: | 2716 | default: |
2717 | ret = ANEG_FAILED; | 2717 | ret = ANEG_FAILED; |
2718 | break; | 2718 | break; |
2719 | }; | 2719 | } |
2720 | 2720 | ||
2721 | return ret; | 2721 | return ret; |
2722 | } | 2722 | } |
@@ -3558,7 +3558,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key, | |||
3558 | 3558 | ||
3559 | default: | 3559 | default: |
3560 | return -EINVAL; | 3560 | return -EINVAL; |
3561 | }; | 3561 | } |
3562 | 3562 | ||
3563 | /* Do not overwrite any of the map or rp information | 3563 | /* Do not overwrite any of the map or rp information |
3564 | * until we are sure we can commit to a new buffer. | 3564 | * until we are sure we can commit to a new buffer. |
@@ -3618,7 +3618,7 @@ static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key, | |||
3618 | 3618 | ||
3619 | default: | 3619 | default: |
3620 | return; | 3620 | return; |
3621 | }; | 3621 | } |
3622 | 3622 | ||
3623 | dest_map->skb = src_map->skb; | 3623 | dest_map->skb = src_map->skb; |
3624 | pci_unmap_addr_set(dest_map, mapping, | 3624 | pci_unmap_addr_set(dest_map, mapping, |
@@ -4961,7 +4961,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int | |||
4961 | 4961 | ||
4962 | default: | 4962 | default: |
4963 | break; | 4963 | break; |
4964 | }; | 4964 | } |
4965 | } | 4965 | } |
4966 | 4966 | ||
4967 | val = tr32(ofs); | 4967 | val = tr32(ofs); |
@@ -5203,7 +5203,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |||
5203 | 5203 | ||
5204 | default: | 5204 | default: |
5205 | break; | 5205 | break; |
5206 | }; | 5206 | } |
5207 | } | 5207 | } |
5208 | 5208 | ||
5209 | if (kind == RESET_KIND_INIT || | 5209 | if (kind == RESET_KIND_INIT || |
@@ -5228,7 +5228,7 @@ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |||
5228 | 5228 | ||
5229 | default: | 5229 | default: |
5230 | break; | 5230 | break; |
5231 | }; | 5231 | } |
5232 | } | 5232 | } |
5233 | 5233 | ||
5234 | if (kind == RESET_KIND_SHUTDOWN) | 5234 | if (kind == RESET_KIND_SHUTDOWN) |
@@ -5257,7 +5257,7 @@ static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |||
5257 | 5257 | ||
5258 | default: | 5258 | default: |
5259 | break; | 5259 | break; |
5260 | }; | 5260 | } |
5261 | } | 5261 | } |
5262 | } | 5262 | } |
5263 | 5263 | ||
@@ -7282,7 +7282,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7282 | 7282 | ||
7283 | default: | 7283 | default: |
7284 | break; | 7284 | break; |
7285 | }; | 7285 | } |
7286 | 7286 | ||
7287 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | 7287 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7288 | /* Write our heartbeat update interval to APE. */ | 7288 | /* Write our heartbeat update interval to APE. */ |
@@ -10879,7 +10879,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |||
10879 | LED_CTRL_MODE_PHY_2); | 10879 | LED_CTRL_MODE_PHY_2); |
10880 | break; | 10880 | break; |
10881 | 10881 | ||
10882 | }; | 10882 | } |
10883 | 10883 | ||
10884 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 10884 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
10885 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | 10885 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && |
@@ -12178,7 +12178,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
12178 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | 12178 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | |
12179 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | 12179 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); |
12180 | break; | 12180 | break; |
12181 | }; | 12181 | } |
12182 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | 12182 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
12183 | switch (cacheline_size) { | 12183 | switch (cacheline_size) { |
12184 | case 16: | 12184 | case 16: |
@@ -12195,7 +12195,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
12195 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | 12195 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; |
12196 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | 12196 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; |
12197 | break; | 12197 | break; |
12198 | }; | 12198 | } |
12199 | } else { | 12199 | } else { |
12200 | switch (cacheline_size) { | 12200 | switch (cacheline_size) { |
12201 | case 16: | 12201 | case 16: |
@@ -12239,7 +12239,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
12239 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | 12239 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | |
12240 | DMA_RWCTRL_WRITE_BNDRY_1024); | 12240 | DMA_RWCTRL_WRITE_BNDRY_1024); |
12241 | break; | 12241 | break; |
12242 | }; | 12242 | } |
12243 | } | 12243 | } |
12244 | 12244 | ||
12245 | out: | 12245 | out: |
@@ -12599,7 +12599,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp) | |||
12599 | case PHY_ID_BCM8002: return "8002/serdes"; | 12599 | case PHY_ID_BCM8002: return "8002/serdes"; |
12600 | case 0: return "serdes"; | 12600 | case 0: return "serdes"; |
12601 | default: return "unknown"; | 12601 | default: return "unknown"; |
12602 | }; | 12602 | } |
12603 | } | 12603 | } |
12604 | 12604 | ||
12605 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) | 12605 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |