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authorMichael Chan <mchan@broadcom.com>2006-04-29 21:56:34 -0400
committerDavid S. Miller <davem@davemloft.net>2006-04-29 21:56:34 -0400
commitc424cb249dae10fb7f118f89091f1329b62b92f4 (patch)
tree71fec6de971313c0add0b0c0b7580c736e0f12cb /drivers/net/tg3.c
parentc8e1e82b6a97ad44517517aa58b7b794ead0bf33 (diff)
[TG3]: Add phy workaround
Add some PHY workaround code to reduce jitter on some PHYs. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c17
1 files changed, 13 insertions, 4 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index a28accbfcdf7..a30734061700 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1030,6 +1030,12 @@ out:
1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2); 1030 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1031 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400); 1031 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1032 } 1032 }
1033 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1034 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1035 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1036 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1037 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1038 }
1033 /* Set Extended packet length bit (bit 14) on all chips that */ 1039 /* Set Extended packet length bit (bit 14) on all chips that */
1034 /* support jumbo frames */ 1040 /* support jumbo frames */
1035 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 1041 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
@@ -10360,10 +10366,13 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10360 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) 10366 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10361 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; 10367 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10362 10368
10363 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) && 10369 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10364 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) && 10370 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10365 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787)) 10371 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
10366 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 10372 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10373 else
10374 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10375 }
10367 10376
10368 tp->coalesce_mode = 0; 10377 tp->coalesce_mode = 0;
10369 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX && 10378 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&