diff options
author | David S. Miller <davem@davemloft.net> | 2008-05-29 06:31:03 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-05-29 06:31:03 -0400 |
commit | a5b17df04c4ad8f25fc598fce37fccb4b387c94c (patch) | |
tree | 2d0084f6db86362eb067b617ff8470f255ba37e7 /drivers/net/tg3.c | |
parent | b79eeeb9e48457579cb742cd02e162fcd673c4a3 (diff) | |
parent | c03571a3e22b821e5be7bda7b166c4554770f489 (diff) |
Merge branch 'upstream-next-davem' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 32 |
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 20a8e3996407..d9f248f23b97 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -2013,7 +2013,7 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state) | |||
2013 | "requested.\n", | 2013 | "requested.\n", |
2014 | tp->dev->name, state); | 2014 | tp->dev->name, state); |
2015 | return -EINVAL; | 2015 | return -EINVAL; |
2016 | }; | 2016 | } |
2017 | 2017 | ||
2018 | power_control |= PCI_PM_CTRL_PME_ENABLE; | 2018 | power_control |= PCI_PM_CTRL_PME_ENABLE; |
2019 | 2019 | ||
@@ -2272,7 +2272,7 @@ static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 | |||
2272 | *speed = SPEED_INVALID; | 2272 | *speed = SPEED_INVALID; |
2273 | *duplex = DUPLEX_INVALID; | 2273 | *duplex = DUPLEX_INVALID; |
2274 | break; | 2274 | break; |
2275 | }; | 2275 | } |
2276 | } | 2276 | } |
2277 | 2277 | ||
2278 | static void tg3_phy_copper_begin(struct tg3 *tp) | 2278 | static void tg3_phy_copper_begin(struct tg3 *tp) |
@@ -2384,7 +2384,7 @@ static void tg3_phy_copper_begin(struct tg3 *tp) | |||
2384 | case SPEED_1000: | 2384 | case SPEED_1000: |
2385 | bmcr |= TG3_BMCR_SPEED1000; | 2385 | bmcr |= TG3_BMCR_SPEED1000; |
2386 | break; | 2386 | break; |
2387 | }; | 2387 | } |
2388 | 2388 | ||
2389 | if (tp->link_config.duplex == DUPLEX_FULL) | 2389 | if (tp->link_config.duplex == DUPLEX_FULL) |
2390 | bmcr |= BMCR_FULLDPLX; | 2390 | bmcr |= BMCR_FULLDPLX; |
@@ -3082,7 +3082,7 @@ static int tg3_fiber_aneg_smachine(struct tg3 *tp, | |||
3082 | default: | 3082 | default: |
3083 | ret = ANEG_FAILED; | 3083 | ret = ANEG_FAILED; |
3084 | break; | 3084 | break; |
3085 | }; | 3085 | } |
3086 | 3086 | ||
3087 | return ret; | 3087 | return ret; |
3088 | } | 3088 | } |
@@ -3924,7 +3924,7 @@ static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key, | |||
3924 | 3924 | ||
3925 | default: | 3925 | default: |
3926 | return -EINVAL; | 3926 | return -EINVAL; |
3927 | }; | 3927 | } |
3928 | 3928 | ||
3929 | /* Do not overwrite any of the map or rp information | 3929 | /* Do not overwrite any of the map or rp information |
3930 | * until we are sure we can commit to a new buffer. | 3930 | * until we are sure we can commit to a new buffer. |
@@ -3984,7 +3984,7 @@ static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key, | |||
3984 | 3984 | ||
3985 | default: | 3985 | default: |
3986 | return; | 3986 | return; |
3987 | }; | 3987 | } |
3988 | 3988 | ||
3989 | dest_map->skb = src_map->skb; | 3989 | dest_map->skb = src_map->skb; |
3990 | pci_unmap_addr_set(dest_map, mapping, | 3990 | pci_unmap_addr_set(dest_map, mapping, |
@@ -5347,7 +5347,7 @@ static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int | |||
5347 | 5347 | ||
5348 | default: | 5348 | default: |
5349 | break; | 5349 | break; |
5350 | }; | 5350 | } |
5351 | } | 5351 | } |
5352 | 5352 | ||
5353 | val = tr32(ofs); | 5353 | val = tr32(ofs); |
@@ -5589,7 +5589,7 @@ static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind) | |||
5589 | 5589 | ||
5590 | default: | 5590 | default: |
5591 | break; | 5591 | break; |
5592 | }; | 5592 | } |
5593 | } | 5593 | } |
5594 | 5594 | ||
5595 | if (kind == RESET_KIND_INIT || | 5595 | if (kind == RESET_KIND_INIT || |
@@ -5614,7 +5614,7 @@ static void tg3_write_sig_post_reset(struct tg3 *tp, int kind) | |||
5614 | 5614 | ||
5615 | default: | 5615 | default: |
5616 | break; | 5616 | break; |
5617 | }; | 5617 | } |
5618 | } | 5618 | } |
5619 | 5619 | ||
5620 | if (kind == RESET_KIND_SHUTDOWN) | 5620 | if (kind == RESET_KIND_SHUTDOWN) |
@@ -5643,7 +5643,7 @@ static void tg3_write_sig_legacy(struct tg3 *tp, int kind) | |||
5643 | 5643 | ||
5644 | default: | 5644 | default: |
5645 | break; | 5645 | break; |
5646 | }; | 5646 | } |
5647 | } | 5647 | } |
5648 | } | 5648 | } |
5649 | 5649 | ||
@@ -7677,7 +7677,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7677 | 7677 | ||
7678 | default: | 7678 | default: |
7679 | break; | 7679 | break; |
7680 | }; | 7680 | } |
7681 | 7681 | ||
7682 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) | 7682 | if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) |
7683 | /* Write our heartbeat update interval to APE. */ | 7683 | /* Write our heartbeat update interval to APE. */ |
@@ -11379,7 +11379,7 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp) | |||
11379 | LED_CTRL_MODE_PHY_2); | 11379 | LED_CTRL_MODE_PHY_2); |
11380 | break; | 11380 | break; |
11381 | 11381 | ||
11382 | }; | 11382 | } |
11383 | 11383 | ||
11384 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || | 11384 | if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 || |
11385 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && | 11385 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) && |
@@ -12690,7 +12690,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
12690 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | | 12690 | val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX | |
12691 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); | 12691 | DMA_RWCTRL_WRITE_BNDRY_384_PCIX); |
12692 | break; | 12692 | break; |
12693 | }; | 12693 | } |
12694 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { | 12694 | } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) { |
12695 | switch (cacheline_size) { | 12695 | switch (cacheline_size) { |
12696 | case 16: | 12696 | case 16: |
@@ -12707,7 +12707,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
12707 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; | 12707 | val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE; |
12708 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; | 12708 | val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE; |
12709 | break; | 12709 | break; |
12710 | }; | 12710 | } |
12711 | } else { | 12711 | } else { |
12712 | switch (cacheline_size) { | 12712 | switch (cacheline_size) { |
12713 | case 16: | 12713 | case 16: |
@@ -12751,7 +12751,7 @@ static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val) | |||
12751 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | | 12751 | val |= (DMA_RWCTRL_READ_BNDRY_1024 | |
12752 | DMA_RWCTRL_WRITE_BNDRY_1024); | 12752 | DMA_RWCTRL_WRITE_BNDRY_1024); |
12753 | break; | 12753 | break; |
12754 | }; | 12754 | } |
12755 | } | 12755 | } |
12756 | 12756 | ||
12757 | out: | 12757 | out: |
@@ -13111,7 +13111,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp) | |||
13111 | case PHY_ID_BCM8002: return "8002/serdes"; | 13111 | case PHY_ID_BCM8002: return "8002/serdes"; |
13112 | case 0: return "serdes"; | 13112 | case 0: return "serdes"; |
13113 | default: return "unknown"; | 13113 | default: return "unknown"; |
13114 | }; | 13114 | } |
13115 | } | 13115 | } |
13116 | 13116 | ||
13117 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) | 13117 | static char * __devinit tg3_bus_string(struct tg3 *tp, char *str) |