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authorMatt Carlson <mcarlson@broadcom.com>2011-04-05 10:22:47 -0400
committerDavid S. Miller <davem@davemloft.net>2011-04-06 14:29:08 -0400
commit9b91b5f178605dd0d4debcbc184a3e97fcb4f591 (patch)
treef8fd3eb0d0658862a8933c58f137fd2a6afe59e8 /drivers/net/tg3.c
parentd78b59f5d18bf064abae2fa5bc87f00545e2160a (diff)
tg3: Add 5720 NVRAM decoding
The 5720 implements its own NVRAM pin strapping scheme. This patch adds the required support. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c117
1 files changed, 116 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 53a1209d4f9c..a079e745a071 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -11889,6 +11889,118 @@ static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11889 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS; 11889 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11890} 11890}
11891 11891
11892static void __devinit tg3_get_5720_nvram_info(struct tg3 *tp)
11893{
11894 u32 nvcfg1, nvmpinstrp;
11895
11896 nvcfg1 = tr32(NVRAM_CFG1);
11897 nvmpinstrp = nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK;
11898
11899 switch (nvmpinstrp) {
11900 case FLASH_5720_EEPROM_HD:
11901 case FLASH_5720_EEPROM_LD:
11902 tp->nvram_jedecnum = JEDEC_ATMEL;
11903 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11904
11905 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11906 tw32(NVRAM_CFG1, nvcfg1);
11907 if (nvmpinstrp == FLASH_5720_EEPROM_HD)
11908 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11909 else
11910 tp->nvram_pagesize = ATMEL_AT24C02_CHIP_SIZE;
11911 return;
11912 case FLASH_5720VENDOR_M_ATMEL_DB011D:
11913 case FLASH_5720VENDOR_A_ATMEL_DB011B:
11914 case FLASH_5720VENDOR_A_ATMEL_DB011D:
11915 case FLASH_5720VENDOR_M_ATMEL_DB021D:
11916 case FLASH_5720VENDOR_A_ATMEL_DB021B:
11917 case FLASH_5720VENDOR_A_ATMEL_DB021D:
11918 case FLASH_5720VENDOR_M_ATMEL_DB041D:
11919 case FLASH_5720VENDOR_A_ATMEL_DB041B:
11920 case FLASH_5720VENDOR_A_ATMEL_DB041D:
11921 case FLASH_5720VENDOR_M_ATMEL_DB081D:
11922 case FLASH_5720VENDOR_A_ATMEL_DB081D:
11923 case FLASH_5720VENDOR_ATMEL_45USPT:
11924 tp->nvram_jedecnum = JEDEC_ATMEL;
11925 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11926 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11927
11928 switch (nvmpinstrp) {
11929 case FLASH_5720VENDOR_M_ATMEL_DB021D:
11930 case FLASH_5720VENDOR_A_ATMEL_DB021B:
11931 case FLASH_5720VENDOR_A_ATMEL_DB021D:
11932 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11933 break;
11934 case FLASH_5720VENDOR_M_ATMEL_DB041D:
11935 case FLASH_5720VENDOR_A_ATMEL_DB041B:
11936 case FLASH_5720VENDOR_A_ATMEL_DB041D:
11937 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11938 break;
11939 case FLASH_5720VENDOR_M_ATMEL_DB081D:
11940 case FLASH_5720VENDOR_A_ATMEL_DB081D:
11941 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11942 break;
11943 default:
11944 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11945 break;
11946 }
11947 break;
11948 case FLASH_5720VENDOR_M_ST_M25PE10:
11949 case FLASH_5720VENDOR_M_ST_M45PE10:
11950 case FLASH_5720VENDOR_A_ST_M25PE10:
11951 case FLASH_5720VENDOR_A_ST_M45PE10:
11952 case FLASH_5720VENDOR_M_ST_M25PE20:
11953 case FLASH_5720VENDOR_M_ST_M45PE20:
11954 case FLASH_5720VENDOR_A_ST_M25PE20:
11955 case FLASH_5720VENDOR_A_ST_M45PE20:
11956 case FLASH_5720VENDOR_M_ST_M25PE40:
11957 case FLASH_5720VENDOR_M_ST_M45PE40:
11958 case FLASH_5720VENDOR_A_ST_M25PE40:
11959 case FLASH_5720VENDOR_A_ST_M45PE40:
11960 case FLASH_5720VENDOR_M_ST_M25PE80:
11961 case FLASH_5720VENDOR_M_ST_M45PE80:
11962 case FLASH_5720VENDOR_A_ST_M25PE80:
11963 case FLASH_5720VENDOR_A_ST_M45PE80:
11964 case FLASH_5720VENDOR_ST_25USPT:
11965 case FLASH_5720VENDOR_ST_45USPT:
11966 tp->nvram_jedecnum = JEDEC_ST;
11967 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11968 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11969
11970 switch (nvmpinstrp) {
11971 case FLASH_5720VENDOR_M_ST_M25PE20:
11972 case FLASH_5720VENDOR_M_ST_M45PE20:
11973 case FLASH_5720VENDOR_A_ST_M25PE20:
11974 case FLASH_5720VENDOR_A_ST_M45PE20:
11975 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11976 break;
11977 case FLASH_5720VENDOR_M_ST_M25PE40:
11978 case FLASH_5720VENDOR_M_ST_M45PE40:
11979 case FLASH_5720VENDOR_A_ST_M25PE40:
11980 case FLASH_5720VENDOR_A_ST_M45PE40:
11981 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11982 break;
11983 case FLASH_5720VENDOR_M_ST_M25PE80:
11984 case FLASH_5720VENDOR_M_ST_M45PE80:
11985 case FLASH_5720VENDOR_A_ST_M25PE80:
11986 case FLASH_5720VENDOR_A_ST_M45PE80:
11987 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11988 break;
11989 default:
11990 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11991 break;
11992 }
11993 break;
11994 default:
11995 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11996 return;
11997 }
11998
11999 tg3_nvram_get_pagesize(tp, nvcfg1);
12000 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
12001 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
12002}
12003
11892/* Chips other than 5700/5701 use the NVRAM for fetching info. */ 12004/* Chips other than 5700/5701 use the NVRAM for fetching info. */
11893static void __devinit tg3_nvram_init(struct tg3 *tp) 12005static void __devinit tg3_nvram_init(struct tg3 *tp)
11894{ 12006{
@@ -11933,8 +12045,11 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
11933 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 || 12045 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11934 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) 12046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11935 tg3_get_57780_nvram_info(tp); 12047 tg3_get_57780_nvram_info(tp);
11936 else if (tp->tg3_flags3 & TG3_FLG3_5717_PLUS) 12048 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
12049 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
11937 tg3_get_5717_nvram_info(tp); 12050 tg3_get_5717_nvram_info(tp);
12051 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
12052 tg3_get_5720_nvram_info(tp);
11938 else 12053 else
11939 tg3_get_nvram_info(tp); 12054 tg3_get_nvram_info(tp);
11940 12055
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-25 18:22:09 -0500