diff options
| author | Matt Carlson <mcarlson@broadcom.com> | 2010-11-24 03:31:45 -0500 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2010-11-24 14:06:16 -0500 |
| commit | 5093eedc8bdfd7d906836a44a248f66a99e27d22 (patch) | |
| tree | c0767ebe53f1d628b8e80d9e77d5eb7938f0dc1c /drivers/net/tg3.c | |
| parent | 2fe66ec242d3f76e3b0101f36419e7e5405bcff3 (diff) | |
tg3: Apply 10Mbps fix to all 57765 revisions
Commit a977dbe8445b8a81d6127c4aa9112a2c29a1a008, entitled
"tg3: Reduce 57765 core clock when link at 10Mbps" needs to be applied
to all revisions of the 57765 asic rev, not just the A0 revision.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
| -rw-r--r-- | drivers/net/tg3.c | 21 |
1 files changed, 12 insertions, 9 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 30ccbb6d097a..ca6b3cbf44d5 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
| @@ -7860,18 +7860,21 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
| 7860 | tw32(GRC_MODE, grc_mode); | 7860 | tw32(GRC_MODE, grc_mode); |
| 7861 | } | 7861 | } |
| 7862 | 7862 | ||
| 7863 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { | 7863 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) { |
| 7864 | u32 grc_mode = tr32(GRC_MODE); | 7864 | if (tp->pci_chip_rev_id == CHIPREV_ID_57765_A0) { |
| 7865 | u32 grc_mode = tr32(GRC_MODE); | ||
| 7865 | 7866 | ||
| 7866 | /* Access the lower 1K of PL PCIE block registers. */ | 7867 | /* Access the lower 1K of PL PCIE block registers. */ |
| 7867 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; | 7868 | val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK; |
| 7868 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); | 7869 | tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL); |
| 7869 | 7870 | ||
| 7870 | val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5); | 7871 | val = tr32(TG3_PCIE_TLDLPL_PORT + |
| 7871 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, | 7872 | TG3_PCIE_PL_LO_PHYCTL5); |
| 7872 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | 7873 | tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL5, |
| 7874 | val | TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ); | ||
| 7873 | 7875 | ||
| 7874 | tw32(GRC_MODE, grc_mode); | 7876 | tw32(GRC_MODE, grc_mode); |
| 7877 | } | ||
| 7875 | 7878 | ||
| 7876 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); | 7879 | val = tr32(TG3_CPMU_LSPD_10MB_CLK); |
| 7877 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; | 7880 | val &= ~CPMU_LSPD_10MB_MACCLK_MASK; |