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authorJohn W. Linville <linville@tuxdriver.com>2005-04-21 20:01:29 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2005-04-21 20:01:29 -0400
commitcbf46853c8db75f98bd005dc545aca0703063d4b (patch)
treec9bc918aeecc55b6de0ee93a9daab25ab09a3b4e /drivers/net/tg3.c
parent6708e5cc103ba045fca035b4d8df236ca31fb8bc (diff)
[TG3]: use new TG3_FLG2_5750_PLUS flag
Replace a number of two-way if statements checking for 5750, and/or 5752 to reference the newly-defined TG3_FLG2_5750_PLUS flag instead. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c38
1 files changed, 13 insertions, 25 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 7b21b074ced9..e75e000df315 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1067,8 +1067,7 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1067 mac_mode = MAC_MODE_PORT_MODE_TBI; 1067 mac_mode = MAC_MODE_PORT_MODE_TBI;
1068 } 1068 }
1069 1069
1070 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && 1070 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1071 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
1072 tw32(MAC_LED_CTRL, tp->led_ctrl); 1071 tw32(MAC_LED_CTRL, tp->led_ctrl);
1073 1072
1074 if (((power_caps & PCI_PM_CAP_PME_D3cold) && 1073 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
@@ -3967,8 +3966,7 @@ static int tg3_chip_reset(struct tg3 *tp)
3967 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); 3966 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
3968 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 3967 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
3969 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 3968 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
3970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 3969 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
3971 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
3972 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 3970 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
3973 } 3971 }
3974 } 3972 }
@@ -5042,8 +5040,7 @@ static int tg3_reset_hw(struct tg3 *tp)
5042 tw32(GRC_MISC_CFG, val); 5040 tw32(GRC_MISC_CFG, val);
5043 5041
5044 /* Initialize MBUF/DESC pool. */ 5042 /* Initialize MBUF/DESC pool. */
5045 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 5043 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
5046 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
5047 /* Do nothing. */ 5044 /* Do nothing. */
5048 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { 5045 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5049 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); 5046 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -7032,8 +7029,7 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7032 tw32(NVRAM_CFG1, nvcfg1); 7029 tw32(NVRAM_CFG1, nvcfg1);
7033 } 7030 }
7034 7031
7035 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7032 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7037 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { 7033 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7038 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: 7034 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7039 tp->nvram_jedecnum = JEDEC_ATMEL; 7035 tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -7098,8 +7094,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
7098 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { 7094 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7099 tp->tg3_flags |= TG3_FLAG_NVRAM; 7095 tp->tg3_flags |= TG3_FLAG_NVRAM;
7100 7096
7101 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7097 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7102 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7103 u32 nvaccess = tr32(NVRAM_ACCESS); 7098 u32 nvaccess = tr32(NVRAM_ACCESS);
7104 7099
7105 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); 7100 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7108,8 +7103,7 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
7108 tg3_get_nvram_info(tp); 7103 tg3_get_nvram_info(tp);
7109 tg3_get_nvram_size(tp); 7104 tg3_get_nvram_size(tp);
7110 7105
7111 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7106 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7112 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7113 u32 nvaccess = tr32(NVRAM_ACCESS); 7107 u32 nvaccess = tr32(NVRAM_ACCESS);
7114 7108
7115 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); 7109 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7202,8 +7196,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7202 7196
7203 tg3_nvram_lock(tp); 7197 tg3_nvram_lock(tp);
7204 7198
7205 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7199 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7206 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7207 u32 nvaccess = tr32(NVRAM_ACCESS); 7200 u32 nvaccess = tr32(NVRAM_ACCESS);
7208 7201
7209 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); 7202 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7218,8 +7211,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7218 7211
7219 tg3_nvram_unlock(tp); 7212 tg3_nvram_unlock(tp);
7220 7213
7221 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7214 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7222 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7223 u32 nvaccess = tr32(NVRAM_ACCESS); 7215 u32 nvaccess = tr32(NVRAM_ACCESS);
7224 7216
7225 tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); 7217 tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7447,8 +7439,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7447 7439
7448 tg3_nvram_lock(tp); 7440 tg3_nvram_lock(tp);
7449 7441
7450 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7442 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7451 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7452 u32 nvaccess = tr32(NVRAM_ACCESS); 7443 u32 nvaccess = tr32(NVRAM_ACCESS);
7453 7444
7454 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); 7445 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7473,8 +7464,7 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7473 grc_mode = tr32(GRC_MODE); 7464 grc_mode = tr32(GRC_MODE);
7474 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); 7465 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
7475 7466
7476 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7467 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7477 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7478 u32 nvaccess = tr32(NVRAM_ACCESS); 7468 u32 nvaccess = tr32(NVRAM_ACCESS);
7479 7469
7480 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); 7470 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7592,11 +7582,10 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
7592 } else 7582 } else
7593 eeprom_phy_id = 0; 7583 eeprom_phy_id = 0;
7594 7584
7595 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7585 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7596 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7597 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | 7586 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
7598 SHASTA_EXT_LED_MODE_MASK); 7587 SHASTA_EXT_LED_MODE_MASK);
7599 } else 7588 else
7600 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK; 7589 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
7601 7590
7602 switch (led_cfg) { 7591 switch (led_cfg) {
@@ -7646,8 +7635,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
7646 7635
7647 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 7636 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7648 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 7637 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7649 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 || 7638 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
7650 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7651 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 7639 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7652 } 7640 }
7653 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL) 7641 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)