diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2008-05-26 02:45:08 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2008-05-29 04:36:14 -0400 |
commit | f51f3562d1c7df6c5a4ffee2185d713e98e76aa0 (patch) | |
tree | 3b50309595f33cfefafbf50b90d2d1ef6226c097 /drivers/net/tg3.c | |
parent | 95e2869adc13041baf3beecb97ab8e38c01525ae (diff) |
tg3: Code cleanup.
This patch applies cleanups that would otherwise clutter later
patches.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 42 |
1 files changed, 15 insertions, 27 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 7928acc1ec7a..e402f162eb81 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -1002,43 +1002,38 @@ static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv) | |||
1002 | return cap; | 1002 | return cap; |
1003 | } | 1003 | } |
1004 | 1004 | ||
1005 | static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv) | 1005 | static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv) |
1006 | { | 1006 | { |
1007 | u8 new_tg3_flags = 0; | 1007 | u8 flowctrl = 0; |
1008 | u32 old_rx_mode = tp->rx_mode; | 1008 | u32 old_rx_mode = tp->rx_mode; |
1009 | u32 old_tx_mode = tp->tx_mode; | 1009 | u32 old_tx_mode = tp->tx_mode; |
1010 | 1010 | ||
1011 | if (tp->link_config.autoneg == AUTONEG_ENABLE && | 1011 | if (tp->link_config.autoneg == AUTONEG_ENABLE && |
1012 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { | 1012 | (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) { |
1013 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) | 1013 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) |
1014 | new_tg3_flags = tg3_resolve_flowctrl_1000X(local_adv, | 1014 | flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv); |
1015 | remote_adv); | ||
1016 | else | 1015 | else |
1017 | new_tg3_flags = tg3_resolve_flowctrl_1000T(local_adv, | 1016 | flowctrl = tg3_resolve_flowctrl_1000T(lcladv, rmtadv); |
1018 | remote_adv); | 1017 | } else |
1019 | } else { | 1018 | flowctrl = tp->link_config.flowctrl; |
1020 | new_tg3_flags = tp->link_config.flowctrl; | ||
1021 | } | ||
1022 | 1019 | ||
1023 | tp->link_config.active_flowctrl = new_tg3_flags; | 1020 | tp->link_config.active_flowctrl = flowctrl; |
1024 | 1021 | ||
1025 | if (new_tg3_flags & TG3_FLOW_CTRL_RX) | 1022 | if (flowctrl & TG3_FLOW_CTRL_RX) |
1026 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; | 1023 | tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE; |
1027 | else | 1024 | else |
1028 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; | 1025 | tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE; |
1029 | 1026 | ||
1030 | if (old_rx_mode != tp->rx_mode) { | 1027 | if (old_rx_mode != tp->rx_mode) |
1031 | tw32_f(MAC_RX_MODE, tp->rx_mode); | 1028 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
1032 | } | ||
1033 | 1029 | ||
1034 | if (new_tg3_flags & TG3_FLOW_CTRL_TX) | 1030 | if (flowctrl & TG3_FLOW_CTRL_TX) |
1035 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; | 1031 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1036 | else | 1032 | else |
1037 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; | 1033 | tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE; |
1038 | 1034 | ||
1039 | if (old_tx_mode != tp->tx_mode) { | 1035 | if (old_tx_mode != tp->tx_mode) |
1040 | tw32_f(MAC_TX_MODE, tp->tx_mode); | 1036 | tw32_f(MAC_TX_MODE, tp->tx_mode); |
1041 | } | ||
1042 | } | 1037 | } |
1043 | 1038 | ||
1044 | static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) | 1039 | static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val) |
@@ -7091,7 +7086,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
7091 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) || | 7086 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) || |
7092 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) || | 7087 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784) || |
7093 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)) | 7088 | (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)) |
7094 | val |= (1 << 29); | 7089 | val |= WDMAC_MODE_STATUS_TAG_FIX; |
7095 | 7090 | ||
7096 | tw32_f(WDMAC_MODE, val); | 7091 | tw32_f(WDMAC_MODE, val); |
7097 | udelay(40); | 7092 | udelay(40); |
@@ -11542,14 +11537,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
11542 | } | 11537 | } |
11543 | } | 11538 | } |
11544 | 11539 | ||
11545 | if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && | 11540 | if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) || |
11546 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && | 11541 | (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) |
11547 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 && | ||
11548 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 && | ||
11549 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 && | ||
11550 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 && | ||
11551 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 && | ||
11552 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) | ||
11553 | tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; | 11542 | tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE; |
11554 | 11543 | ||
11555 | pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); | 11544 | pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP); |
@@ -11833,8 +11822,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
11833 | tp->phy_otp = TG3_OTP_DEFAULT; | 11822 | tp->phy_otp = TG3_OTP_DEFAULT; |
11834 | } | 11823 | } |
11835 | 11824 | ||
11836 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || | 11825 | if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) |
11837 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) | ||
11838 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; | 11826 | tp->mi_mode = MAC_MI_MODE_500KHZ_CONST; |
11839 | else | 11827 | else |
11840 | tp->mi_mode = MAC_MI_MODE_BASE; | 11828 | tp->mi_mode = MAC_MI_MODE_BASE; |