diff options
author | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
commit | 6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch) | |
tree | df0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/tg3.c | |
parent | 7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff) |
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 124 |
1 files changed, 62 insertions, 62 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index d6e2a6869f28..4d66d86e41ea 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -363,7 +363,7 @@ static void tg3_write32(struct tg3 *tp, u32 off, u32 val) | |||
363 | 363 | ||
364 | static u32 tg3_read32(struct tg3 *tp, u32 off) | 364 | static u32 tg3_read32(struct tg3 *tp, u32 off) |
365 | { | 365 | { |
366 | return (readl(tp->regs + off)); | 366 | return (readl(tp->regs + off)); |
367 | } | 367 | } |
368 | 368 | ||
369 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) | 369 | static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val) |
@@ -584,7 +584,7 @@ static inline unsigned int tg3_has_work(struct tg3 *tp) | |||
584 | /* tg3_restart_ints | 584 | /* tg3_restart_ints |
585 | * similar to tg3_enable_ints, but it accurately determines whether there | 585 | * similar to tg3_enable_ints, but it accurately determines whether there |
586 | * is new work pending and can return without flushing the PIO write | 586 | * is new work pending and can return without flushing the PIO write |
587 | * which reenables interrupts | 587 | * which reenables interrupts |
588 | */ | 588 | */ |
589 | static void tg3_restart_ints(struct tg3 *tp) | 589 | static void tg3_restart_ints(struct tg3 *tp) |
590 | { | 590 | { |
@@ -673,7 +673,7 @@ static int tg3_readphy(struct tg3 *tp, int reg, u32 *val) | |||
673 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & | 673 | frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) & |
674 | MI_COM_REG_ADDR_MASK); | 674 | MI_COM_REG_ADDR_MASK); |
675 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); | 675 | frame_val |= (MI_COM_CMD_READ | MI_COM_START); |
676 | 676 | ||
677 | tw32_f(MAC_MI_COM, frame_val); | 677 | tw32_f(MAC_MI_COM, frame_val); |
678 | 678 | ||
679 | loops = PHY_BUSY_LOOPS; | 679 | loops = PHY_BUSY_LOOPS; |
@@ -721,7 +721,7 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val) | |||
721 | MI_COM_REG_ADDR_MASK); | 721 | MI_COM_REG_ADDR_MASK); |
722 | frame_val |= (val & MI_COM_DATA_MASK); | 722 | frame_val |= (val & MI_COM_DATA_MASK); |
723 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); | 723 | frame_val |= (MI_COM_CMD_WRITE | MI_COM_START); |
724 | 724 | ||
725 | tw32_f(MAC_MI_COM, frame_val); | 725 | tw32_f(MAC_MI_COM, frame_val); |
726 | 726 | ||
727 | loops = PHY_BUSY_LOOPS; | 727 | loops = PHY_BUSY_LOOPS; |
@@ -1477,7 +1477,7 @@ static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv | |||
1477 | if (old_rx_mode != tp->rx_mode) { | 1477 | if (old_rx_mode != tp->rx_mode) { |
1478 | tw32_f(MAC_RX_MODE, tp->rx_mode); | 1478 | tw32_f(MAC_RX_MODE, tp->rx_mode); |
1479 | } | 1479 | } |
1480 | 1480 | ||
1481 | if (new_tg3_flags & TG3_FLAG_TX_PAUSE) | 1481 | if (new_tg3_flags & TG3_FLAG_TX_PAUSE) |
1482 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; | 1482 | tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE; |
1483 | else | 1483 | else |
@@ -2542,7 +2542,7 @@ static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status) | |||
2542 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { | 2542 | if (tp->link_config.autoneg == AUTONEG_ENABLE) { |
2543 | u32 flags; | 2543 | u32 flags; |
2544 | int i; | 2544 | int i; |
2545 | 2545 | ||
2546 | if (fiber_autoneg(tp, &flags)) { | 2546 | if (fiber_autoneg(tp, &flags)) { |
2547 | u32 local_adv, remote_adv; | 2547 | u32 local_adv, remote_adv; |
2548 | 2548 | ||
@@ -3258,7 +3258,7 @@ static int tg3_rx(struct tg3 *tp, int budget) | |||
3258 | 3258 | ||
3259 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */ | 3259 | len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */ |
3260 | 3260 | ||
3261 | if (len > RX_COPY_THRESHOLD | 3261 | if (len > RX_COPY_THRESHOLD |
3262 | && tp->rx_offset == 2 | 3262 | && tp->rx_offset == 2 |
3263 | /* rx_offset != 2 iff this is a 5701 card running | 3263 | /* rx_offset != 2 iff this is a 5701 card running |
3264 | * in PCI-X mode [see tg3_get_invariants()] */ | 3264 | * in PCI-X mode [see tg3_get_invariants()] */ |
@@ -6808,7 +6808,7 @@ static int tg3_test_interrupt(struct tg3 *tp) | |||
6808 | tg3_disable_ints(tp); | 6808 | tg3_disable_ints(tp); |
6809 | 6809 | ||
6810 | free_irq(tp->pdev->irq, dev); | 6810 | free_irq(tp->pdev->irq, dev); |
6811 | 6811 | ||
6812 | err = tg3_request_irq(tp); | 6812 | err = tg3_request_irq(tp); |
6813 | 6813 | ||
6814 | if (err) | 6814 | if (err) |
@@ -7435,7 +7435,7 @@ static struct net_device_stats *tg3_get_stats(struct net_device *dev) | |||
7435 | get_stat64(&hw_stats->rx_ucast_packets) + | 7435 | get_stat64(&hw_stats->rx_ucast_packets) + |
7436 | get_stat64(&hw_stats->rx_mcast_packets) + | 7436 | get_stat64(&hw_stats->rx_mcast_packets) + |
7437 | get_stat64(&hw_stats->rx_bcast_packets); | 7437 | get_stat64(&hw_stats->rx_bcast_packets); |
7438 | 7438 | ||
7439 | stats->tx_packets = old_stats->tx_packets + | 7439 | stats->tx_packets = old_stats->tx_packets + |
7440 | get_stat64(&hw_stats->tx_ucast_packets) + | 7440 | get_stat64(&hw_stats->tx_ucast_packets) + |
7441 | get_stat64(&hw_stats->tx_mcast_packets) + | 7441 | get_stat64(&hw_stats->tx_mcast_packets) + |
@@ -7743,7 +7743,7 @@ static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |||
7743 | return 0; | 7743 | return 0; |
7744 | } | 7744 | } |
7745 | 7745 | ||
7746 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); | 7746 | static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf); |
7747 | 7747 | ||
7748 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | 7748 | static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
7749 | { | 7749 | { |
@@ -7807,7 +7807,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, | |||
7807 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | 7807 | static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
7808 | { | 7808 | { |
7809 | struct tg3 *tp = netdev_priv(dev); | 7809 | struct tg3 *tp = netdev_priv(dev); |
7810 | 7810 | ||
7811 | cmd->supported = (SUPPORTED_Autoneg); | 7811 | cmd->supported = (SUPPORTED_Autoneg); |
7812 | 7812 | ||
7813 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) | 7813 | if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) |
@@ -7825,7 +7825,7 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7825 | cmd->supported |= SUPPORTED_FIBRE; | 7825 | cmd->supported |= SUPPORTED_FIBRE; |
7826 | cmd->port = PORT_FIBRE; | 7826 | cmd->port = PORT_FIBRE; |
7827 | } | 7827 | } |
7828 | 7828 | ||
7829 | cmd->advertising = tp->link_config.advertising; | 7829 | cmd->advertising = tp->link_config.advertising; |
7830 | if (netif_running(dev)) { | 7830 | if (netif_running(dev)) { |
7831 | cmd->speed = tp->link_config.active_speed; | 7831 | cmd->speed = tp->link_config.active_speed; |
@@ -7838,12 +7838,12 @@ static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7838 | cmd->maxrxpkt = 0; | 7838 | cmd->maxrxpkt = 0; |
7839 | return 0; | 7839 | return 0; |
7840 | } | 7840 | } |
7841 | 7841 | ||
7842 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | 7842 | static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) |
7843 | { | 7843 | { |
7844 | struct tg3 *tp = netdev_priv(dev); | 7844 | struct tg3 *tp = netdev_priv(dev); |
7845 | 7845 | ||
7846 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { | 7846 | if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) { |
7847 | /* These are the only valid advertisement bits allowed. */ | 7847 | /* These are the only valid advertisement bits allowed. */ |
7848 | if (cmd->autoneg == AUTONEG_ENABLE && | 7848 | if (cmd->autoneg == AUTONEG_ENABLE && |
7849 | (cmd->advertising & ~(ADVERTISED_1000baseT_Half | | 7849 | (cmd->advertising & ~(ADVERTISED_1000baseT_Half | |
@@ -7875,69 +7875,69 @@ static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) | |||
7875 | tp->link_config.speed = cmd->speed; | 7875 | tp->link_config.speed = cmd->speed; |
7876 | tp->link_config.duplex = cmd->duplex; | 7876 | tp->link_config.duplex = cmd->duplex; |
7877 | } | 7877 | } |
7878 | 7878 | ||
7879 | if (netif_running(dev)) | 7879 | if (netif_running(dev)) |
7880 | tg3_setup_phy(tp, 1); | 7880 | tg3_setup_phy(tp, 1); |
7881 | 7881 | ||
7882 | tg3_full_unlock(tp); | 7882 | tg3_full_unlock(tp); |
7883 | 7883 | ||
7884 | return 0; | 7884 | return 0; |
7885 | } | 7885 | } |
7886 | 7886 | ||
7887 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) | 7887 | static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) |
7888 | { | 7888 | { |
7889 | struct tg3 *tp = netdev_priv(dev); | 7889 | struct tg3 *tp = netdev_priv(dev); |
7890 | 7890 | ||
7891 | strcpy(info->driver, DRV_MODULE_NAME); | 7891 | strcpy(info->driver, DRV_MODULE_NAME); |
7892 | strcpy(info->version, DRV_MODULE_VERSION); | 7892 | strcpy(info->version, DRV_MODULE_VERSION); |
7893 | strcpy(info->fw_version, tp->fw_ver); | 7893 | strcpy(info->fw_version, tp->fw_ver); |
7894 | strcpy(info->bus_info, pci_name(tp->pdev)); | 7894 | strcpy(info->bus_info, pci_name(tp->pdev)); |
7895 | } | 7895 | } |
7896 | 7896 | ||
7897 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | 7897 | static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
7898 | { | 7898 | { |
7899 | struct tg3 *tp = netdev_priv(dev); | 7899 | struct tg3 *tp = netdev_priv(dev); |
7900 | 7900 | ||
7901 | wol->supported = WAKE_MAGIC; | 7901 | wol->supported = WAKE_MAGIC; |
7902 | wol->wolopts = 0; | 7902 | wol->wolopts = 0; |
7903 | if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) | 7903 | if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) |
7904 | wol->wolopts = WAKE_MAGIC; | 7904 | wol->wolopts = WAKE_MAGIC; |
7905 | memset(&wol->sopass, 0, sizeof(wol->sopass)); | 7905 | memset(&wol->sopass, 0, sizeof(wol->sopass)); |
7906 | } | 7906 | } |
7907 | 7907 | ||
7908 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) | 7908 | static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) |
7909 | { | 7909 | { |
7910 | struct tg3 *tp = netdev_priv(dev); | 7910 | struct tg3 *tp = netdev_priv(dev); |
7911 | 7911 | ||
7912 | if (wol->wolopts & ~WAKE_MAGIC) | 7912 | if (wol->wolopts & ~WAKE_MAGIC) |
7913 | return -EINVAL; | 7913 | return -EINVAL; |
7914 | if ((wol->wolopts & WAKE_MAGIC) && | 7914 | if ((wol->wolopts & WAKE_MAGIC) && |
7915 | tp->tg3_flags2 & TG3_FLG2_PHY_SERDES && | 7915 | tp->tg3_flags2 & TG3_FLG2_PHY_SERDES && |
7916 | !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP)) | 7916 | !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP)) |
7917 | return -EINVAL; | 7917 | return -EINVAL; |
7918 | 7918 | ||
7919 | spin_lock_bh(&tp->lock); | 7919 | spin_lock_bh(&tp->lock); |
7920 | if (wol->wolopts & WAKE_MAGIC) | 7920 | if (wol->wolopts & WAKE_MAGIC) |
7921 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; | 7921 | tp->tg3_flags |= TG3_FLAG_WOL_ENABLE; |
7922 | else | 7922 | else |
7923 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; | 7923 | tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE; |
7924 | spin_unlock_bh(&tp->lock); | 7924 | spin_unlock_bh(&tp->lock); |
7925 | 7925 | ||
7926 | return 0; | 7926 | return 0; |
7927 | } | 7927 | } |
7928 | 7928 | ||
7929 | static u32 tg3_get_msglevel(struct net_device *dev) | 7929 | static u32 tg3_get_msglevel(struct net_device *dev) |
7930 | { | 7930 | { |
7931 | struct tg3 *tp = netdev_priv(dev); | 7931 | struct tg3 *tp = netdev_priv(dev); |
7932 | return tp->msg_enable; | 7932 | return tp->msg_enable; |
7933 | } | 7933 | } |
7934 | 7934 | ||
7935 | static void tg3_set_msglevel(struct net_device *dev, u32 value) | 7935 | static void tg3_set_msglevel(struct net_device *dev, u32 value) |
7936 | { | 7936 | { |
7937 | struct tg3 *tp = netdev_priv(dev); | 7937 | struct tg3 *tp = netdev_priv(dev); |
7938 | tp->msg_enable = value; | 7938 | tp->msg_enable = value; |
7939 | } | 7939 | } |
7940 | 7940 | ||
7941 | #if TG3_TSO_SUPPORT != 0 | 7941 | #if TG3_TSO_SUPPORT != 0 |
7942 | static int tg3_set_tso(struct net_device *dev, u32 value) | 7942 | static int tg3_set_tso(struct net_device *dev, u32 value) |
7943 | { | 7943 | { |
@@ -7957,13 +7957,13 @@ static int tg3_set_tso(struct net_device *dev, u32 value) | |||
7957 | return ethtool_op_set_tso(dev, value); | 7957 | return ethtool_op_set_tso(dev, value); |
7958 | } | 7958 | } |
7959 | #endif | 7959 | #endif |
7960 | 7960 | ||
7961 | static int tg3_nway_reset(struct net_device *dev) | 7961 | static int tg3_nway_reset(struct net_device *dev) |
7962 | { | 7962 | { |
7963 | struct tg3 *tp = netdev_priv(dev); | 7963 | struct tg3 *tp = netdev_priv(dev); |
7964 | u32 bmcr; | 7964 | u32 bmcr; |
7965 | int r; | 7965 | int r; |
7966 | 7966 | ||
7967 | if (!netif_running(dev)) | 7967 | if (!netif_running(dev)) |
7968 | return -EAGAIN; | 7968 | return -EAGAIN; |
7969 | 7969 | ||
@@ -7981,14 +7981,14 @@ static int tg3_nway_reset(struct net_device *dev) | |||
7981 | r = 0; | 7981 | r = 0; |
7982 | } | 7982 | } |
7983 | spin_unlock_bh(&tp->lock); | 7983 | spin_unlock_bh(&tp->lock); |
7984 | 7984 | ||
7985 | return r; | 7985 | return r; |
7986 | } | 7986 | } |
7987 | 7987 | ||
7988 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | 7988 | static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
7989 | { | 7989 | { |
7990 | struct tg3 *tp = netdev_priv(dev); | 7990 | struct tg3 *tp = netdev_priv(dev); |
7991 | 7991 | ||
7992 | ering->rx_max_pending = TG3_RX_RING_SIZE - 1; | 7992 | ering->rx_max_pending = TG3_RX_RING_SIZE - 1; |
7993 | ering->rx_mini_max_pending = 0; | 7993 | ering->rx_mini_max_pending = 0; |
7994 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) | 7994 | if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) |
@@ -8007,24 +8007,24 @@ static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam * | |||
8007 | 8007 | ||
8008 | ering->tx_pending = tp->tx_pending; | 8008 | ering->tx_pending = tp->tx_pending; |
8009 | } | 8009 | } |
8010 | 8010 | ||
8011 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) | 8011 | static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering) |
8012 | { | 8012 | { |
8013 | struct tg3 *tp = netdev_priv(dev); | 8013 | struct tg3 *tp = netdev_priv(dev); |
8014 | int irq_sync = 0, err = 0; | 8014 | int irq_sync = 0, err = 0; |
8015 | 8015 | ||
8016 | if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || | 8016 | if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) || |
8017 | (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || | 8017 | (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || |
8018 | (ering->tx_pending > TG3_TX_RING_SIZE - 1)) | 8018 | (ering->tx_pending > TG3_TX_RING_SIZE - 1)) |
8019 | return -EINVAL; | 8019 | return -EINVAL; |
8020 | 8020 | ||
8021 | if (netif_running(dev)) { | 8021 | if (netif_running(dev)) { |
8022 | tg3_netif_stop(tp); | 8022 | tg3_netif_stop(tp); |
8023 | irq_sync = 1; | 8023 | irq_sync = 1; |
8024 | } | 8024 | } |
8025 | 8025 | ||
8026 | tg3_full_lock(tp, irq_sync); | 8026 | tg3_full_lock(tp, irq_sync); |
8027 | 8027 | ||
8028 | tp->rx_pending = ering->rx_pending; | 8028 | tp->rx_pending = ering->rx_pending; |
8029 | 8029 | ||
8030 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && | 8030 | if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) && |
@@ -8041,24 +8041,24 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e | |||
8041 | } | 8041 | } |
8042 | 8042 | ||
8043 | tg3_full_unlock(tp); | 8043 | tg3_full_unlock(tp); |
8044 | 8044 | ||
8045 | return err; | 8045 | return err; |
8046 | } | 8046 | } |
8047 | 8047 | ||
8048 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | 8048 | static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
8049 | { | 8049 | { |
8050 | struct tg3 *tp = netdev_priv(dev); | 8050 | struct tg3 *tp = netdev_priv(dev); |
8051 | 8051 | ||
8052 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; | 8052 | epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0; |
8053 | epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0; | 8053 | epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0; |
8054 | epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0; | 8054 | epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0; |
8055 | } | 8055 | } |
8056 | 8056 | ||
8057 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) | 8057 | static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause) |
8058 | { | 8058 | { |
8059 | struct tg3 *tp = netdev_priv(dev); | 8059 | struct tg3 *tp = netdev_priv(dev); |
8060 | int irq_sync = 0, err = 0; | 8060 | int irq_sync = 0, err = 0; |
8061 | 8061 | ||
8062 | if (netif_running(dev)) { | 8062 | if (netif_running(dev)) { |
8063 | tg3_netif_stop(tp); | 8063 | tg3_netif_stop(tp); |
8064 | irq_sync = 1; | 8064 | irq_sync = 1; |
@@ -8087,46 +8087,46 @@ static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam | |||
8087 | } | 8087 | } |
8088 | 8088 | ||
8089 | tg3_full_unlock(tp); | 8089 | tg3_full_unlock(tp); |
8090 | 8090 | ||
8091 | return err; | 8091 | return err; |
8092 | } | 8092 | } |
8093 | 8093 | ||
8094 | static u32 tg3_get_rx_csum(struct net_device *dev) | 8094 | static u32 tg3_get_rx_csum(struct net_device *dev) |
8095 | { | 8095 | { |
8096 | struct tg3 *tp = netdev_priv(dev); | 8096 | struct tg3 *tp = netdev_priv(dev); |
8097 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; | 8097 | return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0; |
8098 | } | 8098 | } |
8099 | 8099 | ||
8100 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) | 8100 | static int tg3_set_rx_csum(struct net_device *dev, u32 data) |
8101 | { | 8101 | { |
8102 | struct tg3 *tp = netdev_priv(dev); | 8102 | struct tg3 *tp = netdev_priv(dev); |
8103 | 8103 | ||
8104 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { | 8104 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
8105 | if (data != 0) | 8105 | if (data != 0) |
8106 | return -EINVAL; | 8106 | return -EINVAL; |
8107 | return 0; | 8107 | return 0; |
8108 | } | 8108 | } |
8109 | 8109 | ||
8110 | spin_lock_bh(&tp->lock); | 8110 | spin_lock_bh(&tp->lock); |
8111 | if (data) | 8111 | if (data) |
8112 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; | 8112 | tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS; |
8113 | else | 8113 | else |
8114 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; | 8114 | tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS; |
8115 | spin_unlock_bh(&tp->lock); | 8115 | spin_unlock_bh(&tp->lock); |
8116 | 8116 | ||
8117 | return 0; | 8117 | return 0; |
8118 | } | 8118 | } |
8119 | 8119 | ||
8120 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) | 8120 | static int tg3_set_tx_csum(struct net_device *dev, u32 data) |
8121 | { | 8121 | { |
8122 | struct tg3 *tp = netdev_priv(dev); | 8122 | struct tg3 *tp = netdev_priv(dev); |
8123 | 8123 | ||
8124 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { | 8124 | if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) { |
8125 | if (data != 0) | 8125 | if (data != 0) |
8126 | return -EINVAL; | 8126 | return -EINVAL; |
8127 | return 0; | 8127 | return 0; |
8128 | } | 8128 | } |
8129 | 8129 | ||
8130 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || | 8130 | if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 || |
8131 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) | 8131 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) |
8132 | ethtool_op_set_tx_hw_csum(dev, data); | 8132 | ethtool_op_set_tx_hw_csum(dev, data); |
@@ -8181,7 +8181,7 @@ static int tg3_phys_id(struct net_device *dev, u32 data) | |||
8181 | LED_CTRL_TRAFFIC_OVERRIDE | | 8181 | LED_CTRL_TRAFFIC_OVERRIDE | |
8182 | LED_CTRL_TRAFFIC_BLINK | | 8182 | LED_CTRL_TRAFFIC_BLINK | |
8183 | LED_CTRL_TRAFFIC_LED); | 8183 | LED_CTRL_TRAFFIC_LED); |
8184 | 8184 | ||
8185 | else | 8185 | else |
8186 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | | 8186 | tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE | |
8187 | LED_CTRL_TRAFFIC_OVERRIDE); | 8187 | LED_CTRL_TRAFFIC_OVERRIDE); |
@@ -8358,7 +8358,7 @@ static int tg3_test_registers(struct tg3 *tp) | |||
8358 | 0x00000000, 0xffff0002 }, | 8358 | 0x00000000, 0xffff0002 }, |
8359 | { RCVDBDI_STD_BD+0xc, 0x0000, | 8359 | { RCVDBDI_STD_BD+0xc, 0x0000, |
8360 | 0x00000000, 0xffffffff }, | 8360 | 0x00000000, 0xffffffff }, |
8361 | 8361 | ||
8362 | /* Receive BD Initiator Control Registers. */ | 8362 | /* Receive BD Initiator Control Registers. */ |
8363 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, | 8363 | { RCVBDI_STD_THRESH, TG3_FL_NOT_5705, |
8364 | 0x00000000, 0xffffffff }, | 8364 | 0x00000000, 0xffffffff }, |
@@ -8366,7 +8366,7 @@ static int tg3_test_registers(struct tg3 *tp) | |||
8366 | 0x00000000, 0x000003ff }, | 8366 | 0x00000000, 0x000003ff }, |
8367 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, | 8367 | { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705, |
8368 | 0x00000000, 0xffffffff }, | 8368 | 0x00000000, 0xffffffff }, |
8369 | 8369 | ||
8370 | /* Host Coalescing Control Registers. */ | 8370 | /* Host Coalescing Control Registers. */ |
8371 | { HOSTCC_MODE, TG3_FL_NOT_5705, | 8371 | { HOSTCC_MODE, TG3_FL_NOT_5705, |
8372 | 0x00000000, 0x00000004 }, | 8372 | 0x00000000, 0x00000004 }, |
@@ -8430,7 +8430,7 @@ static int tg3_test_registers(struct tg3 *tp) | |||
8430 | 0xffffffff, 0x00000000 }, | 8430 | 0xffffffff, 0x00000000 }, |
8431 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, | 8431 | { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705, |
8432 | 0xffffffff, 0x00000000 }, | 8432 | 0xffffffff, 0x00000000 }, |
8433 | 8433 | ||
8434 | /* Mailbox Registers */ | 8434 | /* Mailbox Registers */ |
8435 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, | 8435 | { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000, |
8436 | 0x00000000, 0x000001ff }, | 8436 | 0x00000000, 0x000001ff }, |
@@ -8570,7 +8570,7 @@ static int tg3_test_memory(struct tg3 *tp) | |||
8570 | mem_tbl[i].len)) != 0) | 8570 | mem_tbl[i].len)) != 0) |
8571 | break; | 8571 | break; |
8572 | } | 8572 | } |
8573 | 8573 | ||
8574 | return err; | 8574 | return err; |
8575 | } | 8575 | } |
8576 | 8576 | ||
@@ -8705,7 +8705,7 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode) | |||
8705 | goto out; | 8705 | goto out; |
8706 | } | 8706 | } |
8707 | err = 0; | 8707 | err = 0; |
8708 | 8708 | ||
8709 | /* tg3_free_rings will unmap and free the rx_skb */ | 8709 | /* tg3_free_rings will unmap and free the rx_skb */ |
8710 | out: | 8710 | out: |
8711 | return err; | 8711 | return err; |
@@ -9033,7 +9033,7 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |||
9033 | 9033 | ||
9034 | tp->nvram_size = cursize; | 9034 | tp->nvram_size = cursize; |
9035 | } | 9035 | } |
9036 | 9036 | ||
9037 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) | 9037 | static void __devinit tg3_get_nvram_size(struct tg3 *tp) |
9038 | { | 9038 | { |
9039 | u32 val; | 9039 | u32 val; |
@@ -9449,7 +9449,7 @@ static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, | |||
9449 | (addr & EEPROM_ADDR_ADDR_MASK) | | 9449 | (addr & EEPROM_ADDR_ADDR_MASK) | |
9450 | EEPROM_ADDR_START | | 9450 | EEPROM_ADDR_START | |
9451 | EEPROM_ADDR_WRITE); | 9451 | EEPROM_ADDR_WRITE); |
9452 | 9452 | ||
9453 | for (j = 0; j < 10000; j++) { | 9453 | for (j = 0; j < 10000; j++) { |
9454 | val = tr32(GRC_EEPROM_ADDR); | 9454 | val = tr32(GRC_EEPROM_ADDR); |
9455 | 9455 | ||
@@ -9485,7 +9485,7 @@ static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len, | |||
9485 | u32 phy_addr, page_off, size; | 9485 | u32 phy_addr, page_off, size; |
9486 | 9486 | ||
9487 | phy_addr = offset & ~pagemask; | 9487 | phy_addr = offset & ~pagemask; |
9488 | 9488 | ||
9489 | for (j = 0; j < pagesize; j += 4) { | 9489 | for (j = 0; j < pagesize; j += 4) { |
9490 | if ((ret = tg3_nvram_read(tp, phy_addr + j, | 9490 | if ((ret = tg3_nvram_read(tp, phy_addr + j, |
9491 | (u32 *) (tmp + j)))) | 9491 | (u32 *) (tmp + j)))) |
@@ -9941,7 +9941,7 @@ static int __devinit tg3_phy_probe(struct tg3 *tp) | |||
9941 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && | 9941 | if (!tg3_readphy(tp, MII_BMSR, &bmsr) && |
9942 | (bmsr & BMSR_LSTATUS)) | 9942 | (bmsr & BMSR_LSTATUS)) |
9943 | goto skip_phy_reset; | 9943 | goto skip_phy_reset; |
9944 | 9944 | ||
9945 | err = tg3_phy_reset(tp); | 9945 | err = tg3_phy_reset(tp); |
9946 | if (err) | 9946 | if (err) |
9947 | return err; | 9947 | return err; |
@@ -10461,7 +10461,7 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) | |||
10461 | * When the flag is set, it means that GPIO1 is used for eeprom | 10461 | * When the flag is set, it means that GPIO1 is used for eeprom |
10462 | * write protect and also implies that it is a LOM where GPIOs | 10462 | * write protect and also implies that it is a LOM where GPIOs |
10463 | * are not used to switch power. | 10463 | * are not used to switch power. |
10464 | */ | 10464 | */ |
10465 | tg3_get_eeprom_hw_cfg(tp); | 10465 | tg3_get_eeprom_hw_cfg(tp); |
10466 | 10466 | ||
10467 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). | 10467 | /* Set up tp->grc_local_ctrl before calling tg3_set_power_state(). |