diff options
author | Michael Chan <mchan@broadcom.com> | 2006-03-21 01:29:15 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2006-03-21 01:29:15 -0500 |
commit | 1820180b0e59cc48019414018b180518059f50d3 (patch) | |
tree | 6f79d249a19a5094e6da5e7cc8fc7afd27e4e961 /drivers/net/tg3.c | |
parent | 79f4d13a15774c2d442b619bad95a4c612eed4f3 (diff) |
[TG3]: nvram cleanup
Some nvram related cleanup:
1. Add a tg3_nvram_read_swab() since swabing the data is frequently
done.
2. Add a function to convert nvram address to physical address
instead of doing it in 2 separate places.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 62 |
1 files changed, 35 insertions, 27 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index fe5c565a5284..602326b78ef9 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -7457,6 +7457,7 @@ static int tg3_get_eeprom_len(struct net_device *dev) | |||
7457 | } | 7457 | } |
7458 | 7458 | ||
7459 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val); | 7459 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val); |
7460 | static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val); | ||
7460 | 7461 | ||
7461 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) | 7462 | static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data) |
7462 | { | 7463 | { |
@@ -7973,10 +7974,9 @@ static int tg3_test_nvram(struct tg3 *tp) | |||
7973 | u32 *buf, csum, magic; | 7974 | u32 *buf, csum, magic; |
7974 | int i, j, err = 0, size; | 7975 | int i, j, err = 0, size; |
7975 | 7976 | ||
7976 | if (tg3_nvram_read(tp, 0, &magic) != 0) | 7977 | if (tg3_nvram_read_swab(tp, 0, &magic) != 0) |
7977 | return -EIO; | 7978 | return -EIO; |
7978 | 7979 | ||
7979 | magic = swab32(magic); | ||
7980 | if (magic == TG3_EEPROM_MAGIC) | 7980 | if (magic == TG3_EEPROM_MAGIC) |
7981 | size = NVRAM_TEST_SIZE; | 7981 | size = NVRAM_TEST_SIZE; |
7982 | else if ((magic & 0xff000000) == 0xa5000000) { | 7982 | else if ((magic & 0xff000000) == 0xa5000000) { |
@@ -8749,10 +8749,9 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |||
8749 | 8749 | ||
8750 | tp->nvram_size = EEPROM_CHIP_SIZE; | 8750 | tp->nvram_size = EEPROM_CHIP_SIZE; |
8751 | 8751 | ||
8752 | if (tg3_nvram_read(tp, 0, &val) != 0) | 8752 | if (tg3_nvram_read_swab(tp, 0, &magic) != 0) |
8753 | return; | 8753 | return; |
8754 | 8754 | ||
8755 | magic = swab32(val); | ||
8756 | if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000)) | 8755 | if ((magic != TG3_EEPROM_MAGIC) && ((magic & 0xff000000) != 0xa5000000)) |
8757 | return; | 8756 | return; |
8758 | 8757 | ||
@@ -8764,10 +8763,10 @@ static void __devinit tg3_get_eeprom_size(struct tg3 *tp) | |||
8764 | cursize = 0x10; | 8763 | cursize = 0x10; |
8765 | 8764 | ||
8766 | while (cursize < tp->nvram_size) { | 8765 | while (cursize < tp->nvram_size) { |
8767 | if (tg3_nvram_read(tp, cursize, &val) != 0) | 8766 | if (tg3_nvram_read_swab(tp, cursize, &val) != 0) |
8768 | return; | 8767 | return; |
8769 | 8768 | ||
8770 | if (swab32(val) == magic) | 8769 | if (val == magic) |
8771 | break; | 8770 | break; |
8772 | 8771 | ||
8773 | cursize <<= 1; | 8772 | cursize <<= 1; |
@@ -8780,11 +8779,11 @@ static void __devinit tg3_get_nvram_size(struct tg3 *tp) | |||
8780 | { | 8779 | { |
8781 | u32 val; | 8780 | u32 val; |
8782 | 8781 | ||
8783 | if (tg3_nvram_read(tp, 0, &val) != 0) | 8782 | if (tg3_nvram_read_swab(tp, 0, &val) != 0) |
8784 | return; | 8783 | return; |
8785 | 8784 | ||
8786 | /* Selfboot format */ | 8785 | /* Selfboot format */ |
8787 | if (swab32(val) != TG3_EEPROM_MAGIC) { | 8786 | if (val != TG3_EEPROM_MAGIC) { |
8788 | tg3_get_eeprom_size(tp); | 8787 | tg3_get_eeprom_size(tp); |
8789 | return; | 8788 | return; |
8790 | } | 8789 | } |
@@ -9056,6 +9055,20 @@ static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd) | |||
9056 | return 0; | 9055 | return 0; |
9057 | } | 9056 | } |
9058 | 9057 | ||
9058 | static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr) | ||
9059 | { | ||
9060 | if ((tp->tg3_flags & TG3_FLAG_NVRAM) && | ||
9061 | (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | ||
9062 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | ||
9063 | (tp->nvram_jedecnum == JEDEC_ATMEL)) | ||
9064 | |||
9065 | addr = ((addr / tp->nvram_pagesize) << | ||
9066 | ATMEL_AT45DB0X1B_PAGE_POS) + | ||
9067 | (addr % tp->nvram_pagesize); | ||
9068 | |||
9069 | return addr; | ||
9070 | } | ||
9071 | |||
9059 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | 9072 | static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) |
9060 | { | 9073 | { |
9061 | int ret; | 9074 | int ret; |
@@ -9068,14 +9081,7 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | |||
9068 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) | 9081 | if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) |
9069 | return tg3_nvram_read_using_eeprom(tp, offset, val); | 9082 | return tg3_nvram_read_using_eeprom(tp, offset, val); |
9070 | 9083 | ||
9071 | if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) && | 9084 | offset = tg3_nvram_phys_addr(tp, offset); |
9072 | (tp->tg3_flags2 & TG3_FLG2_FLASH) && | ||
9073 | (tp->nvram_jedecnum == JEDEC_ATMEL)) { | ||
9074 | |||
9075 | offset = ((offset / tp->nvram_pagesize) << | ||
9076 | ATMEL_AT45DB0X1B_PAGE_POS) + | ||
9077 | (offset % tp->nvram_pagesize); | ||
9078 | } | ||
9079 | 9085 | ||
9080 | if (offset > NVRAM_ADDR_MSK) | 9086 | if (offset > NVRAM_ADDR_MSK) |
9081 | return -EINVAL; | 9087 | return -EINVAL; |
@@ -9100,6 +9106,16 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val) | |||
9100 | return ret; | 9106 | return ret; |
9101 | } | 9107 | } |
9102 | 9108 | ||
9109 | static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val) | ||
9110 | { | ||
9111 | int err; | ||
9112 | u32 tmp; | ||
9113 | |||
9114 | err = tg3_nvram_read(tp, offset, &tmp); | ||
9115 | *val = swab32(tmp); | ||
9116 | return err; | ||
9117 | } | ||
9118 | |||
9103 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, | 9119 | static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp, |
9104 | u32 offset, u32 len, u8 *buf) | 9120 | u32 offset, u32 len, u8 *buf) |
9105 | { | 9121 | { |
@@ -9252,15 +9268,7 @@ static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len, | |||
9252 | 9268 | ||
9253 | page_off = offset % tp->nvram_pagesize; | 9269 | page_off = offset % tp->nvram_pagesize; |
9254 | 9270 | ||
9255 | if ((tp->tg3_flags2 & TG3_FLG2_FLASH) && | 9271 | phy_addr = tg3_nvram_phys_addr(tp, offset); |
9256 | (tp->nvram_jedecnum == JEDEC_ATMEL)) { | ||
9257 | |||
9258 | phy_addr = ((offset / tp->nvram_pagesize) << | ||
9259 | ATMEL_AT45DB0X1B_PAGE_POS) + page_off; | ||
9260 | } | ||
9261 | else { | ||
9262 | phy_addr = offset; | ||
9263 | } | ||
9264 | 9272 | ||
9265 | tw32(NVRAM_ADDR, phy_addr); | 9273 | tw32(NVRAM_ADDR, phy_addr); |
9266 | 9274 | ||
@@ -9689,10 +9697,10 @@ static void __devinit tg3_read_partno(struct tg3 *tp) | |||
9689 | return; | 9697 | return; |
9690 | } | 9698 | } |
9691 | 9699 | ||
9692 | if (tg3_nvram_read(tp, 0x0, &magic)) | 9700 | if (tg3_nvram_read_swab(tp, 0x0, &magic)) |
9693 | return; | 9701 | return; |
9694 | 9702 | ||
9695 | if (swab32(magic) == TG3_EEPROM_MAGIC) { | 9703 | if (magic == TG3_EEPROM_MAGIC) { |
9696 | for (i = 0; i < 256; i += 4) { | 9704 | for (i = 0; i < 256; i += 4) { |
9697 | u32 tmp; | 9705 | u32 tmp; |
9698 | 9706 | ||