diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2009-02-25 09:26:33 -0500 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2009-02-27 02:16:38 -0500 |
commit | acd9c119cc663860fff4f1445ed0f87d82378d99 (patch) | |
tree | 32bd7f0a7ee79bd832ba3f2ebbe394cc65f80b03 /drivers/net/tg3.c | |
parent | 6d348f2c1e0bb1cf7a494b51fc921095ead3f6ae (diff) |
tg3: Refactor firmware version routines
This patch reorganizes the firmware version routines in preparation for
the following patches.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Signed-off-by: Benjamin Li <benli@broadcom.com>
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 98 |
1 files changed, 55 insertions, 43 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 945391862ab1..2e8375587ee8 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -11461,6 +11461,31 @@ static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset) | |||
11461 | return 1; | 11461 | return 1; |
11462 | } | 11462 | } |
11463 | 11463 | ||
11464 | static void __devinit tg3_read_bc_ver(struct tg3 *tp) | ||
11465 | { | ||
11466 | u32 offset, start, ver_offset; | ||
11467 | int i; | ||
11468 | |||
11469 | if (tg3_nvram_read(tp, 0xc, &offset) || | ||
11470 | tg3_nvram_read(tp, 0x4, &start)) | ||
11471 | return; | ||
11472 | |||
11473 | offset = tg3_nvram_logical_addr(tp, offset); | ||
11474 | |||
11475 | if (!tg3_fw_img_is_valid(tp, offset) || | ||
11476 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | ||
11477 | return; | ||
11478 | |||
11479 | offset = offset + ver_offset - start; | ||
11480 | for (i = 0; i < 16; i += 4) { | ||
11481 | __be32 v; | ||
11482 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | ||
11483 | return; | ||
11484 | |||
11485 | memcpy(tp->fw_ver + i, &v, sizeof(v)); | ||
11486 | } | ||
11487 | } | ||
11488 | |||
11464 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) | 11489 | static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) |
11465 | { | 11490 | { |
11466 | u32 offset, major, minor, build; | 11491 | u32 offset, major, minor, build; |
@@ -11506,44 +11531,10 @@ static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val) | |||
11506 | } | 11531 | } |
11507 | } | 11532 | } |
11508 | 11533 | ||
11509 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) | 11534 | static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp) |
11510 | { | 11535 | { |
11511 | u32 val, offset, start; | 11536 | u32 val, offset, start; |
11512 | u32 ver_offset; | 11537 | int i, vlen; |
11513 | int i, bcnt; | ||
11514 | |||
11515 | if (tg3_nvram_read(tp, 0, &val)) | ||
11516 | return; | ||
11517 | |||
11518 | if (val != TG3_EEPROM_MAGIC) { | ||
11519 | if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | ||
11520 | tg3_read_sb_ver(tp, val); | ||
11521 | |||
11522 | return; | ||
11523 | } | ||
11524 | |||
11525 | if (tg3_nvram_read(tp, 0xc, &offset) || | ||
11526 | tg3_nvram_read(tp, 0x4, &start)) | ||
11527 | return; | ||
11528 | |||
11529 | offset = tg3_nvram_logical_addr(tp, offset); | ||
11530 | |||
11531 | if (!tg3_fw_img_is_valid(tp, offset) || | ||
11532 | tg3_nvram_read(tp, offset + 8, &ver_offset)) | ||
11533 | return; | ||
11534 | |||
11535 | offset = offset + ver_offset - start; | ||
11536 | for (i = 0; i < 16; i += 4) { | ||
11537 | __be32 v; | ||
11538 | if (tg3_nvram_read_be32(tp, offset + i, &v)) | ||
11539 | return; | ||
11540 | |||
11541 | memcpy(tp->fw_ver + i, &v, 4); | ||
11542 | } | ||
11543 | |||
11544 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | ||
11545 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | ||
11546 | return; | ||
11547 | 11538 | ||
11548 | for (offset = TG3_NVM_DIR_START; | 11539 | for (offset = TG3_NVM_DIR_START; |
11549 | offset < TG3_NVM_DIR_END; | 11540 | offset < TG3_NVM_DIR_END; |
@@ -11570,10 +11561,10 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |||
11570 | 11561 | ||
11571 | offset += val - start; | 11562 | offset += val - start; |
11572 | 11563 | ||
11573 | bcnt = strlen(tp->fw_ver); | 11564 | vlen = strlen(tp->fw_ver); |
11574 | 11565 | ||
11575 | tp->fw_ver[bcnt++] = ','; | 11566 | tp->fw_ver[vlen++] = ','; |
11576 | tp->fw_ver[bcnt++] = ' '; | 11567 | tp->fw_ver[vlen++] = ' '; |
11577 | 11568 | ||
11578 | for (i = 0; i < 4; i++) { | 11569 | for (i = 0; i < 4; i++) { |
11579 | __be32 v; | 11570 | __be32 v; |
@@ -11582,14 +11573,35 @@ static void __devinit tg3_read_fw_ver(struct tg3 *tp) | |||
11582 | 11573 | ||
11583 | offset += sizeof(v); | 11574 | offset += sizeof(v); |
11584 | 11575 | ||
11585 | if (bcnt > TG3_VER_SIZE - sizeof(v)) { | 11576 | if (vlen > TG3_VER_SIZE - sizeof(v)) { |
11586 | memcpy(&tp->fw_ver[bcnt], &v, TG3_VER_SIZE - bcnt); | 11577 | memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen); |
11587 | break; | 11578 | break; |
11588 | } | 11579 | } |
11589 | 11580 | ||
11590 | memcpy(&tp->fw_ver[bcnt], &v, sizeof(v)); | 11581 | memcpy(&tp->fw_ver[vlen], &v, sizeof(v)); |
11591 | bcnt += sizeof(v); | 11582 | vlen += sizeof(v); |
11592 | } | 11583 | } |
11584 | } | ||
11585 | |||
11586 | static void __devinit tg3_read_fw_ver(struct tg3 *tp) | ||
11587 | { | ||
11588 | u32 val; | ||
11589 | |||
11590 | if (tg3_nvram_read(tp, 0, &val)) | ||
11591 | return; | ||
11592 | |||
11593 | if (val == TG3_EEPROM_MAGIC) | ||
11594 | tg3_read_bc_ver(tp); | ||
11595 | else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) | ||
11596 | tg3_read_sb_ver(tp, val); | ||
11597 | else | ||
11598 | return; | ||
11599 | |||
11600 | if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) || | ||
11601 | (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) | ||
11602 | return; | ||
11603 | |||
11604 | tg3_read_mgmtfw_ver(tp); | ||
11593 | 11605 | ||
11594 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; | 11606 | tp->fw_ver[TG3_VER_SIZE - 1] = 0; |
11595 | } | 11607 | } |