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authorAndy Gospodarek <andy@greyhouse.net>2007-09-06 15:42:14 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:49:00 -0400
commitab0049b4a2f66074dff6af851b35bba888f53972 (patch)
tree1a52559d41e77ec216f53d5bc3f6e42e335f0eca /drivers/net/tg3.c
parent50f17787e9b0222ce65cc831407c3ba4790db3ff (diff)
[TG3]: remove sparse warnings
Removed sparse warnings from tg3 driver. The new logic seems fine (I don't immediately see where we are running over values for any of the variables that need to be saved). This patch compiles fine and I'm currently using a tg3 with the patched driver to post this patch as a basic proof of concept. Signed-off-by: Andy Gospodarek <andy@greyhouse.net> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index ef1e3d1173c4..cbfa4df09592 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4870,7 +4870,6 @@ static void tg3_restore_pci_state(struct tg3 *tp)
4870 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val); 4870 pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4871 4871
4872 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) { 4872 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4873 u32 val;
4874 4873
4875 /* Chip reset on 5780 will reset MSI enable bit, 4874 /* Chip reset on 5780 will reset MSI enable bit,
4876 * so need to restore it. 4875 * so need to restore it.
@@ -5027,7 +5026,7 @@ static int tg3_chip_reset(struct tg3 *tp)
5027 tw32(GRC_MODE, tp->grc_mode); 5026 tw32(GRC_MODE, tp->grc_mode);
5028 5027
5029 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) { 5028 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
5030 u32 val = tr32(0xc4); 5029 val = tr32(0xc4);
5031 5030
5032 tw32(0xc4, val | (1 << 15)); 5031 tw32(0xc4, val | (1 << 15));
5033 } 5032 }
@@ -5056,7 +5055,7 @@ static int tg3_chip_reset(struct tg3 *tp)
5056 5055
5057 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && 5056 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
5058 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) { 5057 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
5059 u32 val = tr32(0x7c00); 5058 val = tr32(0x7c00);
5060 5059
5061 tw32(0x7c00, val | (1 << 25)); 5060 tw32(0x7c00, val | (1 << 25));
5062 } 5061 }
@@ -7991,7 +7990,7 @@ static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
7991 buf = data; 7990 buf = data;
7992 if (b_offset || odd_len) { 7991 if (b_offset || odd_len) {
7993 buf = kmalloc(len, GFP_KERNEL); 7992 buf = kmalloc(len, GFP_KERNEL);
7994 if (buf == 0) 7993 if (!buf)
7995 return -ENOMEM; 7994 return -ENOMEM;
7996 if (b_offset) 7995 if (b_offset)
7997 memcpy(buf, &start, 4); 7996 memcpy(buf, &start, 4);
@@ -8420,7 +8419,7 @@ static void tg3_get_ethtool_stats (struct net_device *dev,
8420static int tg3_test_nvram(struct tg3 *tp) 8419static int tg3_test_nvram(struct tg3 *tp)
8421{ 8420{
8422 u32 *buf, csum, magic; 8421 u32 *buf, csum, magic;
8423 int i, j, err = 0, size; 8422 int i, j, k, err = 0, size;
8424 8423
8425 if (tg3_nvram_read_swab(tp, 0, &magic) != 0) 8424 if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8426 return -EIO; 8425 return -EIO;
@@ -8474,7 +8473,6 @@ static int tg3_test_nvram(struct tg3 *tp)
8474 u8 data[NVRAM_SELFBOOT_DATA_SIZE]; 8473 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8475 u8 parity[NVRAM_SELFBOOT_DATA_SIZE]; 8474 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8476 u8 *buf8 = (u8 *) buf; 8475 u8 *buf8 = (u8 *) buf;
8477 int j, k;
8478 8476
8479 /* Separate the parity bits and the data bytes. */ 8477 /* Separate the parity bits and the data bytes. */
8480 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) { 8478 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
@@ -10730,7 +10728,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10730 */ 10728 */
10731 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) { 10729 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10732 u32 pm_reg; 10730 u32 pm_reg;
10733 u16 pci_cmd;
10734 10731
10735 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG; 10732 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10736 10733
@@ -11876,7 +11873,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
11876 INIT_WORK(&tp->reset_task, tg3_reset_task); 11873 INIT_WORK(&tp->reset_task, tg3_reset_task);
11877 11874
11878 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len); 11875 tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11879 if (tp->regs == 0UL) { 11876 if (!tp->regs) {
11880 printk(KERN_ERR PFX "Cannot map device registers, " 11877 printk(KERN_ERR PFX "Cannot map device registers, "
11881 "aborting.\n"); 11878 "aborting.\n");
11882 err = -ENOMEM; 11879 err = -ENOMEM;