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authorMatt Carlson <mcarlson@broadcom.com>2007-10-21 19:17:55 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-22 05:59:51 -0400
commit8a6eac90e21633e054e17d21454a2c26824aeb18 (patch)
tree0d9bce8b6c5f359d6532f854467c71eb83356d90 /drivers/net/tg3.c
parent9c8a620e7f85fff050a54697da44bbd1a66e8e0b (diff)
[TG3]: PCI command adjustment
This patch changes the way the driver works with the PCI command register. It adjusts the access size from dwords to words. This patch is done both as a PCI configuration space cleanup and as preparatory work for PCI error recovery. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c7
1 files changed, 2 insertions, 5 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 98f465828110..328eb4adc10b 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -5029,10 +5029,7 @@ static int tg3_poll_fw(struct tg3 *tp)
5029/* Save PCI command register before chip reset */ 5029/* Save PCI command register before chip reset */
5030static void tg3_save_pci_state(struct tg3 *tp) 5030static void tg3_save_pci_state(struct tg3 *tp)
5031{ 5031{
5032 u32 val; 5032 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
5033
5034 pci_read_config_dword(tp->pdev, TG3PCI_COMMAND, &val);
5035 tp->pci_cmd = val;
5036} 5033}
5037 5034
5038/* Restore PCI state after chip reset */ 5035/* Restore PCI state after chip reset */
@@ -5055,7 +5052,7 @@ static void tg3_restore_pci_state(struct tg3 *tp)
5055 PCISTATE_ALLOW_APE_SHMEM_WR; 5052 PCISTATE_ALLOW_APE_SHMEM_WR;
5056 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val); 5053 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
5057 5054
5058 pci_write_config_dword(tp->pdev, TG3PCI_COMMAND, tp->pci_cmd); 5055 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
5059 5056
5060 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) { 5057 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
5061 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, 5058 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,