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authorMichael Chan <mchan@broadcom.com>2006-12-07 03:19:40 -0500
committerDavid S. Miller <davem@davemloft.net>2006-12-07 03:19:40 -0500
commit5d64ad34f468278ce66f9eb4d876dd221490e94c (patch)
treeafbb4b855a912592ac6f179e146af000810fa56b /drivers/net/tg3.c
parent456c38f9682645cbb0537cb4e16848a28c1d3a76 (diff)
[TG3]: Fix Phy loopback.
Phy loopback on most 10/100 devices need to be run in 1Gbps mode in GMII mode. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c23
1 files changed, 10 insertions, 13 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index d9123c9adc1e..e6561c1d85d6 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -8781,17 +8781,20 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8781 tg3_writephy(tp, 0x10, phy & ~0x4000); 8781 tg3_writephy(tp, 0x10, phy & ~0x4000);
8782 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest); 8782 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8783 } 8783 }
8784 } 8784 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8785 val = BMCR_LOOPBACK | BMCR_FULLDPLX; 8785 } else
8786 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) 8786 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8787 val |= BMCR_SPEED100;
8788 else
8789 val |= BMCR_SPEED1000;
8790 8787
8791 tg3_writephy(tp, MII_BMCR, val); 8788 tg3_writephy(tp, MII_BMCR, val);
8792 udelay(40); 8789 udelay(40);
8793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) 8790
8791 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8792 MAC_MODE_LINK_POLARITY;
8793 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8794 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800); 8794 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8795 mac_mode |= MAC_MODE_PORT_MODE_MII;
8796 } else
8797 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8795 8798
8796 /* reset to prevent losing 1st rx packet intermittently */ 8799 /* reset to prevent losing 1st rx packet intermittently */
8797 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) { 8800 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
@@ -8799,12 +8802,6 @@ static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8799 udelay(10); 8802 udelay(10);
8800 tw32_f(MAC_RX_MODE, tp->rx_mode); 8803 tw32_f(MAC_RX_MODE, tp->rx_mode);
8801 } 8804 }
8802 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8803 MAC_MODE_LINK_POLARITY;
8804 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8805 mac_mode |= MAC_MODE_PORT_MODE_MII;
8806 else
8807 mac_mode |= MAC_MODE_PORT_MODE_GMII;
8808 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) { 8805 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8809 mac_mode &= ~MAC_MODE_LINK_POLARITY; 8806 mac_mode &= ~MAC_MODE_LINK_POLARITY;
8810 tg3_writephy(tp, MII_TG3_EXT_CTRL, 8807 tg3_writephy(tp, MII_TG3_EXT_CTRL,