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authorMatt Carlson <mcarlson@broadcom.com>2010-09-30 06:34:31 -0400
committerDavid S. Miller <davem@davemloft.net>2010-10-01 03:24:42 -0400
commitd309a46e42542223946d3a9e4e239fdc945cb53e (patch)
tree43fae359546e61d0bda67d903d03db11d227033c /drivers/net/tg3.c
parent66cfd1bd05a7a1c31c9cdbb2ddf5c57d1cddc5f6 (diff)
tg3: 5719: Prevent tx data corruption
This patch enables a bit that prevents read DMA overflows and adjusts the txmbuf margin from the hardware default. The combination of these modifications prevents a tx data corruption issue we were seeing on the 5719. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 982ed44f0752..b6388be1cd1e 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -7857,7 +7857,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7857 tw32(BUFMGR_DMA_HIGH_WATER, 7857 tw32(BUFMGR_DMA_HIGH_WATER,
7858 tp->bufmgr_config.dma_high_water); 7858 tp->bufmgr_config.dma_high_water);
7859 7859
7860 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE); 7860 val = BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE;
7861 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719)
7862 val |= BUFMGR_MODE_NO_TX_UNDERRUN;
7863 tw32(BUFMGR_MODE, val);
7861 for (i = 0; i < 2000; i++) { 7864 for (i = 0; i < 2000; i++) {
7862 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE) 7865 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7863 break; 7866 break;
@@ -8037,6 +8040,13 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
8037 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX); 8040 val | TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX);
8038 } 8041 }
8039 8042
8043 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719) {
8044 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
8045 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val |
8046 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K |
8047 TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K);
8048 }
8049
8040 /* Receive/send statistics. */ 8050 /* Receive/send statistics. */
8041 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) { 8051 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
8042 val = tr32(RCVLPC_STATS_ENABLE); 8052 val = tr32(RCVLPC_STATS_ENABLE);