diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2011-07-20 06:20:52 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-07-21 15:36:15 -0400 |
commit | b715ce947f51c6637e78b262501f0c4ff9d848cc (patch) | |
tree | c3cb340a096d646cf2d1440309d87f4fd2b767a8 /drivers/net/tg3.c | |
parent | be671947b5b3efc6863ff429c1f265aa38e291db (diff) |
tg3: Fix link down notify failure when EEE disabled
Occasionally, when the network cable is removed after a successful
autonegotiation, the device will not send a link down interrupt to the
driver. This happens because of a bad interaction of an EEE
workaround. The fix is to adjust the code so that the root cause
condition does not happen.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 38 |
1 files changed, 25 insertions, 13 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index 2a9ab99baafd..e0413bcce0f5 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -1858,6 +1858,12 @@ static void tg3_phy_eee_adjust(struct tg3 *tp, u32 current_link_up) | |||
1858 | } | 1858 | } |
1859 | 1859 | ||
1860 | if (!tp->setlpicnt) { | 1860 | if (!tp->setlpicnt) { |
1861 | if (current_link_up == 1 && | ||
1862 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | ||
1863 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0000); | ||
1864 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | ||
1865 | } | ||
1866 | |||
1861 | val = tr32(TG3_CPMU_EEE_MODE); | 1867 | val = tr32(TG3_CPMU_EEE_MODE); |
1862 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); | 1868 | tw32(TG3_CPMU_EEE_MODE, val & ~TG3_CPMU_EEEMD_LPI_ENABLE); |
1863 | } | 1869 | } |
@@ -1872,7 +1878,9 @@ static void tg3_phy_eee_enable(struct tg3 *tp) | |||
1872 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || | 1878 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5719 || |
1873 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && | 1879 | GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) && |
1874 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { | 1880 | !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) { |
1875 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, 0x0003); | 1881 | val = MII_TG3_DSP_TAP26_ALNOKO | |
1882 | MII_TG3_DSP_TAP26_RMRXSTO; | ||
1883 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | ||
1876 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | 1884 | TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
1877 | } | 1885 | } |
1878 | 1886 | ||
@@ -3128,13 +3136,26 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) | |||
3128 | if (!err) { | 3136 | if (!err) { |
3129 | u32 err2; | 3137 | u32 err2; |
3130 | 3138 | ||
3139 | val = 0; | ||
3140 | /* Advertise 100-BaseTX EEE ability */ | ||
3141 | if (advertise & ADVERTISED_100baseT_Full) | ||
3142 | val |= MDIO_AN_EEE_ADV_100TX; | ||
3143 | /* Advertise 1000-BaseT EEE ability */ | ||
3144 | if (advertise & ADVERTISED_1000baseT_Full) | ||
3145 | val |= MDIO_AN_EEE_ADV_1000T; | ||
3146 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | ||
3147 | if (err) | ||
3148 | val = 0; | ||
3149 | |||
3131 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { | 3150 | switch (GET_ASIC_REV(tp->pci_chip_rev_id)) { |
3132 | case ASIC_REV_5717: | 3151 | case ASIC_REV_5717: |
3133 | case ASIC_REV_57765: | 3152 | case ASIC_REV_57765: |
3134 | case ASIC_REV_5719: | 3153 | case ASIC_REV_5719: |
3135 | val = MII_TG3_DSP_TAP26_ALNOKO | | 3154 | /* If we advertised any eee advertisements above... */ |
3136 | MII_TG3_DSP_TAP26_RMRXSTO | | 3155 | if (val) |
3137 | MII_TG3_DSP_TAP26_OPCSINPT; | 3156 | val = MII_TG3_DSP_TAP26_ALNOKO | |
3157 | MII_TG3_DSP_TAP26_RMRXSTO | | ||
3158 | MII_TG3_DSP_TAP26_OPCSINPT; | ||
3138 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); | 3159 | tg3_phydsp_write(tp, MII_TG3_DSP_TAP26, val); |
3139 | /* Fall through */ | 3160 | /* Fall through */ |
3140 | case ASIC_REV_5720: | 3161 | case ASIC_REV_5720: |
@@ -3143,15 +3164,6 @@ static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl) | |||
3143 | MII_TG3_DSP_CH34TP2_HIBW01); | 3164 | MII_TG3_DSP_CH34TP2_HIBW01); |
3144 | } | 3165 | } |
3145 | 3166 | ||
3146 | val = 0; | ||
3147 | /* Advertise 100-BaseTX EEE ability */ | ||
3148 | if (advertise & ADVERTISED_100baseT_Full) | ||
3149 | val |= MDIO_AN_EEE_ADV_100TX; | ||
3150 | /* Advertise 1000-BaseT EEE ability */ | ||
3151 | if (advertise & ADVERTISED_1000baseT_Full) | ||
3152 | val |= MDIO_AN_EEE_ADV_1000T; | ||
3153 | err = tg3_phy_cl45_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val); | ||
3154 | |||
3155 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); | 3167 | err2 = TG3_PHY_AUXCTL_SMDSP_DISABLE(tp); |
3156 | if (!err) | 3168 | if (!err) |
3157 | err = err2; | 3169 | err = err2; |