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authorDavid S. Miller <davem@davemloft.net>2010-01-23 03:31:06 -0500
committerDavid S. Miller <davem@davemloft.net>2010-01-23 03:31:06 -0500
commit51c24aaacaea90c8e87f1dec75a2ac7622b593f8 (patch)
tree9f54936c87764bef75e97395cb56b7d1e0df24c6 /drivers/net/tg3.c
parent4276e47e2d1c85a2477caf0d22b91c4f2377fba8 (diff)
parent6be325719b3e54624397e413efd4b33a997e55a3 (diff)
Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c27
1 files changed, 19 insertions, 8 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index eaed2aa09e1f..7195bdec17f3 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4,7 +4,7 @@
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com) 4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com) 5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc. 6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation. 7 * Copyright (C) 2005-2010 Broadcom Corporation.
8 * 8 *
9 * Firmware is: 9 * Firmware is:
10 * Derived from proprietary unpublished source code, 10 * Derived from proprietary unpublished source code,
@@ -68,8 +68,8 @@
68 68
69#define DRV_MODULE_NAME "tg3" 69#define DRV_MODULE_NAME "tg3"
70#define PFX DRV_MODULE_NAME ": " 70#define PFX DRV_MODULE_NAME ": "
71#define DRV_MODULE_VERSION "3.105" 71#define DRV_MODULE_VERSION "3.106"
72#define DRV_MODULE_RELDATE "December 2, 2009" 72#define DRV_MODULE_RELDATE "January 12, 2010"
73 73
74#define TG3_DEF_MAC_MODE 0 74#define TG3_DEF_MAC_MODE 0
75#define TG3_DEF_RX_MODE 0 75#define TG3_DEF_RX_MODE 0
@@ -1043,7 +1043,11 @@ static void tg3_mdio_start(struct tg3 *tp)
1043 else 1043 else
1044 tp->phy_addr = 1; 1044 tp->phy_addr = 1;
1045 1045
1046 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES; 1046 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
1047 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1048 else
1049 is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
1050 TG3_CPMU_PHY_STRAP_IS_SERDES;
1047 if (is_serdes) 1051 if (is_serdes)
1048 tp->phy_addr += 7; 1052 tp->phy_addr += 7;
1049 } else 1053 } else
@@ -4707,8 +4711,9 @@ next_pkt:
4707 (*post_ptr)++; 4711 (*post_ptr)++;
4708 4712
4709 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) { 4713 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4710 u32 idx = *post_ptr % TG3_RX_RING_SIZE; 4714 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4711 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx); 4715 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4716 tpr->rx_std_prod_idx);
4712 work_mask &= ~RXD_OPAQUE_RING_STD; 4717 work_mask &= ~RXD_OPAQUE_RING_STD;
4713 rx_std_posted = 0; 4718 rx_std_posted = 0;
4714 } 4719 }
@@ -7773,7 +7778,7 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7773 ((u64) tpr->rx_std_mapping >> 32)); 7778 ((u64) tpr->rx_std_mapping >> 32));
7774 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 7779 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7775 ((u64) tpr->rx_std_mapping & 0xffffffff)); 7780 ((u64) tpr->rx_std_mapping & 0xffffffff));
7776 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) 7781 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7777 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, 7782 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7778 NIC_SRAM_RX_BUFFER_DESC); 7783 NIC_SRAM_RX_BUFFER_DESC);
7779 7784
@@ -12172,7 +12177,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12172 12177
12173 tp->phy_id = eeprom_phy_id; 12178 tp->phy_id = eeprom_phy_id;
12174 if (eeprom_phy_serdes) { 12179 if (eeprom_phy_serdes) {
12175 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) 12180 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
12181 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
12176 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES; 12182 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12177 else 12183 else
12178 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES; 12184 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
@@ -13437,6 +13443,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
13437 if (err) 13443 if (err)
13438 return err; 13444 return err;
13439 13445
13446 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
13447 (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0 ||
13448 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
13449 return -ENOTSUPP;
13450
13440 /* Initialize data/descriptor byte/word swapping. */ 13451 /* Initialize data/descriptor byte/word swapping. */
13441 val = tr32(GRC_MODE); 13452 val = tr32(GRC_MODE);
13442 val &= GRC_MODE_HOST_STACKUP; 13453 val &= GRC_MODE_HOST_STACKUP;