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authorMatt Carlson <mcarlson@broadcom.com>2009-11-13 08:03:46 -0500
committerDavid S. Miller <davem@davemloft.net>2009-11-16 01:14:49 -0500
commit411da6407e778bf946911df08bb5afc505422f31 (patch)
tree24bd8cde28cb13191f029796bbc7fa4806a8fbd2 /drivers/net/tg3.c
parent86b21e59c9a65c8e46d35ac6c4220f63639828c6 (diff)
tg3: rename rx_[std|jmb]_ptr
A later patch is going to add consumer indicies for the producer rings. To keep things readable, this patch renames rx_[std|jmb]_ptr to rx_[std|jmb]_prod_idx. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 00e7e14fd3f7..59a715a25623 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -4564,13 +4564,13 @@ static int tg3_rx(struct tg3_napi *tnapi, int budget)
4564 ri = &tpr->rx_std_buffers[desc_idx]; 4564 ri = &tpr->rx_std_buffers[desc_idx];
4565 dma_addr = pci_unmap_addr(ri, mapping); 4565 dma_addr = pci_unmap_addr(ri, mapping);
4566 skb = ri->skb; 4566 skb = ri->skb;
4567 post_ptr = &tpr->rx_std_ptr; 4567 post_ptr = &tpr->rx_std_prod_idx;
4568 rx_std_posted++; 4568 rx_std_posted++;
4569 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) { 4569 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4570 ri = &tpr->rx_jmb_buffers[desc_idx]; 4570 ri = &tpr->rx_jmb_buffers[desc_idx];
4571 dma_addr = pci_unmap_addr(ri, mapping); 4571 dma_addr = pci_unmap_addr(ri, mapping);
4572 skb = ri->skb; 4572 skb = ri->skb;
4573 post_ptr = &tpr->rx_jmb_ptr; 4573 post_ptr = &tpr->rx_jmb_prod_idx;
4574 } else 4574 } else
4575 goto next_pkt_nopost; 4575 goto next_pkt_nopost;
4576 4576
@@ -4687,12 +4687,12 @@ next_pkt_nopost:
4687 4687
4688 /* Refill RX ring(s). */ 4688 /* Refill RX ring(s). */
4689 if (work_mask & RXD_OPAQUE_RING_STD) { 4689 if (work_mask & RXD_OPAQUE_RING_STD) {
4690 sw_idx = tpr->rx_std_ptr % TG3_RX_RING_SIZE; 4690 sw_idx = tpr->rx_std_prod_idx % TG3_RX_RING_SIZE;
4691 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, 4691 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
4692 sw_idx); 4692 sw_idx);
4693 } 4693 }
4694 if (work_mask & RXD_OPAQUE_RING_JUMBO) { 4694 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4695 sw_idx = tpr->rx_jmb_ptr % TG3_RX_JUMBO_RING_SIZE; 4695 sw_idx = tpr->rx_jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4696 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 4696 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
4697 sw_idx); 4697 sw_idx);
4698 } 4698 }
@@ -7509,14 +7509,14 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7509 7509
7510 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val); 7510 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7511 7511
7512 tpr->rx_std_ptr = tp->rx_pending; 7512 tpr->rx_std_prod_idx = tp->rx_pending;
7513 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, 7513 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
7514 tpr->rx_std_ptr); 7514 tpr->rx_std_prod_idx);
7515 7515
7516 tpr->rx_jmb_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ? 7516 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7517 tp->rx_jumbo_pending : 0; 7517 tp->rx_jumbo_pending : 0;
7518 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 7518 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
7519 tpr->rx_jmb_ptr); 7519 tpr->rx_jmb_prod_idx);
7520 7520
7521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) { 7521 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
7522 tw32(STD_REPLENISH_LWM, 32); 7522 tw32(STD_REPLENISH_LWM, 32);