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authorJohn W. Linville <linville@tuxdriver.com>2005-04-21 19:56:08 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2005-04-21 19:56:08 -0400
commit2052da946096590035438626afbc7f329d2549d8 (patch)
tree4cdb3bf407c8573f26a5a373016520b2ef44e8c7 /drivers/net/tg3.c
parentebc37b611616ad46dce7d590b15ad655aa50213a (diff)
[TG3]: add basic bcm5752 support
Add ASIC_REV_5752 definition. Track-down all references to ASIC_REV_5750 and mirror them with references to the newly defined ASIC_REV_5752. Signed-off-by: John W. Linville <linville@tuxdriver.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c63
1 files changed, 42 insertions, 21 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 12de80884b1a..34301ef34714 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -86,7 +86,8 @@
86#define TG3_MIN_MTU 60 86#define TG3_MIN_MTU 60
87#define TG3_MAX_MTU(tp) \ 87#define TG3_MAX_MTU(tp) \
88 ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \ 88 ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
89 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) ? 9000 : 1500) 89 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && \
90 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) ? 9000 : 1500)
90 91
91/* These numbers seem to be hard coded in the NIC firmware somehow. 92/* These numbers seem to be hard coded in the NIC firmware somehow.
92 * You can't change the ring sizes, but you can change where you place 93 * You can't change the ring sizes, but you can change where you place
@@ -861,7 +862,8 @@ out:
861 /* Cannot do read-modify-write on 5401 */ 862 /* Cannot do read-modify-write on 5401 */
862 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20); 863 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
863 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && 864 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
864 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) { 865 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
866 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
865 u32 phy_reg; 867 u32 phy_reg;
866 868
867 /* Set bit 14 with read-modify-write to preserve other bits */ 869 /* Set bit 14 with read-modify-write to preserve other bits */
@@ -874,7 +876,8 @@ out:
874 * jumbo frames transmission. 876 * jumbo frames transmission.
875 */ 877 */
876 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && 878 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
877 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) { 879 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
880 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
878 u32 phy_reg; 881 u32 phy_reg;
879 882
880 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg)) 883 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -1068,7 +1071,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state)
1068 mac_mode = MAC_MODE_PORT_MODE_TBI; 1071 mac_mode = MAC_MODE_PORT_MODE_TBI;
1069 } 1072 }
1070 1073
1071 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) 1074 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
1075 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
1072 tw32(MAC_LED_CTRL, tp->led_ctrl); 1076 tw32(MAC_LED_CTRL, tp->led_ctrl);
1073 1077
1074 if (((power_caps & PCI_PM_CAP_PME_D3cold) && 1078 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
@@ -3967,7 +3971,8 @@ static int tg3_chip_reset(struct tg3 *tp)
3967 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg); 3971 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
3968 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 3972 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
3969 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 3973 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
3970 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 3974 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
3975 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
3971 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 3976 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
3972 } 3977 }
3973 } 3978 }
@@ -5041,7 +5046,8 @@ static int tg3_reset_hw(struct tg3 *tp)
5041 tw32(GRC_MISC_CFG, val); 5046 tw32(GRC_MISC_CFG, val);
5042 5047
5043 /* Initialize MBUF/DESC pool. */ 5048 /* Initialize MBUF/DESC pool. */
5044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 5049 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
5050 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
5045 /* Do nothing. */ 5051 /* Do nothing. */
5046 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) { 5052 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
5047 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE); 5053 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -5240,7 +5246,8 @@ static int tg3_reset_hw(struct tg3 *tp)
5240 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE; 5246 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
5241 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && 5247 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5242 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || 5248 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5243 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) { 5249 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
5250 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
5244 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE && 5251 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
5245 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || 5252 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5246 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { 5253 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
@@ -5355,7 +5362,8 @@ static int tg3_reset_hw(struct tg3 *tp)
5355 5362
5356 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 && 5363 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
5357 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) || 5364 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
5358 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 5365 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
5366 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
5359 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) && 5367 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
5360 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 || 5368 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
5361 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) { 5369 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
@@ -7028,7 +7036,8 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
7028 tw32(NVRAM_CFG1, nvcfg1); 7036 tw32(NVRAM_CFG1, nvcfg1);
7029 } 7037 }
7030 7038
7031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7039 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7040 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7032 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) { 7041 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
7033 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED: 7042 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
7034 tp->nvram_jedecnum = JEDEC_ATMEL; 7043 tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -7093,7 +7102,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
7093 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) { 7102 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
7094 tp->tg3_flags |= TG3_FLAG_NVRAM; 7103 tp->tg3_flags |= TG3_FLAG_NVRAM;
7095 7104
7096 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7106 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7097 u32 nvaccess = tr32(NVRAM_ACCESS); 7107 u32 nvaccess = tr32(NVRAM_ACCESS);
7098 7108
7099 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); 7109 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7102,7 +7112,8 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
7102 tg3_get_nvram_info(tp); 7112 tg3_get_nvram_info(tp);
7103 tg3_get_nvram_size(tp); 7113 tg3_get_nvram_size(tp);
7104 7114
7105 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7115 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7116 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7106 u32 nvaccess = tr32(NVRAM_ACCESS); 7117 u32 nvaccess = tr32(NVRAM_ACCESS);
7107 7118
7108 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); 7119 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7195,7 +7206,8 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7195 7206
7196 tg3_nvram_lock(tp); 7207 tg3_nvram_lock(tp);
7197 7208
7198 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7209 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7210 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7199 u32 nvaccess = tr32(NVRAM_ACCESS); 7211 u32 nvaccess = tr32(NVRAM_ACCESS);
7200 7212
7201 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); 7213 tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7210,7 +7222,8 @@ static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
7210 7222
7211 tg3_nvram_unlock(tp); 7223 tg3_nvram_unlock(tp);
7212 7224
7213 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7225 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7226 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7214 u32 nvaccess = tr32(NVRAM_ACCESS); 7227 u32 nvaccess = tr32(NVRAM_ACCESS);
7215 7228
7216 tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); 7229 tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7438,7 +7451,8 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7438 7451
7439 tg3_nvram_lock(tp); 7452 tg3_nvram_lock(tp);
7440 7453
7441 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7454 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7455 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7442 u32 nvaccess = tr32(NVRAM_ACCESS); 7456 u32 nvaccess = tr32(NVRAM_ACCESS);
7443 7457
7444 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE); 7458 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7463,7 +7477,8 @@ static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
7463 grc_mode = tr32(GRC_MODE); 7477 grc_mode = tr32(GRC_MODE);
7464 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE); 7478 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
7465 7479
7466 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7480 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7481 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7467 u32 nvaccess = tr32(NVRAM_ACCESS); 7482 u32 nvaccess = tr32(NVRAM_ACCESS);
7468 7483
7469 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE); 7484 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7581,7 +7596,8 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
7581 } else 7596 } else
7582 eeprom_phy_id = 0; 7597 eeprom_phy_id = 0;
7583 7598
7584 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) { 7599 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7600 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
7585 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK | 7601 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
7586 SHASTA_EXT_LED_MODE_MASK); 7602 SHASTA_EXT_LED_MODE_MASK);
7587 } else 7603 } else
@@ -7634,7 +7650,8 @@ static int __devinit tg3_phy_probe(struct tg3 *tp)
7634 7650
7635 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) { 7651 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
7636 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF; 7652 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
7637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 7653 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7654 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7638 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 7655 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7639 } 7656 }
7640 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL) 7657 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
@@ -7932,10 +7949,12 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
7932 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff; 7949 tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
7933 7950
7934 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) || 7951 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
7935 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) 7952 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
7953 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752))
7936 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS; 7954 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
7937 7955
7938 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 7956 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
7957 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7939 tp->tg3_flags2 |= TG3_FLG2_HW_TSO; 7958 tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
7940 7959
7941 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0) 7960 if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
@@ -8066,7 +8085,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
8066 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG; 8085 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
8067 8086
8068 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || 8087 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
8069 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 8088 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8089 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8070 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG; 8090 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
8071 8091
8072 /* Only 5701 and later support tagged irq status mode. 8092 /* Only 5701 and later support tagged irq status mode.
@@ -8462,7 +8482,8 @@ static int __devinit tg3_test_dma(struct tg3 *tp)
8462 tp->dma_rwctrl |= 0x00180000; 8482 tp->dma_rwctrl |= 0x00180000;
8463 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) { 8483 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
8464 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 || 8484 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
8465 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) 8485 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
8486 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
8466 tp->dma_rwctrl |= 0x003f0000; 8487 tp->dma_rwctrl |= 0x003f0000;
8467 else 8488 else
8468 tp->dma_rwctrl |= 0x003f000f; 8489 tp->dma_rwctrl |= 0x003f000f;