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authorMichael Chan <mchan@broadcom.com>2005-07-25 15:31:48 -0400
committerDavid S. Miller <davem@davemloft.net>2005-07-25 15:31:48 -0400
commitfdfec1726b14b4b2121adcfcbba98d4cc1a61751 (patch)
tree7cb407d307526b41165f974ee318c36b92e04a9e /drivers/net/tg3.c
parent7e72aad48c3790636bfa006f3b0027852ccad47e (diff)
[TG3]: consolidate all DMA water mark settings
Consolidate all DMA watermark settings for standard and jumbo frames on all chips in tg3_init_bufmgr_config() and add new settings for 5780. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c53
1 files changed, 30 insertions, 23 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index eca4b91454c0..2b7d99fc257c 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -9826,19 +9826,35 @@ static void __devinit tg3_init_link_config(struct tg3 *tp)
9826 9826
9827static void __devinit tg3_init_bufmgr_config(struct tg3 *tp) 9827static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
9828{ 9828{
9829 tp->bufmgr_config.mbuf_read_dma_low_water = 9829 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
9830 DEFAULT_MB_RDMA_LOW_WATER; 9830 tp->bufmgr_config.mbuf_read_dma_low_water =
9831 tp->bufmgr_config.mbuf_mac_rx_low_water = 9831 DEFAULT_MB_RDMA_LOW_WATER_5705;
9832 DEFAULT_MB_MACRX_LOW_WATER; 9832 tp->bufmgr_config.mbuf_mac_rx_low_water =
9833 tp->bufmgr_config.mbuf_high_water = 9833 DEFAULT_MB_MACRX_LOW_WATER_5705;
9834 DEFAULT_MB_HIGH_WATER; 9834 tp->bufmgr_config.mbuf_high_water =
9835 9835 DEFAULT_MB_HIGH_WATER_5705;
9836 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo = 9836
9837 DEFAULT_MB_RDMA_LOW_WATER_JUMBO; 9837 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9838 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo = 9838 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
9839 DEFAULT_MB_MACRX_LOW_WATER_JUMBO; 9839 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9840 tp->bufmgr_config.mbuf_high_water_jumbo = 9840 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
9841 DEFAULT_MB_HIGH_WATER_JUMBO; 9841 tp->bufmgr_config.mbuf_high_water_jumbo =
9842 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
9843 } else {
9844 tp->bufmgr_config.mbuf_read_dma_low_water =
9845 DEFAULT_MB_RDMA_LOW_WATER;
9846 tp->bufmgr_config.mbuf_mac_rx_low_water =
9847 DEFAULT_MB_MACRX_LOW_WATER;
9848 tp->bufmgr_config.mbuf_high_water =
9849 DEFAULT_MB_HIGH_WATER;
9850
9851 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
9852 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
9853 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
9854 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
9855 tp->bufmgr_config.mbuf_high_water_jumbo =
9856 DEFAULT_MB_HIGH_WATER_JUMBO;
9857 }
9842 9858
9843 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER; 9859 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
9844 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER; 9860 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
@@ -10052,8 +10068,6 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10052 10068
10053 tg3_init_link_config(tp); 10069 tg3_init_link_config(tp);
10054 10070
10055 tg3_init_bufmgr_config(tp);
10056
10057 tp->rx_pending = TG3_DEF_RX_RING_PENDING; 10071 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
10058 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING; 10072 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
10059 tp->tx_pending = TG3_DEF_TX_RING_PENDING; 10073 tp->tx_pending = TG3_DEF_TX_RING_PENDING;
@@ -10082,14 +10096,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
10082 goto err_out_iounmap; 10096 goto err_out_iounmap;
10083 } 10097 }
10084 10098
10085 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) { 10099 tg3_init_bufmgr_config(tp);
10086 tp->bufmgr_config.mbuf_read_dma_low_water =
10087 DEFAULT_MB_RDMA_LOW_WATER_5705;
10088 tp->bufmgr_config.mbuf_mac_rx_low_water =
10089 DEFAULT_MB_MACRX_LOW_WATER_5705;
10090 tp->bufmgr_config.mbuf_high_water =
10091 DEFAULT_MB_HIGH_WATER_5705;
10092 }
10093 10100
10094#if TG3_TSO_SUPPORT != 0 10101#if TG3_TSO_SUPPORT != 0
10095 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) { 10102 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {