diff options
author | Michael Chan <mchan@broadcom.com> | 2005-04-21 20:13:25 -0400 |
---|---|---|
committer | David S. Miller <davem@sunset.davemloft.net> | 2005-04-21 20:13:25 -0400 |
commit | 88b06bc26b87cf0490b0e3faea7fefc7549dd75d (patch) | |
tree | ffba7c235ad94e3c1e0074cb209504e6ea25afe3 /drivers/net/tg3.c | |
parent | 1c8594b48b00a98d12477355e944e165a5f64cd5 (diff) |
[TG3]: Add msi support
Add MSI support for 5751 C0 and 5752.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 76 |
1 files changed, 71 insertions, 5 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index fb3eb6f8a737..2a17af9bd1ce 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -2907,6 +2907,43 @@ static inline unsigned int tg3_has_work(struct net_device *dev, struct tg3 *tp) | |||
2907 | return work_exists; | 2907 | return work_exists; |
2908 | } | 2908 | } |
2909 | 2909 | ||
2910 | /* MSI ISR - No need to check for interrupt sharing and no need to | ||
2911 | * flush status block and interrupt mailbox. PCI ordering rules | ||
2912 | * guarantee that MSI will arrive after the status block. | ||
2913 | */ | ||
2914 | static irqreturn_t tg3_msi(int irq, void *dev_id, struct pt_regs *regs) | ||
2915 | { | ||
2916 | struct net_device *dev = dev_id; | ||
2917 | struct tg3 *tp = netdev_priv(dev); | ||
2918 | struct tg3_hw_status *sblk = tp->hw_status; | ||
2919 | unsigned long flags; | ||
2920 | |||
2921 | spin_lock_irqsave(&tp->lock, flags); | ||
2922 | |||
2923 | /* | ||
2924 | * writing any value to intr-mbox-0 clears PCI INTA# and | ||
2925 | * chip-internal interrupt pending events. | ||
2926 | * writing non-zero to intr-mbox-0 additional tells the | ||
2927 | * NIC to stop sending us irqs, engaging "in-intr-handler" | ||
2928 | * event coalescing. | ||
2929 | */ | ||
2930 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001); | ||
2931 | sblk->status &= ~SD_STATUS_UPDATED; | ||
2932 | |||
2933 | if (likely(tg3_has_work(dev, tp))) | ||
2934 | netif_rx_schedule(dev); /* schedule NAPI poll */ | ||
2935 | else { | ||
2936 | /* no work, re-enable interrupts | ||
2937 | */ | ||
2938 | tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, | ||
2939 | 0x00000000); | ||
2940 | } | ||
2941 | |||
2942 | spin_unlock_irqrestore(&tp->lock, flags); | ||
2943 | |||
2944 | return IRQ_RETVAL(1); | ||
2945 | } | ||
2946 | |||
2910 | static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs) | 2947 | static irqreturn_t tg3_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
2911 | { | 2948 | { |
2912 | struct net_device *dev = dev_id; | 2949 | struct net_device *dev = dev_id; |
@@ -2965,7 +3002,9 @@ static int tg3_halt(struct tg3 *); | |||
2965 | #ifdef CONFIG_NET_POLL_CONTROLLER | 3002 | #ifdef CONFIG_NET_POLL_CONTROLLER |
2966 | static void tg3_poll_controller(struct net_device *dev) | 3003 | static void tg3_poll_controller(struct net_device *dev) |
2967 | { | 3004 | { |
2968 | tg3_interrupt(dev->irq, dev, NULL); | 3005 | struct tg3 *tp = netdev_priv(dev); |
3006 | |||
3007 | tg3_interrupt(tp->pdev->irq, dev, NULL); | ||
2969 | } | 3008 | } |
2970 | #endif | 3009 | #endif |
2971 | 3010 | ||
@@ -5778,10 +5817,29 @@ static int tg3_open(struct net_device *dev) | |||
5778 | if (err) | 5817 | if (err) |
5779 | return err; | 5818 | return err; |
5780 | 5819 | ||
5781 | err = request_irq(dev->irq, tg3_interrupt, | 5820 | if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) && |
5782 | SA_SHIRQ, dev->name, dev); | 5821 | (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) && |
5822 | (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX)) { | ||
5823 | if (pci_enable_msi(tp->pdev) == 0) { | ||
5824 | u32 msi_mode; | ||
5825 | |||
5826 | msi_mode = tr32(MSGINT_MODE); | ||
5827 | tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE); | ||
5828 | tp->tg3_flags2 |= TG3_FLG2_USING_MSI; | ||
5829 | } | ||
5830 | } | ||
5831 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) | ||
5832 | err = request_irq(tp->pdev->irq, tg3_msi, | ||
5833 | 0, dev->name, dev); | ||
5834 | else | ||
5835 | err = request_irq(tp->pdev->irq, tg3_interrupt, | ||
5836 | SA_SHIRQ, dev->name, dev); | ||
5783 | 5837 | ||
5784 | if (err) { | 5838 | if (err) { |
5839 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | ||
5840 | pci_disable_msi(tp->pdev); | ||
5841 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | ||
5842 | } | ||
5785 | tg3_free_consistent(tp); | 5843 | tg3_free_consistent(tp); |
5786 | return err; | 5844 | return err; |
5787 | } | 5845 | } |
@@ -5811,7 +5869,11 @@ static int tg3_open(struct net_device *dev) | |||
5811 | spin_unlock_irq(&tp->lock); | 5869 | spin_unlock_irq(&tp->lock); |
5812 | 5870 | ||
5813 | if (err) { | 5871 | if (err) { |
5814 | free_irq(dev->irq, dev); | 5872 | free_irq(tp->pdev->irq, dev); |
5873 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | ||
5874 | pci_disable_msi(tp->pdev); | ||
5875 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | ||
5876 | } | ||
5815 | tg3_free_consistent(tp); | 5877 | tg3_free_consistent(tp); |
5816 | return err; | 5878 | return err; |
5817 | } | 5879 | } |
@@ -6086,7 +6148,11 @@ static int tg3_close(struct net_device *dev) | |||
6086 | spin_unlock(&tp->tx_lock); | 6148 | spin_unlock(&tp->tx_lock); |
6087 | spin_unlock_irq(&tp->lock); | 6149 | spin_unlock_irq(&tp->lock); |
6088 | 6150 | ||
6089 | free_irq(dev->irq, dev); | 6151 | free_irq(tp->pdev->irq, dev); |
6152 | if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) { | ||
6153 | pci_disable_msi(tp->pdev); | ||
6154 | tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI; | ||
6155 | } | ||
6090 | 6156 | ||
6091 | memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev), | 6157 | memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev), |
6092 | sizeof(tp->net_stats_prev)); | 6158 | sizeof(tp->net_stats_prev)); |