aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.c
diff options
context:
space:
mode:
authorGary Zambrano <zambrano@broadcom.com>2007-05-05 14:52:19 -0400
committerDavid S. Miller <davem@davemloft.net>2007-05-05 14:52:19 -0400
commita85feb8cfc53c08b6f0d770f930ca9cc6885f414 (patch)
treef5806132fb6e60fd7c68a281680e5f05014d5933 /drivers/net/tg3.c
parentaaf84465fc994e9a840a8c0c6fa842b54cdb3426 (diff)
[TG3]: WoL fixes.
Change TG3_FLAG_SERDES_WOL_CAP to TG3_FLAG_WOL_CAP to make it easier to manage WoL. This flag is now used consistently during ethtool WoL setup and power setting changes. Signed-off-by: Gary Zambrano <zambrano@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c25
1 files changed, 15 insertions, 10 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 00027a14eaa1..e829262ded43 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1300,9 +1300,11 @@ static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1300 msleep(1); 1300 msleep(1);
1301 } 1301 }
1302 } 1302 }
1303 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE | 1303 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
1304 WOL_DRV_STATE_SHUTDOWN | 1304 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1305 WOL_DRV_WOL | WOL_SET_MAGIC_PKT); 1305 WOL_DRV_STATE_SHUTDOWN |
1306 WOL_DRV_WOL |
1307 WOL_SET_MAGIC_PKT);
1306 1308
1307 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps); 1309 pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1308 1310
@@ -8034,7 +8036,10 @@ static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8034{ 8036{
8035 struct tg3 *tp = netdev_priv(dev); 8037 struct tg3 *tp = netdev_priv(dev);
8036 8038
8037 wol->supported = WAKE_MAGIC; 8039 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
8040 wol->supported = WAKE_MAGIC;
8041 else
8042 wol->supported = 0;
8038 wol->wolopts = 0; 8043 wol->wolopts = 0;
8039 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) 8044 if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8040 wol->wolopts = WAKE_MAGIC; 8045 wol->wolopts = WAKE_MAGIC;
@@ -8048,8 +8053,7 @@ static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8048 if (wol->wolopts & ~WAKE_MAGIC) 8053 if (wol->wolopts & ~WAKE_MAGIC)
8049 return -EINVAL; 8054 return -EINVAL;
8050 if ((wol->wolopts & WAKE_MAGIC) && 8055 if ((wol->wolopts & WAKE_MAGIC) &&
8051 tp->tg3_flags2 & TG3_FLG2_ANY_SERDES && 8056 !(tp->tg3_flags & TG3_FLAG_WOL_CAP))
8052 !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8053 return -EINVAL; 8057 return -EINVAL;
8054 8058
8055 spin_lock_bh(&tp->lock); 8059 spin_lock_bh(&tp->lock);
@@ -10001,8 +10005,8 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10001 tp->phy_id = PHY_ID_INVALID; 10005 tp->phy_id = PHY_ID_INVALID;
10002 tp->led_ctrl = LED_CTRL_MODE_PHY_1; 10006 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10003 10007
10004 /* Assume an onboard device by default. */ 10008 /* Assume an onboard device and WOL capable by default. */
10005 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT; 10009 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
10006 10010
10007 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) { 10011 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10008 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) { 10012 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
@@ -10125,8 +10129,9 @@ static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
10125 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) 10129 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10126 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE; 10130 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10127 } 10131 }
10128 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL) 10132 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
10129 tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP; 10133 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
10134 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
10130 10135
10131 if (cfg2 & (1 << 17)) 10136 if (cfg2 & (1 << 17))
10132 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING; 10137 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;