aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/tg3.c
diff options
context:
space:
mode:
authorMatt Carlson <mcarlson@broadcom.com>2011-04-20 03:57:39 -0400
committerDavid S. Miller <davem@davemloft.net>2011-04-21 20:05:57 -0400
commitb0988c15c12c40b9680730f55a8351f30ec7a564 (patch)
treecb979884597f2577577c276bb95b0a43b86e65ba /drivers/net/tg3.c
parent34eea5ac214353ccd93ef7dd8dbd10aed87f5f46 (diff)
tg3: Move phy accessor functions higher
Phy accessor functions should live closer to where the base phy read / write routines are. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c136
1 files changed, 68 insertions, 68 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index e134e484aee3..ea41d76a70d3 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -881,6 +881,74 @@ static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
881 return ret; 881 return ret;
882} 882}
883 883
884static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
885{
886 int err;
887
888 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
889 if (err)
890 goto done;
891
892 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
893 if (err)
894 goto done;
895
896 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
897 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
898 if (err)
899 goto done;
900
901 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
902
903done:
904 return err;
905}
906
907static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
908{
909 int err;
910
911 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
912 if (err)
913 goto done;
914
915 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
916 if (err)
917 goto done;
918
919 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
920 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
921 if (err)
922 goto done;
923
924 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
925
926done:
927 return err;
928}
929
930static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
931{
932 int err;
933
934 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
935 if (!err)
936 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
937
938 return err;
939}
940
941static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
942{
943 int err;
944
945 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
946 if (!err)
947 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
948
949 return err;
950}
951
884static int tg3_bmcr_reset(struct tg3 *tp) 952static int tg3_bmcr_reset(struct tg3 *tp)
885{ 953{
886 u32 phy_control; 954 u32 phy_control;
@@ -1154,52 +1222,6 @@ static void tg3_mdio_fini(struct tg3 *tp)
1154 } 1222 }
1155} 1223}
1156 1224
1157static int tg3_phy_cl45_write(struct tg3 *tp, u32 devad, u32 addr, u32 val)
1158{
1159 int err;
1160
1161 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1162 if (err)
1163 goto done;
1164
1165 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1166 if (err)
1167 goto done;
1168
1169 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1170 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1171 if (err)
1172 goto done;
1173
1174 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, val);
1175
1176done:
1177 return err;
1178}
1179
1180static int tg3_phy_cl45_read(struct tg3 *tp, u32 devad, u32 addr, u32 *val)
1181{
1182 int err;
1183
1184 err = tg3_writephy(tp, MII_TG3_MMD_CTRL, devad);
1185 if (err)
1186 goto done;
1187
1188 err = tg3_writephy(tp, MII_TG3_MMD_ADDRESS, addr);
1189 if (err)
1190 goto done;
1191
1192 err = tg3_writephy(tp, MII_TG3_MMD_CTRL,
1193 MII_TG3_MMD_CTRL_DATA_NOINC | devad);
1194 if (err)
1195 goto done;
1196
1197 err = tg3_readphy(tp, MII_TG3_MMD_ADDRESS, val);
1198
1199done:
1200 return err;
1201}
1202
1203/* tp->lock is held. */ 1225/* tp->lock is held. */
1204static inline void tg3_generate_fw_event(struct tg3 *tp) 1226static inline void tg3_generate_fw_event(struct tg3 *tp)
1205{ 1227{
@@ -1576,28 +1598,6 @@ static void tg3_phy_fini(struct tg3 *tp)
1576 } 1598 }
1577} 1599}
1578 1600
1579static int tg3_phydsp_read(struct tg3 *tp, u32 reg, u32 *val)
1580{
1581 int err;
1582
1583 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1584 if (!err)
1585 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val);
1586
1587 return err;
1588}
1589
1590static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1591{
1592 int err;
1593
1594 err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1595 if (!err)
1596 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1597
1598 return err;
1599}
1600
1601static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable) 1601static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1602{ 1602{
1603 u32 phytest; 1603 u32 phytest;