diff options
author | Matt Carlson <mcarlson@broadcom.com> | 2011-07-20 06:20:50 -0400 |
---|---|---|
committer | David S. Miller <davem@davemloft.net> | 2011-07-21 15:36:15 -0400 |
commit | 9e975cc291d80d5e4562d6bed15ec171e896d69b (patch) | |
tree | 7f64a2805778a627559d5cbe7f58f12836aaac1e /drivers/net/tg3.c | |
parent | 7961689586d30a34c10b18ac95ba1cd72cefe725 (diff) |
tg3: Fix io failures after chip reset
Commit f2096f94b514d88593355995d5dd276961e88af1, entitled
"tg3: Add 5720 H2BMC support", needed to add code to preserve some bits
set by firmware. Unfortunately the new code causes throughput to stop
after a chip reset because it enables state machines before they are
ready. This patch undoes the problematic code. The bits will be
restored later in the init sequence.
Signed-off-by: Matt Carlson <mcarlson@broadcom.com>
Reviewed-by: Michael Chan <mchan@broadcom.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r-- | drivers/net/tg3.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c index a5ff82d3b750..5bf7671dc2b2 100644 --- a/drivers/net/tg3.c +++ b/drivers/net/tg3.c | |||
@@ -7412,16 +7412,11 @@ static int tg3_chip_reset(struct tg3 *tp) | |||
7412 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); | 7412 | tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl); |
7413 | } | 7413 | } |
7414 | 7414 | ||
7415 | if (tg3_flag(tp, ENABLE_APE)) | ||
7416 | tp->mac_mode = MAC_MODE_APE_TX_EN | | ||
7417 | MAC_MODE_APE_RX_EN | | ||
7418 | MAC_MODE_TDE_ENABLE; | ||
7419 | |||
7420 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { | 7415 | if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES) { |
7421 | tp->mac_mode |= MAC_MODE_PORT_MODE_TBI; | 7416 | tp->mac_mode = MAC_MODE_PORT_MODE_TBI; |
7422 | val = tp->mac_mode; | 7417 | val = tp->mac_mode; |
7423 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { | 7418 | } else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES) { |
7424 | tp->mac_mode |= MAC_MODE_PORT_MODE_GMII; | 7419 | tp->mac_mode = MAC_MODE_PORT_MODE_GMII; |
7425 | val = tp->mac_mode; | 7420 | val = tp->mac_mode; |
7426 | } else | 7421 | } else |
7427 | val = 0; | 7422 | val = 0; |
@@ -8559,12 +8554,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy) | |||
8559 | udelay(10); | 8554 | udelay(10); |
8560 | } | 8555 | } |
8561 | 8556 | ||
8562 | if (tg3_flag(tp, ENABLE_APE)) | ||
8563 | tp->mac_mode = MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | ||
8564 | else | ||
8565 | tp->mac_mode = 0; | ||
8566 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | | 8557 | tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE | |
8567 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE; | 8558 | MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | |
8559 | MAC_MODE_FHDE_ENABLE; | ||
8560 | if (tg3_flag(tp, ENABLE_APE)) | ||
8561 | tp->mac_mode |= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN; | ||
8568 | if (!tg3_flag(tp, 5705_PLUS) && | 8562 | if (!tg3_flag(tp, 5705_PLUS) && |
8569 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && | 8563 | !(tp->phy_flags & TG3_PHYFLG_PHY_SERDES) && |
8570 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) | 8564 | GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) |