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authorMichael Chan <mchan@broadcom.com>2007-02-21 02:25:40 -0500
committerDavid S. Miller <davem@sunset.davemloft.net>2007-02-26 14:42:47 -0500
commit7f62ad5d37f4e43c841e92c6f159c93dcf2d2cdd (patch)
treef8d0e5d2dcc5e7783ace1f966b9e008278357067 /drivers/net/tg3.c
parentad930650c0e694233971c56e8de8e78b896e2613 (diff)
[TG3]: TSO workaround fixes.
1. Add race condition check after netif_stop_queue(). tg3_tx() runs without netif_tx_lock and can race with tg3_start_xmit_dma_bug() -> tg3_tso_bug(). 2. Firmware TSO in 5703/5704/5705 also have the same TSO limitation, i.e. they cannot handle TSO headers bigger than 80 bytes. Rename TG3_FL2_HW_TSO_1_BUG to TG3_FL2_TSO_BUG and set this flag on these chips as well. 3. Update version to 3.74. Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c20
1 files changed, 11 insertions, 9 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index 81a1c2e1a3f5..26c6ac48288c 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -64,8 +64,8 @@
64 64
65#define DRV_MODULE_NAME "tg3" 65#define DRV_MODULE_NAME "tg3"
66#define PFX DRV_MODULE_NAME ": " 66#define PFX DRV_MODULE_NAME ": "
67#define DRV_MODULE_VERSION "3.73" 67#define DRV_MODULE_VERSION "3.74"
68#define DRV_MODULE_RELDATE "February 12, 2007" 68#define DRV_MODULE_RELDATE "February 20, 2007"
69 69
70#define TG3_DEF_MAC_MODE 0 70#define TG3_DEF_MAC_MODE 0
71#define TG3_DEF_RX_MODE 0 71#define TG3_DEF_RX_MODE 0
@@ -3993,7 +3993,10 @@ static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3993 /* Estimate the number of fragments in the worst case */ 3993 /* Estimate the number of fragments in the worst case */
3994 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) { 3994 if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3995 netif_stop_queue(tp->dev); 3995 netif_stop_queue(tp->dev);
3996 return NETDEV_TX_BUSY; 3996 if (tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))
3997 return NETDEV_TX_BUSY;
3998
3999 netif_wake_queue(tp->dev);
3997 } 4000 }
3998 4001
3999 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO); 4002 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
@@ -4061,7 +4064,7 @@ static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4061 4064
4062 hdr_len = ip_tcp_len + tcp_opt_len; 4065 hdr_len = ip_tcp_len + tcp_opt_len;
4063 if (unlikely((ETH_HLEN + hdr_len) > 80) && 4066 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4064 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG)) 4067 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
4065 return (tg3_tso_bug(tp, skb)); 4068 return (tg3_tso_bug(tp, skb));
4066 4069
4067 base_flags |= (TXD_FLAG_CPU_PRE_DMA | 4070 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
@@ -8137,7 +8140,7 @@ static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *e
8137 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) || 8140 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8138 (ering->tx_pending > TG3_TX_RING_SIZE - 1) || 8141 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8139 (ering->tx_pending <= MAX_SKB_FRAGS) || 8142 (ering->tx_pending <= MAX_SKB_FRAGS) ||
8140 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) && 8143 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
8141 (ering->tx_pending <= (MAX_SKB_FRAGS * 3)))) 8144 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8142 return -EINVAL; 8145 return -EINVAL;
8143 8146
@@ -10557,12 +10560,11 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
10557 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2; 10560 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10558 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI; 10561 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10559 } else { 10562 } else {
10560 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | 10563 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
10561 TG3_FLG2_HW_TSO_1_BUG;
10562 if (GET_ASIC_REV(tp->pci_chip_rev_id) == 10564 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10563 ASIC_REV_5750 && 10565 ASIC_REV_5750 &&
10564 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2) 10566 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10565 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG; 10567 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
10566 } 10568 }
10567 } 10569 }
10568 10570
@@ -11867,7 +11869,7 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
11867 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) { 11869 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11868 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE; 11870 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11869 } else { 11871 } else {
11870 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE; 11872 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG;
11871 } 11873 }
11872 11874
11873 /* TSO is on by default on chips that support hardware TSO. 11875 /* TSO is on by default on chips that support hardware TSO.