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authorMatt Carlson <mcarlson@broadcom.com>2008-06-09 18:41:12 -0400
committerDavid S. Miller <davem@davemloft.net>2008-06-09 18:41:12 -0400
commit5f0c4a3cb6fda7c505f8c916b54ea90205feed68 (patch)
tree2fc90e6ff08e84934e6e18d3055e145ff0d8d45b /drivers/net/tg3.c
parent0ba11fb307a4f18c11df6f5f255158ce055a2a16 (diff)
tg3: Fix 5761 WOL
On 5761 non-e devices, two problems prevent the administrator from overriding the WOL settings in the device's NVRAM. The first problem is that GPIO 0 and GPIO 2 have been swapped. This change prevented the administrator from turning on WOL when it is disabled in NVRAM. The fix is to add a new path for the 5761 that swaps the two GPIOs in the code as well. The second problem is that GPIO 1 could not be toggled by the driver because the GPIO is shared with the debug UART GPIO. This will prevent the administrator from being able to turn WOL off if it was enabled in NVRAM. The fix is to always disable the debug UART after a GRC reset. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/tg3.c')
-rw-r--r--drivers/net/tg3.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/net/tg3.c b/drivers/net/tg3.c
index c12931829439..f8ce87344b27 100644
--- a/drivers/net/tg3.c
+++ b/drivers/net/tg3.c
@@ -1295,6 +1295,21 @@ static void tg3_frob_aux_power(struct tg3 *tp)
1295 GRC_LCLCTRL_GPIO_OUTPUT0 | 1295 GRC_LCLCTRL_GPIO_OUTPUT0 |
1296 GRC_LCLCTRL_GPIO_OUTPUT1), 1296 GRC_LCLCTRL_GPIO_OUTPUT1),
1297 100); 1297 100);
1298 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
1299 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
1300 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
1301 GRC_LCLCTRL_GPIO_OE1 |
1302 GRC_LCLCTRL_GPIO_OE2 |
1303 GRC_LCLCTRL_GPIO_OUTPUT0 |
1304 GRC_LCLCTRL_GPIO_OUTPUT1 |
1305 tp->grc_local_ctrl;
1306 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1307
1308 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
1309 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1310
1311 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
1312 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
1298 } else { 1313 } else {
1299 u32 no_gpio2; 1314 u32 no_gpio2;
1300 u32 grc_local_ctrl = 0; 1315 u32 grc_local_ctrl = 0;
@@ -11767,6 +11782,15 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
11767 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) 11782 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11768 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL; 11783 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11769 11784
11785 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761) {
11786 /* Turn off the debug UART. */
11787 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
11788 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
11789 /* Keep VMain power. */
11790 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
11791 GRC_LCLCTRL_GPIO_OUTPUT0;
11792 }
11793
11770 /* Force the chip into D0. */ 11794 /* Force the chip into D0. */
11771 err = tg3_set_power_state(tp, PCI_D0); 11795 err = tg3_set_power_state(tp, PCI_D0);
11772 if (err) { 11796 if (err) {