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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 18:20:36 -0400
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /drivers/net/sungem.c
Linux-2.6.12-rc2v2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'drivers/net/sungem.c')
-rw-r--r--drivers/net/sungem.c3204
1 files changed, 3204 insertions, 0 deletions
diff --git a/drivers/net/sungem.c b/drivers/net/sungem.c
new file mode 100644
index 000000000000..5cd50fd53c12
--- /dev/null
+++ b/drivers/net/sungem.c
@@ -0,0 +1,3204 @@
1/* $Id: sungem.c,v 1.44.2.22 2002/03/13 01:18:12 davem Exp $
2 * sungem.c: Sun GEM ethernet driver.
3 *
4 * Copyright (C) 2000, 2001, 2002, 2003 David S. Miller (davem@redhat.com)
5 *
6 * Support for Apple GMAC and assorted PHYs, WOL, Power Management
7 * (C) 2001,2002,2003 Benjamin Herrenscmidt (benh@kernel.crashing.org)
8 * (C) 2004,2005 Benjamin Herrenscmidt, IBM Corp.
9 *
10 * NAPI and NETPOLL support
11 * (C) 2004 by Eric Lemoine (eric.lemoine@gmail.com)
12 *
13 * TODO:
14 * - Now that the driver was significantly simplified, I need to rework
15 * the locking. I'm sure we don't need _2_ spinlocks, and we probably
16 * can avoid taking most of them for so long period of time (and schedule
17 * instead). The main issues at this point are caused by the netdev layer
18 * though:
19 *
20 * gem_change_mtu() and gem_set_multicast() are called with a read_lock()
21 * help by net/core/dev.c, thus they can't schedule. That means they can't
22 * call netif_poll_disable() neither, thus force gem_poll() to keep a spinlock
23 * where it could have been dropped. change_mtu especially would love also to
24 * be able to msleep instead of horrid locked delays when resetting the HW,
25 * but that read_lock() makes it impossible, unless I defer it's action to
26 * the reset task, which means it'll be asynchronous (won't take effect until
27 * the system schedules a bit).
28 *
29 * Also, it would probably be possible to also remove most of the long-life
30 * locking in open/resume code path (gem_reinit_chip) by beeing more careful
31 * about when we can start taking interrupts or get xmit() called...
32 */
33
34#include <linux/module.h>
35#include <linux/kernel.h>
36#include <linux/types.h>
37#include <linux/fcntl.h>
38#include <linux/interrupt.h>
39#include <linux/ioport.h>
40#include <linux/in.h>
41#include <linux/slab.h>
42#include <linux/string.h>
43#include <linux/delay.h>
44#include <linux/init.h>
45#include <linux/errno.h>
46#include <linux/pci.h>
47#include <linux/netdevice.h>
48#include <linux/etherdevice.h>
49#include <linux/skbuff.h>
50#include <linux/mii.h>
51#include <linux/ethtool.h>
52#include <linux/crc32.h>
53#include <linux/random.h>
54#include <linux/workqueue.h>
55#include <linux/if_vlan.h>
56#include <linux/bitops.h>
57
58#include <asm/system.h>
59#include <asm/io.h>
60#include <asm/byteorder.h>
61#include <asm/uaccess.h>
62#include <asm/irq.h>
63
64#ifdef __sparc__
65#include <asm/idprom.h>
66#include <asm/openprom.h>
67#include <asm/oplib.h>
68#include <asm/pbm.h>
69#endif
70
71#ifdef CONFIG_PPC_PMAC
72#include <asm/pci-bridge.h>
73#include <asm/prom.h>
74#include <asm/machdep.h>
75#include <asm/pmac_feature.h>
76#endif
77
78#include "sungem_phy.h"
79#include "sungem.h"
80
81/* Stripping FCS is causing problems, disabled for now */
82#undef STRIP_FCS
83
84#define DEFAULT_MSG (NETIF_MSG_DRV | \
85 NETIF_MSG_PROBE | \
86 NETIF_MSG_LINK)
87
88#define ADVERTISE_MASK (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full | \
89 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full | \
90 SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)
91
92#define DRV_NAME "sungem"
93#define DRV_VERSION "0.98"
94#define DRV_RELDATE "8/24/03"
95#define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
96
97static char version[] __devinitdata =
98 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
99
100MODULE_AUTHOR(DRV_AUTHOR);
101MODULE_DESCRIPTION("Sun GEM Gbit ethernet driver");
102MODULE_LICENSE("GPL");
103
104#define GEM_MODULE_NAME "gem"
105#define PFX GEM_MODULE_NAME ": "
106
107static struct pci_device_id gem_pci_tbl[] = {
108 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_GEM,
109 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
110
111 /* These models only differ from the original GEM in
112 * that their tx/rx fifos are of a different size and
113 * they only support 10/100 speeds. -DaveM
114 *
115 * Apple's GMAC does support gigabit on machines with
116 * the BCM54xx PHYs. -BenH
117 */
118 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_RIO_GEM,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
120 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
122 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMACP,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
124 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_GMAC2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
126 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_GMAC,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
128 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_SUNGEM,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
130 {0, }
131};
132
133MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
134
135static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
136{
137 u32 cmd;
138 int limit = 10000;
139
140 cmd = (1 << 30);
141 cmd |= (2 << 28);
142 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
143 cmd |= (reg << 18) & MIF_FRAME_REGAD;
144 cmd |= (MIF_FRAME_TAMSB);
145 writel(cmd, gp->regs + MIF_FRAME);
146
147 while (limit--) {
148 cmd = readl(gp->regs + MIF_FRAME);
149 if (cmd & MIF_FRAME_TALSB)
150 break;
151
152 udelay(10);
153 }
154
155 if (!limit)
156 cmd = 0xffff;
157
158 return cmd & MIF_FRAME_DATA;
159}
160
161static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
162{
163 struct gem *gp = dev->priv;
164 return __phy_read(gp, mii_id, reg);
165}
166
167static inline u16 phy_read(struct gem *gp, int reg)
168{
169 return __phy_read(gp, gp->mii_phy_addr, reg);
170}
171
172static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
173{
174 u32 cmd;
175 int limit = 10000;
176
177 cmd = (1 << 30);
178 cmd |= (1 << 28);
179 cmd |= (phy_addr << 23) & MIF_FRAME_PHYAD;
180 cmd |= (reg << 18) & MIF_FRAME_REGAD;
181 cmd |= (MIF_FRAME_TAMSB);
182 cmd |= (val & MIF_FRAME_DATA);
183 writel(cmd, gp->regs + MIF_FRAME);
184
185 while (limit--) {
186 cmd = readl(gp->regs + MIF_FRAME);
187 if (cmd & MIF_FRAME_TALSB)
188 break;
189
190 udelay(10);
191 }
192}
193
194static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
195{
196 struct gem *gp = dev->priv;
197 __phy_write(gp, mii_id, reg, val & 0xffff);
198}
199
200static inline void phy_write(struct gem *gp, int reg, u16 val)
201{
202 __phy_write(gp, gp->mii_phy_addr, reg, val);
203}
204
205static inline void gem_enable_ints(struct gem *gp)
206{
207 /* Enable all interrupts but TXDONE */
208 writel(GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
209}
210
211static inline void gem_disable_ints(struct gem *gp)
212{
213 /* Disable all interrupts, including TXDONE */
214 writel(GREG_STAT_NAPI | GREG_STAT_TXDONE, gp->regs + GREG_IMASK);
215}
216
217static void gem_get_cell(struct gem *gp)
218{
219 BUG_ON(gp->cell_enabled < 0);
220 gp->cell_enabled++;
221#ifdef CONFIG_PPC_PMAC
222 if (gp->cell_enabled == 1) {
223 mb();
224 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 1);
225 udelay(10);
226 }
227#endif /* CONFIG_PPC_PMAC */
228}
229
230/* Turn off the chip's clock */
231static void gem_put_cell(struct gem *gp)
232{
233 BUG_ON(gp->cell_enabled <= 0);
234 gp->cell_enabled--;
235#ifdef CONFIG_PPC_PMAC
236 if (gp->cell_enabled == 0) {
237 mb();
238 pmac_call_feature(PMAC_FTR_GMAC_ENABLE, gp->of_node, 0, 0);
239 udelay(10);
240 }
241#endif /* CONFIG_PPC_PMAC */
242}
243
244static void gem_handle_mif_event(struct gem *gp, u32 reg_val, u32 changed_bits)
245{
246 if (netif_msg_intr(gp))
247 printk(KERN_DEBUG "%s: mif interrupt\n", gp->dev->name);
248}
249
250static int gem_pcs_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
251{
252 u32 pcs_istat = readl(gp->regs + PCS_ISTAT);
253 u32 pcs_miistat;
254
255 if (netif_msg_intr(gp))
256 printk(KERN_DEBUG "%s: pcs interrupt, pcs_istat: 0x%x\n",
257 gp->dev->name, pcs_istat);
258
259 if (!(pcs_istat & PCS_ISTAT_LSC)) {
260 printk(KERN_ERR "%s: PCS irq but no link status change???\n",
261 dev->name);
262 return 0;
263 }
264
265 /* The link status bit latches on zero, so you must
266 * read it twice in such a case to see a transition
267 * to the link being up.
268 */
269 pcs_miistat = readl(gp->regs + PCS_MIISTAT);
270 if (!(pcs_miistat & PCS_MIISTAT_LS))
271 pcs_miistat |=
272 (readl(gp->regs + PCS_MIISTAT) &
273 PCS_MIISTAT_LS);
274
275 if (pcs_miistat & PCS_MIISTAT_ANC) {
276 /* The remote-fault indication is only valid
277 * when autoneg has completed.
278 */
279 if (pcs_miistat & PCS_MIISTAT_RF)
280 printk(KERN_INFO "%s: PCS AutoNEG complete, "
281 "RemoteFault\n", dev->name);
282 else
283 printk(KERN_INFO "%s: PCS AutoNEG complete.\n",
284 dev->name);
285 }
286
287 if (pcs_miistat & PCS_MIISTAT_LS) {
288 printk(KERN_INFO "%s: PCS link is now up.\n",
289 dev->name);
290 netif_carrier_on(gp->dev);
291 } else {
292 printk(KERN_INFO "%s: PCS link is now down.\n",
293 dev->name);
294 netif_carrier_off(gp->dev);
295 /* If this happens and the link timer is not running,
296 * reset so we re-negotiate.
297 */
298 if (!timer_pending(&gp->link_timer))
299 return 1;
300 }
301
302 return 0;
303}
304
305static int gem_txmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
306{
307 u32 txmac_stat = readl(gp->regs + MAC_TXSTAT);
308
309 if (netif_msg_intr(gp))
310 printk(KERN_DEBUG "%s: txmac interrupt, txmac_stat: 0x%x\n",
311 gp->dev->name, txmac_stat);
312
313 /* Defer timer expiration is quite normal,
314 * don't even log the event.
315 */
316 if ((txmac_stat & MAC_TXSTAT_DTE) &&
317 !(txmac_stat & ~MAC_TXSTAT_DTE))
318 return 0;
319
320 if (txmac_stat & MAC_TXSTAT_URUN) {
321 printk(KERN_ERR "%s: TX MAC xmit underrun.\n",
322 dev->name);
323 gp->net_stats.tx_fifo_errors++;
324 }
325
326 if (txmac_stat & MAC_TXSTAT_MPE) {
327 printk(KERN_ERR "%s: TX MAC max packet size error.\n",
328 dev->name);
329 gp->net_stats.tx_errors++;
330 }
331
332 /* The rest are all cases of one of the 16-bit TX
333 * counters expiring.
334 */
335 if (txmac_stat & MAC_TXSTAT_NCE)
336 gp->net_stats.collisions += 0x10000;
337
338 if (txmac_stat & MAC_TXSTAT_ECE) {
339 gp->net_stats.tx_aborted_errors += 0x10000;
340 gp->net_stats.collisions += 0x10000;
341 }
342
343 if (txmac_stat & MAC_TXSTAT_LCE) {
344 gp->net_stats.tx_aborted_errors += 0x10000;
345 gp->net_stats.collisions += 0x10000;
346 }
347
348 /* We do not keep track of MAC_TXSTAT_FCE and
349 * MAC_TXSTAT_PCE events.
350 */
351 return 0;
352}
353
354/* When we get a RX fifo overflow, the RX unit in GEM is probably hung
355 * so we do the following.
356 *
357 * If any part of the reset goes wrong, we return 1 and that causes the
358 * whole chip to be reset.
359 */
360static int gem_rxmac_reset(struct gem *gp)
361{
362 struct net_device *dev = gp->dev;
363 int limit, i;
364 u64 desc_dma;
365 u32 val;
366
367 /* First, reset & disable MAC RX. */
368 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
369 for (limit = 0; limit < 5000; limit++) {
370 if (!(readl(gp->regs + MAC_RXRST) & MAC_RXRST_CMD))
371 break;
372 udelay(10);
373 }
374 if (limit == 5000) {
375 printk(KERN_ERR "%s: RX MAC will not reset, resetting whole "
376 "chip.\n", dev->name);
377 return 1;
378 }
379
380 writel(gp->mac_rx_cfg & ~MAC_RXCFG_ENAB,
381 gp->regs + MAC_RXCFG);
382 for (limit = 0; limit < 5000; limit++) {
383 if (!(readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB))
384 break;
385 udelay(10);
386 }
387 if (limit == 5000) {
388 printk(KERN_ERR "%s: RX MAC will not disable, resetting whole "
389 "chip.\n", dev->name);
390 return 1;
391 }
392
393 /* Second, disable RX DMA. */
394 writel(0, gp->regs + RXDMA_CFG);
395 for (limit = 0; limit < 5000; limit++) {
396 if (!(readl(gp->regs + RXDMA_CFG) & RXDMA_CFG_ENABLE))
397 break;
398 udelay(10);
399 }
400 if (limit == 5000) {
401 printk(KERN_ERR "%s: RX DMA will not disable, resetting whole "
402 "chip.\n", dev->name);
403 return 1;
404 }
405
406 udelay(5000);
407
408 /* Execute RX reset command. */
409 writel(gp->swrst_base | GREG_SWRST_RXRST,
410 gp->regs + GREG_SWRST);
411 for (limit = 0; limit < 5000; limit++) {
412 if (!(readl(gp->regs + GREG_SWRST) & GREG_SWRST_RXRST))
413 break;
414 udelay(10);
415 }
416 if (limit == 5000) {
417 printk(KERN_ERR "%s: RX reset command will not execute, resetting "
418 "whole chip.\n", dev->name);
419 return 1;
420 }
421
422 /* Refresh the RX ring. */
423 for (i = 0; i < RX_RING_SIZE; i++) {
424 struct gem_rxd *rxd = &gp->init_block->rxd[i];
425
426 if (gp->rx_skbs[i] == NULL) {
427 printk(KERN_ERR "%s: Parts of RX ring empty, resetting "
428 "whole chip.\n", dev->name);
429 return 1;
430 }
431
432 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
433 }
434 gp->rx_new = gp->rx_old = 0;
435
436 /* Now we must reprogram the rest of RX unit. */
437 desc_dma = (u64) gp->gblock_dvma;
438 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
439 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
440 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
441 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
442 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
443 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
444 writel(val, gp->regs + RXDMA_CFG);
445 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
446 writel(((5 & RXDMA_BLANK_IPKTS) |
447 ((8 << 12) & RXDMA_BLANK_ITIME)),
448 gp->regs + RXDMA_BLANK);
449 else
450 writel(((5 & RXDMA_BLANK_IPKTS) |
451 ((4 << 12) & RXDMA_BLANK_ITIME)),
452 gp->regs + RXDMA_BLANK);
453 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
454 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
455 writel(val, gp->regs + RXDMA_PTHRESH);
456 val = readl(gp->regs + RXDMA_CFG);
457 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
458 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
459 val = readl(gp->regs + MAC_RXCFG);
460 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
461
462 return 0;
463}
464
465static int gem_rxmac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
466{
467 u32 rxmac_stat = readl(gp->regs + MAC_RXSTAT);
468 int ret = 0;
469
470 if (netif_msg_intr(gp))
471 printk(KERN_DEBUG "%s: rxmac interrupt, rxmac_stat: 0x%x\n",
472 gp->dev->name, rxmac_stat);
473
474 if (rxmac_stat & MAC_RXSTAT_OFLW) {
475 u32 smac = readl(gp->regs + MAC_SMACHINE);
476
477 printk(KERN_ERR "%s: RX MAC fifo overflow smac[%08x].\n",
478 dev->name, smac);
479 gp->net_stats.rx_over_errors++;
480 gp->net_stats.rx_fifo_errors++;
481
482 ret = gem_rxmac_reset(gp);
483 }
484
485 if (rxmac_stat & MAC_RXSTAT_ACE)
486 gp->net_stats.rx_frame_errors += 0x10000;
487
488 if (rxmac_stat & MAC_RXSTAT_CCE)
489 gp->net_stats.rx_crc_errors += 0x10000;
490
491 if (rxmac_stat & MAC_RXSTAT_LCE)
492 gp->net_stats.rx_length_errors += 0x10000;
493
494 /* We do not track MAC_RXSTAT_FCE and MAC_RXSTAT_VCE
495 * events.
496 */
497 return ret;
498}
499
500static int gem_mac_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
501{
502 u32 mac_cstat = readl(gp->regs + MAC_CSTAT);
503
504 if (netif_msg_intr(gp))
505 printk(KERN_DEBUG "%s: mac interrupt, mac_cstat: 0x%x\n",
506 gp->dev->name, mac_cstat);
507
508 /* This interrupt is just for pause frame and pause
509 * tracking. It is useful for diagnostics and debug
510 * but probably by default we will mask these events.
511 */
512 if (mac_cstat & MAC_CSTAT_PS)
513 gp->pause_entered++;
514
515 if (mac_cstat & MAC_CSTAT_PRCV)
516 gp->pause_last_time_recvd = (mac_cstat >> 16);
517
518 return 0;
519}
520
521static int gem_mif_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
522{
523 u32 mif_status = readl(gp->regs + MIF_STATUS);
524 u32 reg_val, changed_bits;
525
526 reg_val = (mif_status & MIF_STATUS_DATA) >> 16;
527 changed_bits = (mif_status & MIF_STATUS_STAT);
528
529 gem_handle_mif_event(gp, reg_val, changed_bits);
530
531 return 0;
532}
533
534static int gem_pci_interrupt(struct net_device *dev, struct gem *gp, u32 gem_status)
535{
536 u32 pci_estat = readl(gp->regs + GREG_PCIESTAT);
537
538 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
539 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
540 printk(KERN_ERR "%s: PCI error [%04x] ",
541 dev->name, pci_estat);
542
543 if (pci_estat & GREG_PCIESTAT_BADACK)
544 printk("<No ACK64# during ABS64 cycle> ");
545 if (pci_estat & GREG_PCIESTAT_DTRTO)
546 printk("<Delayed transaction timeout> ");
547 if (pci_estat & GREG_PCIESTAT_OTHER)
548 printk("<other>");
549 printk("\n");
550 } else {
551 pci_estat |= GREG_PCIESTAT_OTHER;
552 printk(KERN_ERR "%s: PCI error\n", dev->name);
553 }
554
555 if (pci_estat & GREG_PCIESTAT_OTHER) {
556 u16 pci_cfg_stat;
557
558 /* Interrogate PCI config space for the
559 * true cause.
560 */
561 pci_read_config_word(gp->pdev, PCI_STATUS,
562 &pci_cfg_stat);
563 printk(KERN_ERR "%s: Read PCI cfg space status [%04x]\n",
564 dev->name, pci_cfg_stat);
565 if (pci_cfg_stat & PCI_STATUS_PARITY)
566 printk(KERN_ERR "%s: PCI parity error detected.\n",
567 dev->name);
568 if (pci_cfg_stat & PCI_STATUS_SIG_TARGET_ABORT)
569 printk(KERN_ERR "%s: PCI target abort.\n",
570 dev->name);
571 if (pci_cfg_stat & PCI_STATUS_REC_TARGET_ABORT)
572 printk(KERN_ERR "%s: PCI master acks target abort.\n",
573 dev->name);
574 if (pci_cfg_stat & PCI_STATUS_REC_MASTER_ABORT)
575 printk(KERN_ERR "%s: PCI master abort.\n",
576 dev->name);
577 if (pci_cfg_stat & PCI_STATUS_SIG_SYSTEM_ERROR)
578 printk(KERN_ERR "%s: PCI system error SERR#.\n",
579 dev->name);
580 if (pci_cfg_stat & PCI_STATUS_DETECTED_PARITY)
581 printk(KERN_ERR "%s: PCI parity error.\n",
582 dev->name);
583
584 /* Write the error bits back to clear them. */
585 pci_cfg_stat &= (PCI_STATUS_PARITY |
586 PCI_STATUS_SIG_TARGET_ABORT |
587 PCI_STATUS_REC_TARGET_ABORT |
588 PCI_STATUS_REC_MASTER_ABORT |
589 PCI_STATUS_SIG_SYSTEM_ERROR |
590 PCI_STATUS_DETECTED_PARITY);
591 pci_write_config_word(gp->pdev,
592 PCI_STATUS, pci_cfg_stat);
593 }
594
595 /* For all PCI errors, we should reset the chip. */
596 return 1;
597}
598
599/* All non-normal interrupt conditions get serviced here.
600 * Returns non-zero if we should just exit the interrupt
601 * handler right now (ie. if we reset the card which invalidates
602 * all of the other original irq status bits).
603 */
604static int gem_abnormal_irq(struct net_device *dev, struct gem *gp, u32 gem_status)
605{
606 if (gem_status & GREG_STAT_RXNOBUF) {
607 /* Frame arrived, no free RX buffers available. */
608 if (netif_msg_rx_err(gp))
609 printk(KERN_DEBUG "%s: no buffer for rx frame\n",
610 gp->dev->name);
611 gp->net_stats.rx_dropped++;
612 }
613
614 if (gem_status & GREG_STAT_RXTAGERR) {
615 /* corrupt RX tag framing */
616 if (netif_msg_rx_err(gp))
617 printk(KERN_DEBUG "%s: corrupt rx tag framing\n",
618 gp->dev->name);
619 gp->net_stats.rx_errors++;
620
621 goto do_reset;
622 }
623
624 if (gem_status & GREG_STAT_PCS) {
625 if (gem_pcs_interrupt(dev, gp, gem_status))
626 goto do_reset;
627 }
628
629 if (gem_status & GREG_STAT_TXMAC) {
630 if (gem_txmac_interrupt(dev, gp, gem_status))
631 goto do_reset;
632 }
633
634 if (gem_status & GREG_STAT_RXMAC) {
635 if (gem_rxmac_interrupt(dev, gp, gem_status))
636 goto do_reset;
637 }
638
639 if (gem_status & GREG_STAT_MAC) {
640 if (gem_mac_interrupt(dev, gp, gem_status))
641 goto do_reset;
642 }
643
644 if (gem_status & GREG_STAT_MIF) {
645 if (gem_mif_interrupt(dev, gp, gem_status))
646 goto do_reset;
647 }
648
649 if (gem_status & GREG_STAT_PCIERR) {
650 if (gem_pci_interrupt(dev, gp, gem_status))
651 goto do_reset;
652 }
653
654 return 0;
655
656do_reset:
657 gp->reset_task_pending = 1;
658 schedule_work(&gp->reset_task);
659
660 return 1;
661}
662
663static __inline__ void gem_tx(struct net_device *dev, struct gem *gp, u32 gem_status)
664{
665 int entry, limit;
666
667 if (netif_msg_intr(gp))
668 printk(KERN_DEBUG "%s: tx interrupt, gem_status: 0x%x\n",
669 gp->dev->name, gem_status);
670
671 entry = gp->tx_old;
672 limit = ((gem_status & GREG_STAT_TXNR) >> GREG_STAT_TXNR_SHIFT);
673 while (entry != limit) {
674 struct sk_buff *skb;
675 struct gem_txd *txd;
676 dma_addr_t dma_addr;
677 u32 dma_len;
678 int frag;
679
680 if (netif_msg_tx_done(gp))
681 printk(KERN_DEBUG "%s: tx done, slot %d\n",
682 gp->dev->name, entry);
683 skb = gp->tx_skbs[entry];
684 if (skb_shinfo(skb)->nr_frags) {
685 int last = entry + skb_shinfo(skb)->nr_frags;
686 int walk = entry;
687 int incomplete = 0;
688
689 last &= (TX_RING_SIZE - 1);
690 for (;;) {
691 walk = NEXT_TX(walk);
692 if (walk == limit)
693 incomplete = 1;
694 if (walk == last)
695 break;
696 }
697 if (incomplete)
698 break;
699 }
700 gp->tx_skbs[entry] = NULL;
701 gp->net_stats.tx_bytes += skb->len;
702
703 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
704 txd = &gp->init_block->txd[entry];
705
706 dma_addr = le64_to_cpu(txd->buffer);
707 dma_len = le64_to_cpu(txd->control_word) & TXDCTRL_BUFSZ;
708
709 pci_unmap_page(gp->pdev, dma_addr, dma_len, PCI_DMA_TODEVICE);
710 entry = NEXT_TX(entry);
711 }
712
713 gp->net_stats.tx_packets++;
714 dev_kfree_skb_irq(skb);
715 }
716 gp->tx_old = entry;
717
718 if (netif_queue_stopped(dev) &&
719 TX_BUFFS_AVAIL(gp) > (MAX_SKB_FRAGS + 1))
720 netif_wake_queue(dev);
721}
722
723static __inline__ void gem_post_rxds(struct gem *gp, int limit)
724{
725 int cluster_start, curr, count, kick;
726
727 cluster_start = curr = (gp->rx_new & ~(4 - 1));
728 count = 0;
729 kick = -1;
730 wmb();
731 while (curr != limit) {
732 curr = NEXT_RX(curr);
733 if (++count == 4) {
734 struct gem_rxd *rxd =
735 &gp->init_block->rxd[cluster_start];
736 for (;;) {
737 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
738 rxd++;
739 cluster_start = NEXT_RX(cluster_start);
740 if (cluster_start == curr)
741 break;
742 }
743 kick = curr;
744 count = 0;
745 }
746 }
747 if (kick >= 0) {
748 mb();
749 writel(kick, gp->regs + RXDMA_KICK);
750 }
751}
752
753static int gem_rx(struct gem *gp, int work_to_do)
754{
755 int entry, drops, work_done = 0;
756 u32 done;
757
758 if (netif_msg_rx_status(gp))
759 printk(KERN_DEBUG "%s: rx interrupt, done: %d, rx_new: %d\n",
760 gp->dev->name, readl(gp->regs + RXDMA_DONE), gp->rx_new);
761
762 entry = gp->rx_new;
763 drops = 0;
764 done = readl(gp->regs + RXDMA_DONE);
765 for (;;) {
766 struct gem_rxd *rxd = &gp->init_block->rxd[entry];
767 struct sk_buff *skb;
768 u64 status = cpu_to_le64(rxd->status_word);
769 dma_addr_t dma_addr;
770 int len;
771
772 if ((status & RXDCTRL_OWN) != 0)
773 break;
774
775 if (work_done >= RX_RING_SIZE || work_done >= work_to_do)
776 break;
777
778 /* When writing back RX descriptor, GEM writes status
779 * then buffer address, possibly in seperate transactions.
780 * If we don't wait for the chip to write both, we could
781 * post a new buffer to this descriptor then have GEM spam
782 * on the buffer address. We sync on the RX completion
783 * register to prevent this from happening.
784 */
785 if (entry == done) {
786 done = readl(gp->regs + RXDMA_DONE);
787 if (entry == done)
788 break;
789 }
790
791 /* We can now account for the work we're about to do */
792 work_done++;
793
794 skb = gp->rx_skbs[entry];
795
796 len = (status & RXDCTRL_BUFSZ) >> 16;
797 if ((len < ETH_ZLEN) || (status & RXDCTRL_BAD)) {
798 gp->net_stats.rx_errors++;
799 if (len < ETH_ZLEN)
800 gp->net_stats.rx_length_errors++;
801 if (len & RXDCTRL_BAD)
802 gp->net_stats.rx_crc_errors++;
803
804 /* We'll just return it to GEM. */
805 drop_it:
806 gp->net_stats.rx_dropped++;
807 goto next;
808 }
809
810 dma_addr = cpu_to_le64(rxd->buffer);
811 if (len > RX_COPY_THRESHOLD) {
812 struct sk_buff *new_skb;
813
814 new_skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
815 if (new_skb == NULL) {
816 drops++;
817 goto drop_it;
818 }
819 pci_unmap_page(gp->pdev, dma_addr,
820 RX_BUF_ALLOC_SIZE(gp),
821 PCI_DMA_FROMDEVICE);
822 gp->rx_skbs[entry] = new_skb;
823 new_skb->dev = gp->dev;
824 skb_put(new_skb, (gp->rx_buf_sz + RX_OFFSET));
825 rxd->buffer = cpu_to_le64(pci_map_page(gp->pdev,
826 virt_to_page(new_skb->data),
827 offset_in_page(new_skb->data),
828 RX_BUF_ALLOC_SIZE(gp),
829 PCI_DMA_FROMDEVICE));
830 skb_reserve(new_skb, RX_OFFSET);
831
832 /* Trim the original skb for the netif. */
833 skb_trim(skb, len);
834 } else {
835 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
836
837 if (copy_skb == NULL) {
838 drops++;
839 goto drop_it;
840 }
841
842 copy_skb->dev = gp->dev;
843 skb_reserve(copy_skb, 2);
844 skb_put(copy_skb, len);
845 pci_dma_sync_single_for_cpu(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
846 memcpy(copy_skb->data, skb->data, len);
847 pci_dma_sync_single_for_device(gp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
848
849 /* We'll reuse the original ring buffer. */
850 skb = copy_skb;
851 }
852
853 skb->csum = ntohs((status & RXDCTRL_TCPCSUM) ^ 0xffff);
854 skb->ip_summed = CHECKSUM_HW;
855 skb->protocol = eth_type_trans(skb, gp->dev);
856
857 netif_receive_skb(skb);
858
859 gp->net_stats.rx_packets++;
860 gp->net_stats.rx_bytes += len;
861 gp->dev->last_rx = jiffies;
862
863 next:
864 entry = NEXT_RX(entry);
865 }
866
867 gem_post_rxds(gp, entry);
868
869 gp->rx_new = entry;
870
871 if (drops)
872 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n",
873 gp->dev->name);
874
875 return work_done;
876}
877
878static int gem_poll(struct net_device *dev, int *budget)
879{
880 struct gem *gp = dev->priv;
881 unsigned long flags;
882
883 /*
884 * NAPI locking nightmare: See comment at head of driver
885 */
886 spin_lock_irqsave(&gp->lock, flags);
887
888 do {
889 int work_to_do, work_done;
890
891 /* Handle anomalies */
892 if (gp->status & GREG_STAT_ABNORMAL) {
893 if (gem_abnormal_irq(dev, gp, gp->status))
894 break;
895 }
896
897 /* Run TX completion thread */
898 spin_lock(&gp->tx_lock);
899 gem_tx(dev, gp, gp->status);
900 spin_unlock(&gp->tx_lock);
901
902 spin_unlock_irqrestore(&gp->lock, flags);
903
904 /* Run RX thread. We don't use any locking here,
905 * code willing to do bad things - like cleaning the
906 * rx ring - must call netif_poll_disable(), which
907 * schedule_timeout()'s if polling is already disabled.
908 */
909 work_to_do = min(*budget, dev->quota);
910
911 work_done = gem_rx(gp, work_to_do);
912
913 *budget -= work_done;
914 dev->quota -= work_done;
915
916 if (work_done >= work_to_do)
917 return 1;
918
919 spin_lock_irqsave(&gp->lock, flags);
920
921 gp->status = readl(gp->regs + GREG_STAT);
922 } while (gp->status & GREG_STAT_NAPI);
923
924 __netif_rx_complete(dev);
925 gem_enable_ints(gp);
926
927 spin_unlock_irqrestore(&gp->lock, flags);
928 return 0;
929}
930
931static irqreturn_t gem_interrupt(int irq, void *dev_id, struct pt_regs *regs)
932{
933 struct net_device *dev = dev_id;
934 struct gem *gp = dev->priv;
935 unsigned long flags;
936
937 /* Swallow interrupts when shutting the chip down, though
938 * that shouldn't happen, we should have done free_irq() at
939 * this point...
940 */
941 if (!gp->running)
942 return IRQ_HANDLED;
943
944 spin_lock_irqsave(&gp->lock, flags);
945
946 if (netif_rx_schedule_prep(dev)) {
947 u32 gem_status = readl(gp->regs + GREG_STAT);
948
949 if (gem_status == 0) {
950 spin_unlock_irqrestore(&gp->lock, flags);
951 return IRQ_NONE;
952 }
953 gp->status = gem_status;
954 gem_disable_ints(gp);
955 __netif_rx_schedule(dev);
956 }
957
958 spin_unlock_irqrestore(&gp->lock, flags);
959
960 /* If polling was disabled at the time we received that
961 * interrupt, we may return IRQ_HANDLED here while we
962 * should return IRQ_NONE. No big deal...
963 */
964 return IRQ_HANDLED;
965}
966
967#ifdef CONFIG_NET_POLL_CONTROLLER
968static void gem_poll_controller(struct net_device *dev)
969{
970 /* gem_interrupt is safe to reentrance so no need
971 * to disable_irq here.
972 */
973 gem_interrupt(dev->irq, dev, NULL);
974}
975#endif
976
977static void gem_tx_timeout(struct net_device *dev)
978{
979 struct gem *gp = dev->priv;
980
981 printk(KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
982 if (!gp->running) {
983 printk("%s: hrm.. hw not running !\n", dev->name);
984 return;
985 }
986 printk(KERN_ERR "%s: TX_STATE[%08x:%08x:%08x]\n",
987 dev->name,
988 readl(gp->regs + TXDMA_CFG),
989 readl(gp->regs + MAC_TXSTAT),
990 readl(gp->regs + MAC_TXCFG));
991 printk(KERN_ERR "%s: RX_STATE[%08x:%08x:%08x]\n",
992 dev->name,
993 readl(gp->regs + RXDMA_CFG),
994 readl(gp->regs + MAC_RXSTAT),
995 readl(gp->regs + MAC_RXCFG));
996
997 spin_lock_irq(&gp->lock);
998 spin_lock(&gp->tx_lock);
999
1000 gp->reset_task_pending = 1;
1001 schedule_work(&gp->reset_task);
1002
1003 spin_unlock(&gp->tx_lock);
1004 spin_unlock_irq(&gp->lock);
1005}
1006
1007static __inline__ int gem_intme(int entry)
1008{
1009 /* Algorithm: IRQ every 1/2 of descriptors. */
1010 if (!(entry & ((TX_RING_SIZE>>1)-1)))
1011 return 1;
1012
1013 return 0;
1014}
1015
1016static int gem_start_xmit(struct sk_buff *skb, struct net_device *dev)
1017{
1018 struct gem *gp = dev->priv;
1019 int entry;
1020 u64 ctrl;
1021 unsigned long flags;
1022
1023 ctrl = 0;
1024 if (skb->ip_summed == CHECKSUM_HW) {
1025 u64 csum_start_off, csum_stuff_off;
1026
1027 csum_start_off = (u64) (skb->h.raw - skb->data);
1028 csum_stuff_off = (u64) ((skb->h.raw + skb->csum) - skb->data);
1029
1030 ctrl = (TXDCTRL_CENAB |
1031 (csum_start_off << 15) |
1032 (csum_stuff_off << 21));
1033 }
1034
1035 local_irq_save(flags);
1036 if (!spin_trylock(&gp->tx_lock)) {
1037 /* Tell upper layer to requeue */
1038 local_irq_restore(flags);
1039 return NETDEV_TX_LOCKED;
1040 }
1041 /* We raced with gem_do_stop() */
1042 if (!gp->running) {
1043 spin_unlock_irqrestore(&gp->tx_lock, flags);
1044 return NETDEV_TX_BUSY;
1045 }
1046
1047 /* This is a hard error, log it. */
1048 if (TX_BUFFS_AVAIL(gp) <= (skb_shinfo(skb)->nr_frags + 1)) {
1049 netif_stop_queue(dev);
1050 spin_unlock_irqrestore(&gp->tx_lock, flags);
1051 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when queue awake!\n",
1052 dev->name);
1053 return NETDEV_TX_BUSY;
1054 }
1055
1056 entry = gp->tx_new;
1057 gp->tx_skbs[entry] = skb;
1058
1059 if (skb_shinfo(skb)->nr_frags == 0) {
1060 struct gem_txd *txd = &gp->init_block->txd[entry];
1061 dma_addr_t mapping;
1062 u32 len;
1063
1064 len = skb->len;
1065 mapping = pci_map_page(gp->pdev,
1066 virt_to_page(skb->data),
1067 offset_in_page(skb->data),
1068 len, PCI_DMA_TODEVICE);
1069 ctrl |= TXDCTRL_SOF | TXDCTRL_EOF | len;
1070 if (gem_intme(entry))
1071 ctrl |= TXDCTRL_INTME;
1072 txd->buffer = cpu_to_le64(mapping);
1073 wmb();
1074 txd->control_word = cpu_to_le64(ctrl);
1075 entry = NEXT_TX(entry);
1076 } else {
1077 struct gem_txd *txd;
1078 u32 first_len;
1079 u64 intme;
1080 dma_addr_t first_mapping;
1081 int frag, first_entry = entry;
1082
1083 intme = 0;
1084 if (gem_intme(entry))
1085 intme |= TXDCTRL_INTME;
1086
1087 /* We must give this initial chunk to the device last.
1088 * Otherwise we could race with the device.
1089 */
1090 first_len = skb_headlen(skb);
1091 first_mapping = pci_map_page(gp->pdev, virt_to_page(skb->data),
1092 offset_in_page(skb->data),
1093 first_len, PCI_DMA_TODEVICE);
1094 entry = NEXT_TX(entry);
1095
1096 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
1097 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
1098 u32 len;
1099 dma_addr_t mapping;
1100 u64 this_ctrl;
1101
1102 len = this_frag->size;
1103 mapping = pci_map_page(gp->pdev,
1104 this_frag->page,
1105 this_frag->page_offset,
1106 len, PCI_DMA_TODEVICE);
1107 this_ctrl = ctrl;
1108 if (frag == skb_shinfo(skb)->nr_frags - 1)
1109 this_ctrl |= TXDCTRL_EOF;
1110
1111 txd = &gp->init_block->txd[entry];
1112 txd->buffer = cpu_to_le64(mapping);
1113 wmb();
1114 txd->control_word = cpu_to_le64(this_ctrl | len);
1115
1116 if (gem_intme(entry))
1117 intme |= TXDCTRL_INTME;
1118
1119 entry = NEXT_TX(entry);
1120 }
1121 txd = &gp->init_block->txd[first_entry];
1122 txd->buffer = cpu_to_le64(first_mapping);
1123 wmb();
1124 txd->control_word =
1125 cpu_to_le64(ctrl | TXDCTRL_SOF | intme | first_len);
1126 }
1127
1128 gp->tx_new = entry;
1129 if (TX_BUFFS_AVAIL(gp) <= (MAX_SKB_FRAGS + 1))
1130 netif_stop_queue(dev);
1131
1132 if (netif_msg_tx_queued(gp))
1133 printk(KERN_DEBUG "%s: tx queued, slot %d, skblen %d\n",
1134 dev->name, entry, skb->len);
1135 mb();
1136 writel(gp->tx_new, gp->regs + TXDMA_KICK);
1137 spin_unlock_irqrestore(&gp->tx_lock, flags);
1138
1139 dev->trans_start = jiffies;
1140
1141 return NETDEV_TX_OK;
1142}
1143
1144#define STOP_TRIES 32
1145
1146/* Must be invoked under gp->lock and gp->tx_lock. */
1147static void gem_reset(struct gem *gp)
1148{
1149 int limit;
1150 u32 val;
1151
1152 /* Make sure we won't get any more interrupts */
1153 writel(0xffffffff, gp->regs + GREG_IMASK);
1154
1155 /* Reset the chip */
1156 writel(gp->swrst_base | GREG_SWRST_TXRST | GREG_SWRST_RXRST,
1157 gp->regs + GREG_SWRST);
1158
1159 limit = STOP_TRIES;
1160
1161 do {
1162 udelay(20);
1163 val = readl(gp->regs + GREG_SWRST);
1164 if (limit-- <= 0)
1165 break;
1166 } while (val & (GREG_SWRST_TXRST | GREG_SWRST_RXRST));
1167
1168 if (limit <= 0)
1169 printk(KERN_ERR "%s: SW reset is ghetto.\n", gp->dev->name);
1170}
1171
1172/* Must be invoked under gp->lock and gp->tx_lock. */
1173static void gem_start_dma(struct gem *gp)
1174{
1175 u32 val;
1176
1177 /* We are ready to rock, turn everything on. */
1178 val = readl(gp->regs + TXDMA_CFG);
1179 writel(val | TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1180 val = readl(gp->regs + RXDMA_CFG);
1181 writel(val | RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1182 val = readl(gp->regs + MAC_TXCFG);
1183 writel(val | MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1184 val = readl(gp->regs + MAC_RXCFG);
1185 writel(val | MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1186
1187 (void) readl(gp->regs + MAC_RXCFG);
1188 udelay(100);
1189
1190 gem_enable_ints(gp);
1191
1192 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1193}
1194
1195/* Must be invoked under gp->lock and gp->tx_lock. DMA won't be
1196 * actually stopped before about 4ms tho ...
1197 */
1198static void gem_stop_dma(struct gem *gp)
1199{
1200 u32 val;
1201
1202 /* We are done rocking, turn everything off. */
1203 val = readl(gp->regs + TXDMA_CFG);
1204 writel(val & ~TXDMA_CFG_ENABLE, gp->regs + TXDMA_CFG);
1205 val = readl(gp->regs + RXDMA_CFG);
1206 writel(val & ~RXDMA_CFG_ENABLE, gp->regs + RXDMA_CFG);
1207 val = readl(gp->regs + MAC_TXCFG);
1208 writel(val & ~MAC_TXCFG_ENAB, gp->regs + MAC_TXCFG);
1209 val = readl(gp->regs + MAC_RXCFG);
1210 writel(val & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
1211
1212 (void) readl(gp->regs + MAC_RXCFG);
1213
1214 /* Need to wait a bit ... done by the caller */
1215}
1216
1217
1218/* Must be invoked under gp->lock and gp->tx_lock. */
1219// XXX dbl check what that function should do when called on PCS PHY
1220static void gem_begin_auto_negotiation(struct gem *gp, struct ethtool_cmd *ep)
1221{
1222 u32 advertise, features;
1223 int autoneg;
1224 int speed;
1225 int duplex;
1226
1227 if (gp->phy_type != phy_mii_mdio0 &&
1228 gp->phy_type != phy_mii_mdio1)
1229 goto non_mii;
1230
1231 /* Setup advertise */
1232 if (found_mii_phy(gp))
1233 features = gp->phy_mii.def->features;
1234 else
1235 features = 0;
1236
1237 advertise = features & ADVERTISE_MASK;
1238 if (gp->phy_mii.advertising != 0)
1239 advertise &= gp->phy_mii.advertising;
1240
1241 autoneg = gp->want_autoneg;
1242 speed = gp->phy_mii.speed;
1243 duplex = gp->phy_mii.duplex;
1244
1245 /* Setup link parameters */
1246 if (!ep)
1247 goto start_aneg;
1248 if (ep->autoneg == AUTONEG_ENABLE) {
1249 advertise = ep->advertising;
1250 autoneg = 1;
1251 } else {
1252 autoneg = 0;
1253 speed = ep->speed;
1254 duplex = ep->duplex;
1255 }
1256
1257start_aneg:
1258 /* Sanitize settings based on PHY capabilities */
1259 if ((features & SUPPORTED_Autoneg) == 0)
1260 autoneg = 0;
1261 if (speed == SPEED_1000 &&
1262 !(features & (SUPPORTED_1000baseT_Half | SUPPORTED_1000baseT_Full)))
1263 speed = SPEED_100;
1264 if (speed == SPEED_100 &&
1265 !(features & (SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full)))
1266 speed = SPEED_10;
1267 if (duplex == DUPLEX_FULL &&
1268 !(features & (SUPPORTED_1000baseT_Full |
1269 SUPPORTED_100baseT_Full |
1270 SUPPORTED_10baseT_Full)))
1271 duplex = DUPLEX_HALF;
1272 if (speed == 0)
1273 speed = SPEED_10;
1274
1275 /* If we are asleep, we don't try to actually setup the PHY, we
1276 * just store the settings
1277 */
1278 if (gp->asleep) {
1279 gp->phy_mii.autoneg = gp->want_autoneg = autoneg;
1280 gp->phy_mii.speed = speed;
1281 gp->phy_mii.duplex = duplex;
1282 return;
1283 }
1284
1285 /* Configure PHY & start aneg */
1286 gp->want_autoneg = autoneg;
1287 if (autoneg) {
1288 if (found_mii_phy(gp))
1289 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, advertise);
1290 gp->lstate = link_aneg;
1291 } else {
1292 if (found_mii_phy(gp))
1293 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, speed, duplex);
1294 gp->lstate = link_force_ok;
1295 }
1296
1297non_mii:
1298 gp->timer_ticks = 0;
1299 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1300}
1301
1302/* A link-up condition has occurred, initialize and enable the
1303 * rest of the chip.
1304 *
1305 * Must be invoked under gp->lock and gp->tx_lock.
1306 */
1307static int gem_set_link_modes(struct gem *gp)
1308{
1309 u32 val;
1310 int full_duplex, speed, pause;
1311
1312 full_duplex = 0;
1313 speed = SPEED_10;
1314 pause = 0;
1315
1316 if (found_mii_phy(gp)) {
1317 if (gp->phy_mii.def->ops->read_link(&gp->phy_mii))
1318 return 1;
1319 full_duplex = (gp->phy_mii.duplex == DUPLEX_FULL);
1320 speed = gp->phy_mii.speed;
1321 pause = gp->phy_mii.pause;
1322 } else if (gp->phy_type == phy_serialink ||
1323 gp->phy_type == phy_serdes) {
1324 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1325
1326 if (pcs_lpa & PCS_MIIADV_FD)
1327 full_duplex = 1;
1328 speed = SPEED_1000;
1329 }
1330
1331 if (netif_msg_link(gp))
1332 printk(KERN_INFO "%s: Link is up at %d Mbps, %s-duplex.\n",
1333 gp->dev->name, speed, (full_duplex ? "full" : "half"));
1334
1335 if (!gp->running)
1336 return 0;
1337
1338 val = (MAC_TXCFG_EIPG0 | MAC_TXCFG_NGU);
1339 if (full_duplex) {
1340 val |= (MAC_TXCFG_ICS | MAC_TXCFG_ICOLL);
1341 } else {
1342 /* MAC_TXCFG_NBO must be zero. */
1343 }
1344 writel(val, gp->regs + MAC_TXCFG);
1345
1346 val = (MAC_XIFCFG_OE | MAC_XIFCFG_LLED);
1347 if (!full_duplex &&
1348 (gp->phy_type == phy_mii_mdio0 ||
1349 gp->phy_type == phy_mii_mdio1)) {
1350 val |= MAC_XIFCFG_DISE;
1351 } else if (full_duplex) {
1352 val |= MAC_XIFCFG_FLED;
1353 }
1354
1355 if (speed == SPEED_1000)
1356 val |= (MAC_XIFCFG_GMII);
1357
1358 writel(val, gp->regs + MAC_XIFCFG);
1359
1360 /* If gigabit and half-duplex, enable carrier extension
1361 * mode. Else, disable it.
1362 */
1363 if (speed == SPEED_1000 && !full_duplex) {
1364 val = readl(gp->regs + MAC_TXCFG);
1365 writel(val | MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1366
1367 val = readl(gp->regs + MAC_RXCFG);
1368 writel(val | MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1369 } else {
1370 val = readl(gp->regs + MAC_TXCFG);
1371 writel(val & ~MAC_TXCFG_TCE, gp->regs + MAC_TXCFG);
1372
1373 val = readl(gp->regs + MAC_RXCFG);
1374 writel(val & ~MAC_RXCFG_RCE, gp->regs + MAC_RXCFG);
1375 }
1376
1377 if (gp->phy_type == phy_serialink ||
1378 gp->phy_type == phy_serdes) {
1379 u32 pcs_lpa = readl(gp->regs + PCS_MIILP);
1380
1381 if (pcs_lpa & (PCS_MIIADV_SP | PCS_MIIADV_AP))
1382 pause = 1;
1383 }
1384
1385 if (netif_msg_link(gp)) {
1386 if (pause) {
1387 printk(KERN_INFO "%s: Pause is enabled "
1388 "(rxfifo: %d off: %d on: %d)\n",
1389 gp->dev->name,
1390 gp->rx_fifo_sz,
1391 gp->rx_pause_off,
1392 gp->rx_pause_on);
1393 } else {
1394 printk(KERN_INFO "%s: Pause is disabled\n",
1395 gp->dev->name);
1396 }
1397 }
1398
1399 if (!full_duplex)
1400 writel(512, gp->regs + MAC_STIME);
1401 else
1402 writel(64, gp->regs + MAC_STIME);
1403 val = readl(gp->regs + MAC_MCCFG);
1404 if (pause)
1405 val |= (MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1406 else
1407 val &= ~(MAC_MCCFG_SPE | MAC_MCCFG_RPE);
1408 writel(val, gp->regs + MAC_MCCFG);
1409
1410 gem_start_dma(gp);
1411
1412 return 0;
1413}
1414
1415/* Must be invoked under gp->lock and gp->tx_lock. */
1416static int gem_mdio_link_not_up(struct gem *gp)
1417{
1418 switch (gp->lstate) {
1419 case link_force_ret:
1420 if (netif_msg_link(gp))
1421 printk(KERN_INFO "%s: Autoneg failed again, keeping"
1422 " forced mode\n", gp->dev->name);
1423 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii,
1424 gp->last_forced_speed, DUPLEX_HALF);
1425 gp->timer_ticks = 5;
1426 gp->lstate = link_force_ok;
1427 return 0;
1428 case link_aneg:
1429 /* We try forced modes after a failed aneg only on PHYs that don't
1430 * have "magic_aneg" bit set, which means they internally do the
1431 * while forced-mode thingy. On these, we just restart aneg
1432 */
1433 if (gp->phy_mii.def->magic_aneg)
1434 return 1;
1435 if (netif_msg_link(gp))
1436 printk(KERN_INFO "%s: switching to forced 100bt\n",
1437 gp->dev->name);
1438 /* Try forced modes. */
1439 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_100,
1440 DUPLEX_HALF);
1441 gp->timer_ticks = 5;
1442 gp->lstate = link_force_try;
1443 return 0;
1444 case link_force_try:
1445 /* Downgrade from 100 to 10 Mbps if necessary.
1446 * If already at 10Mbps, warn user about the
1447 * situation every 10 ticks.
1448 */
1449 if (gp->phy_mii.speed == SPEED_100) {
1450 gp->phy_mii.def->ops->setup_forced(&gp->phy_mii, SPEED_10,
1451 DUPLEX_HALF);
1452 gp->timer_ticks = 5;
1453 if (netif_msg_link(gp))
1454 printk(KERN_INFO "%s: switching to forced 10bt\n",
1455 gp->dev->name);
1456 return 0;
1457 } else
1458 return 1;
1459 default:
1460 return 0;
1461 }
1462}
1463
1464static void gem_link_timer(unsigned long data)
1465{
1466 struct gem *gp = (struct gem *) data;
1467 int restart_aneg = 0;
1468
1469 if (gp->asleep)
1470 return;
1471
1472 spin_lock_irq(&gp->lock);
1473 spin_lock(&gp->tx_lock);
1474 gem_get_cell(gp);
1475
1476 /* If the reset task is still pending, we just
1477 * reschedule the link timer
1478 */
1479 if (gp->reset_task_pending)
1480 goto restart;
1481
1482 if (gp->phy_type == phy_serialink ||
1483 gp->phy_type == phy_serdes) {
1484 u32 val = readl(gp->regs + PCS_MIISTAT);
1485
1486 if (!(val & PCS_MIISTAT_LS))
1487 val = readl(gp->regs + PCS_MIISTAT);
1488
1489 if ((val & PCS_MIISTAT_LS) != 0) {
1490 gp->lstate = link_up;
1491 netif_carrier_on(gp->dev);
1492 (void)gem_set_link_modes(gp);
1493 }
1494 goto restart;
1495 }
1496 if (found_mii_phy(gp) && gp->phy_mii.def->ops->poll_link(&gp->phy_mii)) {
1497 /* Ok, here we got a link. If we had it due to a forced
1498 * fallback, and we were configured for autoneg, we do
1499 * retry a short autoneg pass. If you know your hub is
1500 * broken, use ethtool ;)
1501 */
1502 if (gp->lstate == link_force_try && gp->want_autoneg) {
1503 gp->lstate = link_force_ret;
1504 gp->last_forced_speed = gp->phy_mii.speed;
1505 gp->timer_ticks = 5;
1506 if (netif_msg_link(gp))
1507 printk(KERN_INFO "%s: Got link after fallback, retrying"
1508 " autoneg once...\n", gp->dev->name);
1509 gp->phy_mii.def->ops->setup_aneg(&gp->phy_mii, gp->phy_mii.advertising);
1510 } else if (gp->lstate != link_up) {
1511 gp->lstate = link_up;
1512 netif_carrier_on(gp->dev);
1513 if (gem_set_link_modes(gp))
1514 restart_aneg = 1;
1515 }
1516 } else {
1517 /* If the link was previously up, we restart the
1518 * whole process
1519 */
1520 if (gp->lstate == link_up) {
1521 gp->lstate = link_down;
1522 if (netif_msg_link(gp))
1523 printk(KERN_INFO "%s: Link down\n",
1524 gp->dev->name);
1525 netif_carrier_off(gp->dev);
1526 gp->reset_task_pending = 1;
1527 schedule_work(&gp->reset_task);
1528 restart_aneg = 1;
1529 } else if (++gp->timer_ticks > 10) {
1530 if (found_mii_phy(gp))
1531 restart_aneg = gem_mdio_link_not_up(gp);
1532 else
1533 restart_aneg = 1;
1534 }
1535 }
1536 if (restart_aneg) {
1537 gem_begin_auto_negotiation(gp, NULL);
1538 goto out_unlock;
1539 }
1540restart:
1541 mod_timer(&gp->link_timer, jiffies + ((12 * HZ) / 10));
1542out_unlock:
1543 gem_put_cell(gp);
1544 spin_unlock(&gp->tx_lock);
1545 spin_unlock_irq(&gp->lock);
1546}
1547
1548/* Must be invoked under gp->lock and gp->tx_lock. */
1549static void gem_clean_rings(struct gem *gp)
1550{
1551 struct gem_init_block *gb = gp->init_block;
1552 struct sk_buff *skb;
1553 int i;
1554 dma_addr_t dma_addr;
1555
1556 for (i = 0; i < RX_RING_SIZE; i++) {
1557 struct gem_rxd *rxd;
1558
1559 rxd = &gb->rxd[i];
1560 if (gp->rx_skbs[i] != NULL) {
1561 skb = gp->rx_skbs[i];
1562 dma_addr = le64_to_cpu(rxd->buffer);
1563 pci_unmap_page(gp->pdev, dma_addr,
1564 RX_BUF_ALLOC_SIZE(gp),
1565 PCI_DMA_FROMDEVICE);
1566 dev_kfree_skb_any(skb);
1567 gp->rx_skbs[i] = NULL;
1568 }
1569 rxd->status_word = 0;
1570 wmb();
1571 rxd->buffer = 0;
1572 }
1573
1574 for (i = 0; i < TX_RING_SIZE; i++) {
1575 if (gp->tx_skbs[i] != NULL) {
1576 struct gem_txd *txd;
1577 int frag;
1578
1579 skb = gp->tx_skbs[i];
1580 gp->tx_skbs[i] = NULL;
1581
1582 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1583 int ent = i & (TX_RING_SIZE - 1);
1584
1585 txd = &gb->txd[ent];
1586 dma_addr = le64_to_cpu(txd->buffer);
1587 pci_unmap_page(gp->pdev, dma_addr,
1588 le64_to_cpu(txd->control_word) &
1589 TXDCTRL_BUFSZ, PCI_DMA_TODEVICE);
1590
1591 if (frag != skb_shinfo(skb)->nr_frags)
1592 i++;
1593 }
1594 dev_kfree_skb_any(skb);
1595 }
1596 }
1597}
1598
1599/* Must be invoked under gp->lock and gp->tx_lock. */
1600static void gem_init_rings(struct gem *gp)
1601{
1602 struct gem_init_block *gb = gp->init_block;
1603 struct net_device *dev = gp->dev;
1604 int i;
1605 dma_addr_t dma_addr;
1606
1607 gp->rx_new = gp->rx_old = gp->tx_new = gp->tx_old = 0;
1608
1609 gem_clean_rings(gp);
1610
1611 gp->rx_buf_sz = max(dev->mtu + ETH_HLEN + VLAN_HLEN,
1612 (unsigned)VLAN_ETH_FRAME_LEN);
1613
1614 for (i = 0; i < RX_RING_SIZE; i++) {
1615 struct sk_buff *skb;
1616 struct gem_rxd *rxd = &gb->rxd[i];
1617
1618 skb = gem_alloc_skb(RX_BUF_ALLOC_SIZE(gp), GFP_ATOMIC);
1619 if (!skb) {
1620 rxd->buffer = 0;
1621 rxd->status_word = 0;
1622 continue;
1623 }
1624
1625 gp->rx_skbs[i] = skb;
1626 skb->dev = dev;
1627 skb_put(skb, (gp->rx_buf_sz + RX_OFFSET));
1628 dma_addr = pci_map_page(gp->pdev,
1629 virt_to_page(skb->data),
1630 offset_in_page(skb->data),
1631 RX_BUF_ALLOC_SIZE(gp),
1632 PCI_DMA_FROMDEVICE);
1633 rxd->buffer = cpu_to_le64(dma_addr);
1634 wmb();
1635 rxd->status_word = cpu_to_le64(RXDCTRL_FRESH(gp));
1636 skb_reserve(skb, RX_OFFSET);
1637 }
1638
1639 for (i = 0; i < TX_RING_SIZE; i++) {
1640 struct gem_txd *txd = &gb->txd[i];
1641
1642 txd->control_word = 0;
1643 wmb();
1644 txd->buffer = 0;
1645 }
1646 wmb();
1647}
1648
1649/* Init PHY interface and start link poll state machine */
1650static void gem_init_phy(struct gem *gp)
1651{
1652 u32 mifcfg;
1653
1654 /* Revert MIF CFG setting done on stop_phy */
1655 mifcfg = readl(gp->regs + MIF_CFG);
1656 mifcfg &= ~MIF_CFG_BBMODE;
1657 writel(mifcfg, gp->regs + MIF_CFG);
1658
1659 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE) {
1660 int i;
1661
1662 /* Those delay sucks, the HW seem to love them though, I'll
1663 * serisouly consider breaking some locks here to be able
1664 * to schedule instead
1665 */
1666 for (i = 0; i < 3; i++) {
1667#ifdef CONFIG_PPC_PMAC
1668 pmac_call_feature(PMAC_FTR_GMAC_PHY_RESET, gp->of_node, 0, 0);
1669 msleep(20);
1670#endif
1671 /* Some PHYs used by apple have problem getting back to us,
1672 * we do an additional reset here
1673 */
1674 phy_write(gp, MII_BMCR, BMCR_RESET);
1675 msleep(20);
1676 if (phy_read(gp, MII_BMCR) != 0xffff)
1677 break;
1678 if (i == 2)
1679 printk(KERN_WARNING "%s: GMAC PHY not responding !\n",
1680 gp->dev->name);
1681 }
1682 }
1683
1684 if (gp->pdev->vendor == PCI_VENDOR_ID_SUN &&
1685 gp->pdev->device == PCI_DEVICE_ID_SUN_GEM) {
1686 u32 val;
1687
1688 /* Init datapath mode register. */
1689 if (gp->phy_type == phy_mii_mdio0 ||
1690 gp->phy_type == phy_mii_mdio1) {
1691 val = PCS_DMODE_MGM;
1692 } else if (gp->phy_type == phy_serialink) {
1693 val = PCS_DMODE_SM | PCS_DMODE_GMOE;
1694 } else {
1695 val = PCS_DMODE_ESM;
1696 }
1697
1698 writel(val, gp->regs + PCS_DMODE);
1699 }
1700
1701 if (gp->phy_type == phy_mii_mdio0 ||
1702 gp->phy_type == phy_mii_mdio1) {
1703 // XXX check for errors
1704 mii_phy_probe(&gp->phy_mii, gp->mii_phy_addr);
1705
1706 /* Init PHY */
1707 if (gp->phy_mii.def && gp->phy_mii.def->ops->init)
1708 gp->phy_mii.def->ops->init(&gp->phy_mii);
1709 } else {
1710 u32 val;
1711 int limit;
1712
1713 /* Reset PCS unit. */
1714 val = readl(gp->regs + PCS_MIICTRL);
1715 val |= PCS_MIICTRL_RST;
1716 writeb(val, gp->regs + PCS_MIICTRL);
1717
1718 limit = 32;
1719 while (readl(gp->regs + PCS_MIICTRL) & PCS_MIICTRL_RST) {
1720 udelay(100);
1721 if (limit-- <= 0)
1722 break;
1723 }
1724 if (limit <= 0)
1725 printk(KERN_WARNING "%s: PCS reset bit would not clear.\n",
1726 gp->dev->name);
1727
1728 /* Make sure PCS is disabled while changing advertisement
1729 * configuration.
1730 */
1731 val = readl(gp->regs + PCS_CFG);
1732 val &= ~(PCS_CFG_ENABLE | PCS_CFG_TO);
1733 writel(val, gp->regs + PCS_CFG);
1734
1735 /* Advertise all capabilities except assymetric
1736 * pause.
1737 */
1738 val = readl(gp->regs + PCS_MIIADV);
1739 val |= (PCS_MIIADV_FD | PCS_MIIADV_HD |
1740 PCS_MIIADV_SP | PCS_MIIADV_AP);
1741 writel(val, gp->regs + PCS_MIIADV);
1742
1743 /* Enable and restart auto-negotiation, disable wrapback/loopback,
1744 * and re-enable PCS.
1745 */
1746 val = readl(gp->regs + PCS_MIICTRL);
1747 val |= (PCS_MIICTRL_RAN | PCS_MIICTRL_ANE);
1748 val &= ~PCS_MIICTRL_WB;
1749 writel(val, gp->regs + PCS_MIICTRL);
1750
1751 val = readl(gp->regs + PCS_CFG);
1752 val |= PCS_CFG_ENABLE;
1753 writel(val, gp->regs + PCS_CFG);
1754
1755 /* Make sure serialink loopback is off. The meaning
1756 * of this bit is logically inverted based upon whether
1757 * you are in Serialink or SERDES mode.
1758 */
1759 val = readl(gp->regs + PCS_SCTRL);
1760 if (gp->phy_type == phy_serialink)
1761 val &= ~PCS_SCTRL_LOOP;
1762 else
1763 val |= PCS_SCTRL_LOOP;
1764 writel(val, gp->regs + PCS_SCTRL);
1765 }
1766
1767 /* Default aneg parameters */
1768 gp->timer_ticks = 0;
1769 gp->lstate = link_down;
1770 netif_carrier_off(gp->dev);
1771
1772 /* Can I advertise gigabit here ? I'd need BCM PHY docs... */
1773 spin_lock_irq(&gp->lock);
1774 gem_begin_auto_negotiation(gp, NULL);
1775 spin_unlock_irq(&gp->lock);
1776}
1777
1778/* Must be invoked under gp->lock and gp->tx_lock. */
1779static void gem_init_dma(struct gem *gp)
1780{
1781 u64 desc_dma = (u64) gp->gblock_dvma;
1782 u32 val;
1783
1784 val = (TXDMA_CFG_BASE | (0x7ff << 10) | TXDMA_CFG_PMODE);
1785 writel(val, gp->regs + TXDMA_CFG);
1786
1787 writel(desc_dma >> 32, gp->regs + TXDMA_DBHI);
1788 writel(desc_dma & 0xffffffff, gp->regs + TXDMA_DBLOW);
1789 desc_dma += (INIT_BLOCK_TX_RING_SIZE * sizeof(struct gem_txd));
1790
1791 writel(0, gp->regs + TXDMA_KICK);
1792
1793 val = (RXDMA_CFG_BASE | (RX_OFFSET << 10) |
1794 ((14 / 2) << 13) | RXDMA_CFG_FTHRESH_128);
1795 writel(val, gp->regs + RXDMA_CFG);
1796
1797 writel(desc_dma >> 32, gp->regs + RXDMA_DBHI);
1798 writel(desc_dma & 0xffffffff, gp->regs + RXDMA_DBLOW);
1799
1800 writel(RX_RING_SIZE - 4, gp->regs + RXDMA_KICK);
1801
1802 val = (((gp->rx_pause_off / 64) << 0) & RXDMA_PTHRESH_OFF);
1803 val |= (((gp->rx_pause_on / 64) << 12) & RXDMA_PTHRESH_ON);
1804 writel(val, gp->regs + RXDMA_PTHRESH);
1805
1806 if (readl(gp->regs + GREG_BIFCFG) & GREG_BIFCFG_M66EN)
1807 writel(((5 & RXDMA_BLANK_IPKTS) |
1808 ((8 << 12) & RXDMA_BLANK_ITIME)),
1809 gp->regs + RXDMA_BLANK);
1810 else
1811 writel(((5 & RXDMA_BLANK_IPKTS) |
1812 ((4 << 12) & RXDMA_BLANK_ITIME)),
1813 gp->regs + RXDMA_BLANK);
1814}
1815
1816/* Must be invoked under gp->lock and gp->tx_lock. */
1817static u32 gem_setup_multicast(struct gem *gp)
1818{
1819 u32 rxcfg = 0;
1820 int i;
1821
1822 if ((gp->dev->flags & IFF_ALLMULTI) ||
1823 (gp->dev->mc_count > 256)) {
1824 for (i=0; i<16; i++)
1825 writel(0xffff, gp->regs + MAC_HASH0 + (i << 2));
1826 rxcfg |= MAC_RXCFG_HFE;
1827 } else if (gp->dev->flags & IFF_PROMISC) {
1828 rxcfg |= MAC_RXCFG_PROM;
1829 } else {
1830 u16 hash_table[16];
1831 u32 crc;
1832 struct dev_mc_list *dmi = gp->dev->mc_list;
1833 int i;
1834
1835 for (i = 0; i < 16; i++)
1836 hash_table[i] = 0;
1837
1838 for (i = 0; i < gp->dev->mc_count; i++) {
1839 char *addrs = dmi->dmi_addr;
1840
1841 dmi = dmi->next;
1842
1843 if (!(*addrs & 1))
1844 continue;
1845
1846 crc = ether_crc_le(6, addrs);
1847 crc >>= 24;
1848 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf));
1849 }
1850 for (i=0; i<16; i++)
1851 writel(hash_table[i], gp->regs + MAC_HASH0 + (i << 2));
1852 rxcfg |= MAC_RXCFG_HFE;
1853 }
1854
1855 return rxcfg;
1856}
1857
1858/* Must be invoked under gp->lock and gp->tx_lock. */
1859static void gem_init_mac(struct gem *gp)
1860{
1861 unsigned char *e = &gp->dev->dev_addr[0];
1862
1863 writel(0x1bf0, gp->regs + MAC_SNDPAUSE);
1864
1865 writel(0x00, gp->regs + MAC_IPG0);
1866 writel(0x08, gp->regs + MAC_IPG1);
1867 writel(0x04, gp->regs + MAC_IPG2);
1868 writel(0x40, gp->regs + MAC_STIME);
1869 writel(0x40, gp->regs + MAC_MINFSZ);
1870
1871 /* Ethernet payload + header + FCS + optional VLAN tag. */
1872 writel(0x20000000 | (gp->rx_buf_sz + 4), gp->regs + MAC_MAXFSZ);
1873
1874 writel(0x07, gp->regs + MAC_PASIZE);
1875 writel(0x04, gp->regs + MAC_JAMSIZE);
1876 writel(0x10, gp->regs + MAC_ATTLIM);
1877 writel(0x8808, gp->regs + MAC_MCTYPE);
1878
1879 writel((e[5] | (e[4] << 8)) & 0x3ff, gp->regs + MAC_RANDSEED);
1880
1881 writel((e[4] << 8) | e[5], gp->regs + MAC_ADDR0);
1882 writel((e[2] << 8) | e[3], gp->regs + MAC_ADDR1);
1883 writel((e[0] << 8) | e[1], gp->regs + MAC_ADDR2);
1884
1885 writel(0, gp->regs + MAC_ADDR3);
1886 writel(0, gp->regs + MAC_ADDR4);
1887 writel(0, gp->regs + MAC_ADDR5);
1888
1889 writel(0x0001, gp->regs + MAC_ADDR6);
1890 writel(0xc200, gp->regs + MAC_ADDR7);
1891 writel(0x0180, gp->regs + MAC_ADDR8);
1892
1893 writel(0, gp->regs + MAC_AFILT0);
1894 writel(0, gp->regs + MAC_AFILT1);
1895 writel(0, gp->regs + MAC_AFILT2);
1896 writel(0, gp->regs + MAC_AF21MSK);
1897 writel(0, gp->regs + MAC_AF0MSK);
1898
1899 gp->mac_rx_cfg = gem_setup_multicast(gp);
1900#ifdef STRIP_FCS
1901 gp->mac_rx_cfg |= MAC_RXCFG_SFCS;
1902#endif
1903 writel(0, gp->regs + MAC_NCOLL);
1904 writel(0, gp->regs + MAC_FASUCC);
1905 writel(0, gp->regs + MAC_ECOLL);
1906 writel(0, gp->regs + MAC_LCOLL);
1907 writel(0, gp->regs + MAC_DTIMER);
1908 writel(0, gp->regs + MAC_PATMPS);
1909 writel(0, gp->regs + MAC_RFCTR);
1910 writel(0, gp->regs + MAC_LERR);
1911 writel(0, gp->regs + MAC_AERR);
1912 writel(0, gp->regs + MAC_FCSERR);
1913 writel(0, gp->regs + MAC_RXCVERR);
1914
1915 /* Clear RX/TX/MAC/XIF config, we will set these up and enable
1916 * them once a link is established.
1917 */
1918 writel(0, gp->regs + MAC_TXCFG);
1919 writel(gp->mac_rx_cfg, gp->regs + MAC_RXCFG);
1920 writel(0, gp->regs + MAC_MCCFG);
1921 writel(0, gp->regs + MAC_XIFCFG);
1922
1923 /* Setup MAC interrupts. We want to get all of the interesting
1924 * counter expiration events, but we do not want to hear about
1925 * normal rx/tx as the DMA engine tells us that.
1926 */
1927 writel(MAC_TXSTAT_XMIT, gp->regs + MAC_TXMASK);
1928 writel(MAC_RXSTAT_RCV, gp->regs + MAC_RXMASK);
1929
1930 /* Don't enable even the PAUSE interrupts for now, we
1931 * make no use of those events other than to record them.
1932 */
1933 writel(0xffffffff, gp->regs + MAC_MCMASK);
1934
1935 /* Don't enable GEM's WOL in normal operations
1936 */
1937 if (gp->has_wol)
1938 writel(0, gp->regs + WOL_WAKECSR);
1939}
1940
1941/* Must be invoked under gp->lock and gp->tx_lock. */
1942static void gem_init_pause_thresholds(struct gem *gp)
1943{
1944 u32 cfg;
1945
1946 /* Calculate pause thresholds. Setting the OFF threshold to the
1947 * full RX fifo size effectively disables PAUSE generation which
1948 * is what we do for 10/100 only GEMs which have FIFOs too small
1949 * to make real gains from PAUSE.
1950 */
1951 if (gp->rx_fifo_sz <= (2 * 1024)) {
1952 gp->rx_pause_off = gp->rx_pause_on = gp->rx_fifo_sz;
1953 } else {
1954 int max_frame = (gp->rx_buf_sz + 4 + 64) & ~63;
1955 int off = (gp->rx_fifo_sz - (max_frame * 2));
1956 int on = off - max_frame;
1957
1958 gp->rx_pause_off = off;
1959 gp->rx_pause_on = on;
1960 }
1961
1962
1963 /* Configure the chip "burst" DMA mode & enable some
1964 * HW bug fixes on Apple version
1965 */
1966 cfg = 0;
1967 if (gp->pdev->vendor == PCI_VENDOR_ID_APPLE)
1968 cfg |= GREG_CFG_RONPAULBIT | GREG_CFG_ENBUG2FIX;
1969#if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA)
1970 cfg |= GREG_CFG_IBURST;
1971#endif
1972 cfg |= ((31 << 1) & GREG_CFG_TXDMALIM);
1973 cfg |= ((31 << 6) & GREG_CFG_RXDMALIM);
1974 writel(cfg, gp->regs + GREG_CFG);
1975
1976 /* If Infinite Burst didn't stick, then use different
1977 * thresholds (and Apple bug fixes don't exist)
1978 */
1979 if (!(readl(gp->regs + GREG_CFG) & GREG_CFG_IBURST)) {
1980 cfg = ((2 << 1) & GREG_CFG_TXDMALIM);
1981 cfg |= ((8 << 6) & GREG_CFG_RXDMALIM);
1982 writel(cfg, gp->regs + GREG_CFG);
1983 }
1984}
1985
1986static int gem_check_invariants(struct gem *gp)
1987{
1988 struct pci_dev *pdev = gp->pdev;
1989 u32 mif_cfg;
1990
1991 /* On Apple's sungem, we can't rely on registers as the chip
1992 * was been powered down by the firmware. The PHY is looked
1993 * up later on.
1994 */
1995 if (pdev->vendor == PCI_VENDOR_ID_APPLE) {
1996 gp->phy_type = phy_mii_mdio0;
1997 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
1998 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
1999 gp->swrst_base = 0;
2000
2001 mif_cfg = readl(gp->regs + MIF_CFG);
2002 mif_cfg &= ~(MIF_CFG_PSELECT|MIF_CFG_POLL|MIF_CFG_BBMODE|MIF_CFG_MDI1);
2003 mif_cfg |= MIF_CFG_MDI0;
2004 writel(mif_cfg, gp->regs + MIF_CFG);
2005 writel(PCS_DMODE_MGM, gp->regs + PCS_DMODE);
2006 writel(MAC_XIFCFG_OE, gp->regs + MAC_XIFCFG);
2007
2008 /* We hard-code the PHY address so we can properly bring it out of
2009 * reset later on, we can't really probe it at this point, though
2010 * that isn't an issue.
2011 */
2012 if (gp->pdev->device == PCI_DEVICE_ID_APPLE_K2_GMAC)
2013 gp->mii_phy_addr = 1;
2014 else
2015 gp->mii_phy_addr = 0;
2016
2017 return 0;
2018 }
2019
2020 mif_cfg = readl(gp->regs + MIF_CFG);
2021
2022 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2023 pdev->device == PCI_DEVICE_ID_SUN_RIO_GEM) {
2024 /* One of the MII PHYs _must_ be present
2025 * as this chip has no gigabit PHY.
2026 */
2027 if ((mif_cfg & (MIF_CFG_MDI0 | MIF_CFG_MDI1)) == 0) {
2028 printk(KERN_ERR PFX "RIO GEM lacks MII phy, mif_cfg[%08x]\n",
2029 mif_cfg);
2030 return -1;
2031 }
2032 }
2033
2034 /* Determine initial PHY interface type guess. MDIO1 is the
2035 * external PHY and thus takes precedence over MDIO0.
2036 */
2037
2038 if (mif_cfg & MIF_CFG_MDI1) {
2039 gp->phy_type = phy_mii_mdio1;
2040 mif_cfg |= MIF_CFG_PSELECT;
2041 writel(mif_cfg, gp->regs + MIF_CFG);
2042 } else if (mif_cfg & MIF_CFG_MDI0) {
2043 gp->phy_type = phy_mii_mdio0;
2044 mif_cfg &= ~MIF_CFG_PSELECT;
2045 writel(mif_cfg, gp->regs + MIF_CFG);
2046 } else {
2047 gp->phy_type = phy_serialink;
2048 }
2049 if (gp->phy_type == phy_mii_mdio1 ||
2050 gp->phy_type == phy_mii_mdio0) {
2051 int i;
2052
2053 for (i = 0; i < 32; i++) {
2054 gp->mii_phy_addr = i;
2055 if (phy_read(gp, MII_BMCR) != 0xffff)
2056 break;
2057 }
2058 if (i == 32) {
2059 if (pdev->device != PCI_DEVICE_ID_SUN_GEM) {
2060 printk(KERN_ERR PFX "RIO MII phy will not respond.\n");
2061 return -1;
2062 }
2063 gp->phy_type = phy_serdes;
2064 }
2065 }
2066
2067 /* Fetch the FIFO configurations now too. */
2068 gp->tx_fifo_sz = readl(gp->regs + TXDMA_FSZ) * 64;
2069 gp->rx_fifo_sz = readl(gp->regs + RXDMA_FSZ) * 64;
2070
2071 if (pdev->vendor == PCI_VENDOR_ID_SUN) {
2072 if (pdev->device == PCI_DEVICE_ID_SUN_GEM) {
2073 if (gp->tx_fifo_sz != (9 * 1024) ||
2074 gp->rx_fifo_sz != (20 * 1024)) {
2075 printk(KERN_ERR PFX "GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2076 gp->tx_fifo_sz, gp->rx_fifo_sz);
2077 return -1;
2078 }
2079 gp->swrst_base = 0;
2080 } else {
2081 if (gp->tx_fifo_sz != (2 * 1024) ||
2082 gp->rx_fifo_sz != (2 * 1024)) {
2083 printk(KERN_ERR PFX "RIO GEM has bogus fifo sizes tx(%d) rx(%d)\n",
2084 gp->tx_fifo_sz, gp->rx_fifo_sz);
2085 return -1;
2086 }
2087 gp->swrst_base = (64 / 4) << GREG_SWRST_CACHE_SHIFT;
2088 }
2089 }
2090
2091 return 0;
2092}
2093
2094/* Must be invoked under gp->lock and gp->tx_lock. */
2095static void gem_reinit_chip(struct gem *gp)
2096{
2097 /* Reset the chip */
2098 gem_reset(gp);
2099
2100 /* Make sure ints are disabled */
2101 gem_disable_ints(gp);
2102
2103 /* Allocate & setup ring buffers */
2104 gem_init_rings(gp);
2105
2106 /* Configure pause thresholds */
2107 gem_init_pause_thresholds(gp);
2108
2109 /* Init DMA & MAC engines */
2110 gem_init_dma(gp);
2111 gem_init_mac(gp);
2112}
2113
2114
2115/* Must be invoked with no lock held. */
2116static void gem_stop_phy(struct gem *gp, int wol)
2117{
2118 u32 mifcfg;
2119 unsigned long flags;
2120
2121 /* Let the chip settle down a bit, it seems that helps
2122 * for sleep mode on some models
2123 */
2124 msleep(10);
2125
2126 /* Make sure we aren't polling PHY status change. We
2127 * don't currently use that feature though
2128 */
2129 mifcfg = readl(gp->regs + MIF_CFG);
2130 mifcfg &= ~MIF_CFG_POLL;
2131 writel(mifcfg, gp->regs + MIF_CFG);
2132
2133 if (wol && gp->has_wol) {
2134 unsigned char *e = &gp->dev->dev_addr[0];
2135 u32 csr;
2136
2137 /* Setup wake-on-lan for MAGIC packet */
2138 writel(MAC_RXCFG_HFE | MAC_RXCFG_SFCS | MAC_RXCFG_ENAB,
2139 gp->regs + MAC_RXCFG);
2140 writel((e[4] << 8) | e[5], gp->regs + WOL_MATCH0);
2141 writel((e[2] << 8) | e[3], gp->regs + WOL_MATCH1);
2142 writel((e[0] << 8) | e[1], gp->regs + WOL_MATCH2);
2143
2144 writel(WOL_MCOUNT_N | WOL_MCOUNT_M, gp->regs + WOL_MCOUNT);
2145 csr = WOL_WAKECSR_ENABLE;
2146 if ((readl(gp->regs + MAC_XIFCFG) & MAC_XIFCFG_GMII) == 0)
2147 csr |= WOL_WAKECSR_MII;
2148 writel(csr, gp->regs + WOL_WAKECSR);
2149 } else {
2150 writel(0, gp->regs + MAC_RXCFG);
2151 (void)readl(gp->regs + MAC_RXCFG);
2152 /* Machine sleep will die in strange ways if we
2153 * dont wait a bit here, looks like the chip takes
2154 * some time to really shut down
2155 */
2156 msleep(10);
2157 }
2158
2159 writel(0, gp->regs + MAC_TXCFG);
2160 writel(0, gp->regs + MAC_XIFCFG);
2161 writel(0, gp->regs + TXDMA_CFG);
2162 writel(0, gp->regs + RXDMA_CFG);
2163
2164 if (!wol) {
2165 spin_lock_irqsave(&gp->lock, flags);
2166 spin_lock(&gp->tx_lock);
2167 gem_reset(gp);
2168 writel(MAC_TXRST_CMD, gp->regs + MAC_TXRST);
2169 writel(MAC_RXRST_CMD, gp->regs + MAC_RXRST);
2170 spin_unlock(&gp->tx_lock);
2171 spin_unlock_irqrestore(&gp->lock, flags);
2172
2173 /* No need to take the lock here */
2174
2175 if (found_mii_phy(gp) && gp->phy_mii.def->ops->suspend)
2176 gp->phy_mii.def->ops->suspend(&gp->phy_mii);
2177
2178 /* According to Apple, we must set the MDIO pins to this begnign
2179 * state or we may 1) eat more current, 2) damage some PHYs
2180 */
2181 writel(mifcfg | MIF_CFG_BBMODE, gp->regs + MIF_CFG);
2182 writel(0, gp->regs + MIF_BBCLK);
2183 writel(0, gp->regs + MIF_BBDATA);
2184 writel(0, gp->regs + MIF_BBOENAB);
2185 writel(MAC_XIFCFG_GMII | MAC_XIFCFG_LBCK, gp->regs + MAC_XIFCFG);
2186 (void) readl(gp->regs + MAC_XIFCFG);
2187 }
2188}
2189
2190
2191static int gem_do_start(struct net_device *dev)
2192{
2193 struct gem *gp = dev->priv;
2194 unsigned long flags;
2195
2196 spin_lock_irqsave(&gp->lock, flags);
2197 spin_lock(&gp->tx_lock);
2198
2199 /* Enable the cell */
2200 gem_get_cell(gp);
2201
2202 /* Init & setup chip hardware */
2203 gem_reinit_chip(gp);
2204
2205 gp->running = 1;
2206
2207 if (gp->lstate == link_up) {
2208 netif_carrier_on(gp->dev);
2209 gem_set_link_modes(gp);
2210 }
2211
2212 netif_wake_queue(gp->dev);
2213
2214 spin_unlock(&gp->tx_lock);
2215 spin_unlock_irqrestore(&gp->lock, flags);
2216
2217 if (request_irq(gp->pdev->irq, gem_interrupt,
2218 SA_SHIRQ, dev->name, (void *)dev)) {
2219 printk(KERN_ERR "%s: failed to request irq !\n", gp->dev->name);
2220
2221 spin_lock_irqsave(&gp->lock, flags);
2222 spin_lock(&gp->tx_lock);
2223
2224 gp->running = 0;
2225 gem_reset(gp);
2226 gem_clean_rings(gp);
2227 gem_put_cell(gp);
2228
2229 spin_unlock(&gp->tx_lock);
2230 spin_unlock_irqrestore(&gp->lock, flags);
2231
2232 return -EAGAIN;
2233 }
2234
2235 return 0;
2236}
2237
2238static void gem_do_stop(struct net_device *dev, int wol)
2239{
2240 struct gem *gp = dev->priv;
2241 unsigned long flags;
2242
2243 spin_lock_irqsave(&gp->lock, flags);
2244 spin_lock(&gp->tx_lock);
2245
2246 gp->running = 0;
2247
2248 /* Stop netif queue */
2249 netif_stop_queue(dev);
2250
2251 /* Make sure ints are disabled */
2252 gem_disable_ints(gp);
2253
2254 /* We can drop the lock now */
2255 spin_unlock(&gp->tx_lock);
2256 spin_unlock_irqrestore(&gp->lock, flags);
2257
2258 /* If we are going to sleep with WOL */
2259 gem_stop_dma(gp);
2260 msleep(10);
2261 if (!wol)
2262 gem_reset(gp);
2263 msleep(10);
2264
2265 /* Get rid of rings */
2266 gem_clean_rings(gp);
2267
2268 /* No irq needed anymore */
2269 free_irq(gp->pdev->irq, (void *) dev);
2270
2271 /* Cell not needed neither if no WOL */
2272 if (!wol) {
2273 spin_lock_irqsave(&gp->lock, flags);
2274 gem_put_cell(gp);
2275 spin_unlock_irqrestore(&gp->lock, flags);
2276 }
2277}
2278
2279static void gem_reset_task(void *data)
2280{
2281 struct gem *gp = (struct gem *) data;
2282
2283 down(&gp->pm_sem);
2284
2285 netif_poll_disable(gp->dev);
2286
2287 spin_lock_irq(&gp->lock);
2288 spin_lock(&gp->tx_lock);
2289
2290 if (gp->running == 0)
2291 goto not_running;
2292
2293 if (gp->running) {
2294 netif_stop_queue(gp->dev);
2295
2296 /* Reset the chip & rings */
2297 gem_reinit_chip(gp);
2298 if (gp->lstate == link_up)
2299 gem_set_link_modes(gp);
2300 netif_wake_queue(gp->dev);
2301 }
2302 not_running:
2303 gp->reset_task_pending = 0;
2304
2305 spin_unlock(&gp->tx_lock);
2306 spin_unlock_irq(&gp->lock);
2307
2308 netif_poll_enable(gp->dev);
2309
2310 up(&gp->pm_sem);
2311}
2312
2313
2314static int gem_open(struct net_device *dev)
2315{
2316 struct gem *gp = dev->priv;
2317 int rc = 0;
2318
2319 down(&gp->pm_sem);
2320
2321 /* We need the cell enabled */
2322 if (!gp->asleep)
2323 rc = gem_do_start(dev);
2324 gp->opened = (rc == 0);
2325
2326 up(&gp->pm_sem);
2327
2328 return rc;
2329}
2330
2331static int gem_close(struct net_device *dev)
2332{
2333 struct gem *gp = dev->priv;
2334
2335 /* Note: we don't need to call netif_poll_disable() here because
2336 * our caller (dev_close) already did it for us
2337 */
2338
2339 down(&gp->pm_sem);
2340
2341 gp->opened = 0;
2342 if (!gp->asleep)
2343 gem_do_stop(dev, 0);
2344
2345 up(&gp->pm_sem);
2346
2347 return 0;
2348}
2349
2350#ifdef CONFIG_PM
2351static int gem_suspend(struct pci_dev *pdev, pm_message_t state)
2352{
2353 struct net_device *dev = pci_get_drvdata(pdev);
2354 struct gem *gp = dev->priv;
2355 unsigned long flags;
2356
2357 down(&gp->pm_sem);
2358
2359 netif_poll_disable(dev);
2360
2361 printk(KERN_INFO "%s: suspending, WakeOnLan %s\n",
2362 dev->name,
2363 (gp->wake_on_lan && gp->opened) ? "enabled" : "disabled");
2364
2365 /* Keep the cell enabled during the entire operation */
2366 spin_lock_irqsave(&gp->lock, flags);
2367 spin_lock(&gp->tx_lock);
2368 gem_get_cell(gp);
2369 spin_unlock(&gp->tx_lock);
2370 spin_unlock_irqrestore(&gp->lock, flags);
2371
2372 /* If the driver is opened, we stop the MAC */
2373 if (gp->opened) {
2374 /* Stop traffic, mark us closed */
2375 netif_device_detach(dev);
2376
2377 /* Switch off MAC, remember WOL setting */
2378 gp->asleep_wol = gp->wake_on_lan;
2379 gem_do_stop(dev, gp->asleep_wol);
2380 } else
2381 gp->asleep_wol = 0;
2382
2383 /* Mark us asleep */
2384 gp->asleep = 1;
2385 wmb();
2386
2387 /* Stop the link timer */
2388 del_timer_sync(&gp->link_timer);
2389
2390 /* Now we release the semaphore to not block the reset task who
2391 * can take it too. We are marked asleep, so there will be no
2392 * conflict here
2393 */
2394 up(&gp->pm_sem);
2395
2396 /* Wait for a pending reset task to complete */
2397 while (gp->reset_task_pending)
2398 yield();
2399 flush_scheduled_work();
2400
2401 /* Shut the PHY down eventually and setup WOL */
2402 gem_stop_phy(gp, gp->asleep_wol);
2403
2404 /* Make sure bus master is disabled */
2405 pci_disable_device(gp->pdev);
2406
2407 /* Release the cell, no need to take a lock at this point since
2408 * nothing else can happen now
2409 */
2410 gem_put_cell(gp);
2411
2412 return 0;
2413}
2414
2415static int gem_resume(struct pci_dev *pdev)
2416{
2417 struct net_device *dev = pci_get_drvdata(pdev);
2418 struct gem *gp = dev->priv;
2419 unsigned long flags;
2420
2421 printk(KERN_INFO "%s: resuming\n", dev->name);
2422
2423 down(&gp->pm_sem);
2424
2425 /* Keep the cell enabled during the entire operation, no need to
2426 * take a lock here tho since nothing else can happen while we are
2427 * marked asleep
2428 */
2429 gem_get_cell(gp);
2430
2431 /* Make sure PCI access and bus master are enabled */
2432 if (pci_enable_device(gp->pdev)) {
2433 printk(KERN_ERR "%s: Can't re-enable chip !\n",
2434 dev->name);
2435 /* Put cell and forget it for now, it will be considered as
2436 * still asleep, a new sleep cycle may bring it back
2437 */
2438 gem_put_cell(gp);
2439 up(&gp->pm_sem);
2440 return 0;
2441 }
2442 pci_set_master(gp->pdev);
2443
2444 /* Reset everything */
2445 gem_reset(gp);
2446
2447 /* Mark us woken up */
2448 gp->asleep = 0;
2449 wmb();
2450
2451 /* Bring the PHY back. Again, lock is useless at this point as
2452 * nothing can be happening until we restart the whole thing
2453 */
2454 gem_init_phy(gp);
2455
2456 /* If we were opened, bring everything back */
2457 if (gp->opened) {
2458 /* Restart MAC */
2459 gem_do_start(dev);
2460
2461 /* Re-attach net device */
2462 netif_device_attach(dev);
2463
2464 }
2465
2466 spin_lock_irqsave(&gp->lock, flags);
2467 spin_lock(&gp->tx_lock);
2468
2469 /* If we had WOL enabled, the cell clock was never turned off during
2470 * sleep, so we end up beeing unbalanced. Fix that here
2471 */
2472 if (gp->asleep_wol)
2473 gem_put_cell(gp);
2474
2475 /* This function doesn't need to hold the cell, it will be held if the
2476 * driver is open by gem_do_start().
2477 */
2478 gem_put_cell(gp);
2479
2480 spin_unlock(&gp->tx_lock);
2481 spin_unlock_irqrestore(&gp->lock, flags);
2482
2483 netif_poll_enable(dev);
2484
2485 up(&gp->pm_sem);
2486
2487 return 0;
2488}
2489#endif /* CONFIG_PM */
2490
2491static struct net_device_stats *gem_get_stats(struct net_device *dev)
2492{
2493 struct gem *gp = dev->priv;
2494 struct net_device_stats *stats = &gp->net_stats;
2495
2496 spin_lock_irq(&gp->lock);
2497 spin_lock(&gp->tx_lock);
2498
2499 /* I have seen this being called while the PM was in progress,
2500 * so we shield against this
2501 */
2502 if (gp->running) {
2503 stats->rx_crc_errors += readl(gp->regs + MAC_FCSERR);
2504 writel(0, gp->regs + MAC_FCSERR);
2505
2506 stats->rx_frame_errors += readl(gp->regs + MAC_AERR);
2507 writel(0, gp->regs + MAC_AERR);
2508
2509 stats->rx_length_errors += readl(gp->regs + MAC_LERR);
2510 writel(0, gp->regs + MAC_LERR);
2511
2512 stats->tx_aborted_errors += readl(gp->regs + MAC_ECOLL);
2513 stats->collisions +=
2514 (readl(gp->regs + MAC_ECOLL) +
2515 readl(gp->regs + MAC_LCOLL));
2516 writel(0, gp->regs + MAC_ECOLL);
2517 writel(0, gp->regs + MAC_LCOLL);
2518 }
2519
2520 spin_unlock(&gp->tx_lock);
2521 spin_unlock_irq(&gp->lock);
2522
2523 return &gp->net_stats;
2524}
2525
2526static void gem_set_multicast(struct net_device *dev)
2527{
2528 struct gem *gp = dev->priv;
2529 u32 rxcfg, rxcfg_new;
2530 int limit = 10000;
2531
2532
2533 spin_lock_irq(&gp->lock);
2534 spin_lock(&gp->tx_lock);
2535
2536 if (!gp->running)
2537 goto bail;
2538
2539 netif_stop_queue(dev);
2540
2541 rxcfg = readl(gp->regs + MAC_RXCFG);
2542 rxcfg_new = gem_setup_multicast(gp);
2543#ifdef STRIP_FCS
2544 rxcfg_new |= MAC_RXCFG_SFCS;
2545#endif
2546 gp->mac_rx_cfg = rxcfg_new;
2547
2548 writel(rxcfg & ~MAC_RXCFG_ENAB, gp->regs + MAC_RXCFG);
2549 while (readl(gp->regs + MAC_RXCFG) & MAC_RXCFG_ENAB) {
2550 if (!limit--)
2551 break;
2552 udelay(10);
2553 }
2554
2555 rxcfg &= ~(MAC_RXCFG_PROM | MAC_RXCFG_HFE);
2556 rxcfg |= rxcfg_new;
2557
2558 writel(rxcfg, gp->regs + MAC_RXCFG);
2559
2560 netif_wake_queue(dev);
2561
2562 bail:
2563 spin_unlock(&gp->tx_lock);
2564 spin_unlock_irq(&gp->lock);
2565}
2566
2567/* Jumbo-grams don't seem to work :-( */
2568#define GEM_MIN_MTU 68
2569#if 1
2570#define GEM_MAX_MTU 1500
2571#else
2572#define GEM_MAX_MTU 9000
2573#endif
2574
2575static int gem_change_mtu(struct net_device *dev, int new_mtu)
2576{
2577 struct gem *gp = dev->priv;
2578
2579 if (new_mtu < GEM_MIN_MTU || new_mtu > GEM_MAX_MTU)
2580 return -EINVAL;
2581
2582 if (!netif_running(dev) || !netif_device_present(dev)) {
2583 /* We'll just catch it later when the
2584 * device is up'd or resumed.
2585 */
2586 dev->mtu = new_mtu;
2587 return 0;
2588 }
2589
2590 down(&gp->pm_sem);
2591 spin_lock_irq(&gp->lock);
2592 spin_lock(&gp->tx_lock);
2593 dev->mtu = new_mtu;
2594 if (gp->running) {
2595 gem_reinit_chip(gp);
2596 if (gp->lstate == link_up)
2597 gem_set_link_modes(gp);
2598 }
2599 spin_unlock(&gp->tx_lock);
2600 spin_unlock_irq(&gp->lock);
2601 up(&gp->pm_sem);
2602
2603 return 0;
2604}
2605
2606static void gem_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2607{
2608 struct gem *gp = dev->priv;
2609
2610 strcpy(info->driver, DRV_NAME);
2611 strcpy(info->version, DRV_VERSION);
2612 strcpy(info->bus_info, pci_name(gp->pdev));
2613}
2614
2615static int gem_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2616{
2617 struct gem *gp = dev->priv;
2618
2619 if (gp->phy_type == phy_mii_mdio0 ||
2620 gp->phy_type == phy_mii_mdio1) {
2621 if (gp->phy_mii.def)
2622 cmd->supported = gp->phy_mii.def->features;
2623 else
2624 cmd->supported = (SUPPORTED_10baseT_Half |
2625 SUPPORTED_10baseT_Full);
2626
2627 /* XXX hardcoded stuff for now */
2628 cmd->port = PORT_MII;
2629 cmd->transceiver = XCVR_EXTERNAL;
2630 cmd->phy_address = 0; /* XXX fixed PHYAD */
2631
2632 /* Return current PHY settings */
2633 spin_lock_irq(&gp->lock);
2634 cmd->autoneg = gp->want_autoneg;
2635 cmd->speed = gp->phy_mii.speed;
2636 cmd->duplex = gp->phy_mii.duplex;
2637 cmd->advertising = gp->phy_mii.advertising;
2638
2639 /* If we started with a forced mode, we don't have a default
2640 * advertise set, we need to return something sensible so
2641 * userland can re-enable autoneg properly.
2642 */
2643 if (cmd->advertising == 0)
2644 cmd->advertising = cmd->supported;
2645 spin_unlock_irq(&gp->lock);
2646 } else { // XXX PCS ?
2647 cmd->supported =
2648 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2649 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2650 SUPPORTED_Autoneg);
2651 cmd->advertising = cmd->supported;
2652 cmd->speed = 0;
2653 cmd->duplex = cmd->port = cmd->phy_address =
2654 cmd->transceiver = cmd->autoneg = 0;
2655 }
2656 cmd->maxtxpkt = cmd->maxrxpkt = 0;
2657
2658 return 0;
2659}
2660
2661static int gem_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2662{
2663 struct gem *gp = dev->priv;
2664
2665 /* Verify the settings we care about. */
2666 if (cmd->autoneg != AUTONEG_ENABLE &&
2667 cmd->autoneg != AUTONEG_DISABLE)
2668 return -EINVAL;
2669
2670 if (cmd->autoneg == AUTONEG_ENABLE &&
2671 cmd->advertising == 0)
2672 return -EINVAL;
2673
2674 if (cmd->autoneg == AUTONEG_DISABLE &&
2675 ((cmd->speed != SPEED_1000 &&
2676 cmd->speed != SPEED_100 &&
2677 cmd->speed != SPEED_10) ||
2678 (cmd->duplex != DUPLEX_HALF &&
2679 cmd->duplex != DUPLEX_FULL)))
2680 return -EINVAL;
2681
2682 /* Apply settings and restart link process. */
2683 spin_lock_irq(&gp->lock);
2684 gem_get_cell(gp);
2685 gem_begin_auto_negotiation(gp, cmd);
2686 gem_put_cell(gp);
2687 spin_unlock_irq(&gp->lock);
2688
2689 return 0;
2690}
2691
2692static int gem_nway_reset(struct net_device *dev)
2693{
2694 struct gem *gp = dev->priv;
2695
2696 if (!gp->want_autoneg)
2697 return -EINVAL;
2698
2699 /* Restart link process. */
2700 spin_lock_irq(&gp->lock);
2701 gem_get_cell(gp);
2702 gem_begin_auto_negotiation(gp, NULL);
2703 gem_put_cell(gp);
2704 spin_unlock_irq(&gp->lock);
2705
2706 return 0;
2707}
2708
2709static u32 gem_get_msglevel(struct net_device *dev)
2710{
2711 struct gem *gp = dev->priv;
2712 return gp->msg_enable;
2713}
2714
2715static void gem_set_msglevel(struct net_device *dev, u32 value)
2716{
2717 struct gem *gp = dev->priv;
2718 gp->msg_enable = value;
2719}
2720
2721
2722/* Add more when I understand how to program the chip */
2723/* like WAKE_UCAST | WAKE_MCAST | WAKE_BCAST */
2724
2725#define WOL_SUPPORTED_MASK (WAKE_MAGIC)
2726
2727static void gem_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2728{
2729 struct gem *gp = dev->priv;
2730
2731 /* Add more when I understand how to program the chip */
2732 if (gp->has_wol) {
2733 wol->supported = WOL_SUPPORTED_MASK;
2734 wol->wolopts = gp->wake_on_lan;
2735 } else {
2736 wol->supported = 0;
2737 wol->wolopts = 0;
2738 }
2739}
2740
2741static int gem_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2742{
2743 struct gem *gp = dev->priv;
2744
2745 if (!gp->has_wol)
2746 return -EOPNOTSUPP;
2747 gp->wake_on_lan = wol->wolopts & WOL_SUPPORTED_MASK;
2748 return 0;
2749}
2750
2751static struct ethtool_ops gem_ethtool_ops = {
2752 .get_drvinfo = gem_get_drvinfo,
2753 .get_link = ethtool_op_get_link,
2754 .get_settings = gem_get_settings,
2755 .set_settings = gem_set_settings,
2756 .nway_reset = gem_nway_reset,
2757 .get_msglevel = gem_get_msglevel,
2758 .set_msglevel = gem_set_msglevel,
2759 .get_wol = gem_get_wol,
2760 .set_wol = gem_set_wol,
2761};
2762
2763static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2764{
2765 struct gem *gp = dev->priv;
2766 struct mii_ioctl_data *data = if_mii(ifr);
2767 int rc = -EOPNOTSUPP;
2768 unsigned long flags;
2769
2770 /* Hold the PM semaphore while doing ioctl's or we may collide
2771 * with power management.
2772 */
2773 down(&gp->pm_sem);
2774
2775 spin_lock_irqsave(&gp->lock, flags);
2776 gem_get_cell(gp);
2777 spin_unlock_irqrestore(&gp->lock, flags);
2778
2779 switch (cmd) {
2780 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
2781 data->phy_id = gp->mii_phy_addr;
2782 /* Fallthrough... */
2783
2784 case SIOCGMIIREG: /* Read MII PHY register. */
2785 if (!gp->running)
2786 rc = -EAGAIN;
2787 else {
2788 data->val_out = __phy_read(gp, data->phy_id & 0x1f,
2789 data->reg_num & 0x1f);
2790 rc = 0;
2791 }
2792 break;
2793
2794 case SIOCSMIIREG: /* Write MII PHY register. */
2795 if (!capable(CAP_NET_ADMIN))
2796 rc = -EPERM;
2797 else if (!gp->running)
2798 rc = -EAGAIN;
2799 else {
2800 __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
2801 data->val_in);
2802 rc = 0;
2803 }
2804 break;
2805 };
2806
2807 spin_lock_irqsave(&gp->lock, flags);
2808 gem_put_cell(gp);
2809 spin_unlock_irqrestore(&gp->lock, flags);
2810
2811 up(&gp->pm_sem);
2812
2813 return rc;
2814}
2815
2816#if (!defined(__sparc__) && !defined(CONFIG_PPC_PMAC))
2817/* Fetch MAC address from vital product data of PCI ROM. */
2818static void find_eth_addr_in_vpd(void __iomem *rom_base, int len, unsigned char *dev_addr)
2819{
2820 int this_offset;
2821
2822 for (this_offset = 0x20; this_offset < len; this_offset++) {
2823 void __iomem *p = rom_base + this_offset;
2824 int i;
2825
2826 if (readb(p + 0) != 0x90 ||
2827 readb(p + 1) != 0x00 ||
2828 readb(p + 2) != 0x09 ||
2829 readb(p + 3) != 0x4e ||
2830 readb(p + 4) != 0x41 ||
2831 readb(p + 5) != 0x06)
2832 continue;
2833
2834 this_offset += 6;
2835 p += 6;
2836
2837 for (i = 0; i < 6; i++)
2838 dev_addr[i] = readb(p + i);
2839 break;
2840 }
2841}
2842
2843static void get_gem_mac_nonobp(struct pci_dev *pdev, unsigned char *dev_addr)
2844{
2845 u32 rom_reg_orig;
2846 void __iomem *p;
2847
2848 if (pdev->resource[PCI_ROM_RESOURCE].parent == NULL) {
2849 if (pci_assign_resource(pdev, PCI_ROM_RESOURCE) < 0)
2850 goto use_random;
2851 }
2852
2853 pci_read_config_dword(pdev, pdev->rom_base_reg, &rom_reg_orig);
2854 pci_write_config_dword(pdev, pdev->rom_base_reg,
2855 rom_reg_orig | PCI_ROM_ADDRESS_ENABLE);
2856
2857 p = ioremap(pci_resource_start(pdev, PCI_ROM_RESOURCE), (64 * 1024));
2858 if (p != NULL && readb(p) == 0x55 && readb(p + 1) == 0xaa)
2859 find_eth_addr_in_vpd(p, (64 * 1024), dev_addr);
2860
2861 if (p != NULL)
2862 iounmap(p);
2863
2864 pci_write_config_dword(pdev, pdev->rom_base_reg, rom_reg_orig);
2865 return;
2866
2867use_random:
2868 /* Sun MAC prefix then 3 random bytes. */
2869 dev_addr[0] = 0x08;
2870 dev_addr[1] = 0x00;
2871 dev_addr[2] = 0x20;
2872 get_random_bytes(dev_addr + 3, 3);
2873 return;
2874}
2875#endif /* not Sparc and not PPC */
2876
2877static int __devinit gem_get_device_address(struct gem *gp)
2878{
2879#if defined(__sparc__) || defined(CONFIG_PPC_PMAC)
2880 struct net_device *dev = gp->dev;
2881#endif
2882
2883#if defined(__sparc__)
2884 struct pci_dev *pdev = gp->pdev;
2885 struct pcidev_cookie *pcp = pdev->sysdata;
2886 int node = -1;
2887
2888 if (pcp != NULL) {
2889 node = pcp->prom_node;
2890 if (prom_getproplen(node, "local-mac-address") == 6)
2891 prom_getproperty(node, "local-mac-address",
2892 dev->dev_addr, 6);
2893 else
2894 node = -1;
2895 }
2896 if (node == -1)
2897 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2898#elif defined(CONFIG_PPC_PMAC)
2899 unsigned char *addr;
2900
2901 addr = get_property(gp->of_node, "local-mac-address", NULL);
2902 if (addr == NULL) {
2903 printk("\n");
2904 printk(KERN_ERR "%s: can't get mac-address\n", dev->name);
2905 return -1;
2906 }
2907 memcpy(dev->dev_addr, addr, 6);
2908#else
2909 get_gem_mac_nonobp(gp->pdev, gp->dev->dev_addr);
2910#endif
2911 return 0;
2912}
2913
2914static void __devexit gem_remove_one(struct pci_dev *pdev)
2915{
2916 struct net_device *dev = pci_get_drvdata(pdev);
2917
2918 if (dev) {
2919 struct gem *gp = dev->priv;
2920
2921 unregister_netdev(dev);
2922
2923 /* Stop the link timer */
2924 del_timer_sync(&gp->link_timer);
2925
2926 /* We shouldn't need any locking here */
2927 gem_get_cell(gp);
2928
2929 /* Wait for a pending reset task to complete */
2930 while (gp->reset_task_pending)
2931 yield();
2932 flush_scheduled_work();
2933
2934 /* Shut the PHY down */
2935 gem_stop_phy(gp, 0);
2936
2937 gem_put_cell(gp);
2938
2939 /* Make sure bus master is disabled */
2940 pci_disable_device(gp->pdev);
2941
2942 /* Free resources */
2943 pci_free_consistent(pdev,
2944 sizeof(struct gem_init_block),
2945 gp->init_block,
2946 gp->gblock_dvma);
2947 iounmap(gp->regs);
2948 pci_release_regions(pdev);
2949 free_netdev(dev);
2950
2951 pci_set_drvdata(pdev, NULL);
2952 }
2953}
2954
2955static int __devinit gem_init_one(struct pci_dev *pdev,
2956 const struct pci_device_id *ent)
2957{
2958 static int gem_version_printed = 0;
2959 unsigned long gemreg_base, gemreg_len;
2960 struct net_device *dev;
2961 struct gem *gp;
2962 int i, err, pci_using_dac;
2963
2964 if (gem_version_printed++ == 0)
2965 printk(KERN_INFO "%s", version);
2966
2967 /* Apple gmac note: during probe, the chip is powered up by
2968 * the arch code to allow the code below to work (and to let
2969 * the chip be probed on the config space. It won't stay powered
2970 * up until the interface is brought up however, so we can't rely
2971 * on register configuration done at this point.
2972 */
2973 err = pci_enable_device(pdev);
2974 if (err) {
2975 printk(KERN_ERR PFX "Cannot enable MMIO operation, "
2976 "aborting.\n");
2977 return err;
2978 }
2979 pci_set_master(pdev);
2980
2981 /* Configure DMA attributes. */
2982
2983 /* All of the GEM documentation states that 64-bit DMA addressing
2984 * is fully supported and should work just fine. However the
2985 * front end for RIO based GEMs is different and only supports
2986 * 32-bit addressing.
2987 *
2988 * For now we assume the various PPC GEMs are 32-bit only as well.
2989 */
2990 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
2991 pdev->device == PCI_DEVICE_ID_SUN_GEM &&
2992 !pci_set_dma_mask(pdev, (u64) 0xffffffffffffffffULL)) {
2993 pci_using_dac = 1;
2994 } else {
2995 err = pci_set_dma_mask(pdev, (u64) 0xffffffff);
2996 if (err) {
2997 printk(KERN_ERR PFX "No usable DMA configuration, "
2998 "aborting.\n");
2999 goto err_disable_device;
3000 }
3001 pci_using_dac = 0;
3002 }
3003
3004 gemreg_base = pci_resource_start(pdev, 0);
3005 gemreg_len = pci_resource_len(pdev, 0);
3006
3007 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
3008 printk(KERN_ERR PFX "Cannot find proper PCI device "
3009 "base address, aborting.\n");
3010 err = -ENODEV;
3011 goto err_disable_device;
3012 }
3013
3014 dev = alloc_etherdev(sizeof(*gp));
3015 if (!dev) {
3016 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
3017 err = -ENOMEM;
3018 goto err_disable_device;
3019 }
3020 SET_MODULE_OWNER(dev);
3021 SET_NETDEV_DEV(dev, &pdev->dev);
3022
3023 gp = dev->priv;
3024
3025 err = pci_request_regions(pdev, DRV_NAME);
3026 if (err) {
3027 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
3028 "aborting.\n");
3029 goto err_out_free_netdev;
3030 }
3031
3032 gp->pdev = pdev;
3033 dev->base_addr = (long) pdev;
3034 gp->dev = dev;
3035
3036 gp->msg_enable = DEFAULT_MSG;
3037
3038 spin_lock_init(&gp->lock);
3039 spin_lock_init(&gp->tx_lock);
3040 init_MUTEX(&gp->pm_sem);
3041
3042 init_timer(&gp->link_timer);
3043 gp->link_timer.function = gem_link_timer;
3044 gp->link_timer.data = (unsigned long) gp;
3045
3046 INIT_WORK(&gp->reset_task, gem_reset_task, gp);
3047
3048 gp->lstate = link_down;
3049 gp->timer_ticks = 0;
3050 netif_carrier_off(dev);
3051
3052 gp->regs = ioremap(gemreg_base, gemreg_len);
3053 if (gp->regs == 0UL) {
3054 printk(KERN_ERR PFX "Cannot map device registers, "
3055 "aborting.\n");
3056 err = -EIO;
3057 goto err_out_free_res;
3058 }
3059
3060 /* On Apple, we want a reference to the Open Firmware device-tree
3061 * node. We use it for clock control.
3062 */
3063#ifdef CONFIG_PPC_PMAC
3064 gp->of_node = pci_device_to_OF_node(pdev);
3065#endif
3066
3067 /* Only Apple version supports WOL afaik */
3068 if (pdev->vendor == PCI_VENDOR_ID_APPLE)
3069 gp->has_wol = 1;
3070
3071 /* Make sure cell is enabled */
3072 gem_get_cell(gp);
3073
3074 /* Make sure everything is stopped and in init state */
3075 gem_reset(gp);
3076
3077 /* Fill up the mii_phy structure (even if we won't use it) */
3078 gp->phy_mii.dev = dev;
3079 gp->phy_mii.mdio_read = _phy_read;
3080 gp->phy_mii.mdio_write = _phy_write;
3081
3082 /* By default, we start with autoneg */
3083 gp->want_autoneg = 1;
3084
3085 /* Check fifo sizes, PHY type, etc... */
3086 if (gem_check_invariants(gp)) {
3087 err = -ENODEV;
3088 goto err_out_iounmap;
3089 }
3090
3091 /* It is guaranteed that the returned buffer will be at least
3092 * PAGE_SIZE aligned.
3093 */
3094 gp->init_block = (struct gem_init_block *)
3095 pci_alloc_consistent(pdev, sizeof(struct gem_init_block),
3096 &gp->gblock_dvma);
3097 if (!gp->init_block) {
3098 printk(KERN_ERR PFX "Cannot allocate init block, "
3099 "aborting.\n");
3100 err = -ENOMEM;
3101 goto err_out_iounmap;
3102 }
3103
3104 if (gem_get_device_address(gp))
3105 goto err_out_free_consistent;
3106
3107 dev->open = gem_open;
3108 dev->stop = gem_close;
3109 dev->hard_start_xmit = gem_start_xmit;
3110 dev->get_stats = gem_get_stats;
3111 dev->set_multicast_list = gem_set_multicast;
3112 dev->do_ioctl = gem_ioctl;
3113 dev->poll = gem_poll;
3114 dev->weight = 64;
3115 dev->ethtool_ops = &gem_ethtool_ops;
3116 dev->tx_timeout = gem_tx_timeout;
3117 dev->watchdog_timeo = 5 * HZ;
3118 dev->change_mtu = gem_change_mtu;
3119 dev->irq = pdev->irq;
3120 dev->dma = 0;
3121#ifdef CONFIG_NET_POLL_CONTROLLER
3122 dev->poll_controller = gem_poll_controller;
3123#endif
3124
3125 /* Set that now, in case PM kicks in now */
3126 pci_set_drvdata(pdev, dev);
3127
3128 /* Detect & init PHY, start autoneg, we release the cell now
3129 * too, it will be managed by whoever needs it
3130 */
3131 gem_init_phy(gp);
3132
3133 spin_lock_irq(&gp->lock);
3134 gem_put_cell(gp);
3135 spin_unlock_irq(&gp->lock);
3136
3137 /* Register with kernel */
3138 if (register_netdev(dev)) {
3139 printk(KERN_ERR PFX "Cannot register net device, "
3140 "aborting.\n");
3141 err = -ENOMEM;
3142 goto err_out_free_consistent;
3143 }
3144
3145 printk(KERN_INFO "%s: Sun GEM (PCI) 10/100/1000BaseT Ethernet ",
3146 dev->name);
3147 for (i = 0; i < 6; i++)
3148 printk("%2.2x%c", dev->dev_addr[i],
3149 i == 5 ? ' ' : ':');
3150 printk("\n");
3151
3152 if (gp->phy_type == phy_mii_mdio0 ||
3153 gp->phy_type == phy_mii_mdio1)
3154 printk(KERN_INFO "%s: Found %s PHY\n", dev->name,
3155 gp->phy_mii.def ? gp->phy_mii.def->name : "no");
3156
3157 /* GEM can do it all... */
3158 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_LLTX;
3159 if (pci_using_dac)
3160 dev->features |= NETIF_F_HIGHDMA;
3161
3162 return 0;
3163
3164err_out_free_consistent:
3165 gem_remove_one(pdev);
3166err_out_iounmap:
3167 gem_put_cell(gp);
3168 iounmap(gp->regs);
3169
3170err_out_free_res:
3171 pci_release_regions(pdev);
3172
3173err_out_free_netdev:
3174 free_netdev(dev);
3175err_disable_device:
3176 pci_disable_device(pdev);
3177 return err;
3178
3179}
3180
3181
3182static struct pci_driver gem_driver = {
3183 .name = GEM_MODULE_NAME,
3184 .id_table = gem_pci_tbl,
3185 .probe = gem_init_one,
3186 .remove = __devexit_p(gem_remove_one),
3187#ifdef CONFIG_PM
3188 .suspend = gem_suspend,
3189 .resume = gem_resume,
3190#endif /* CONFIG_PM */
3191};
3192
3193static int __init gem_init(void)
3194{
3195 return pci_module_init(&gem_driver);
3196}
3197
3198static void __exit gem_cleanup(void)
3199{
3200 pci_unregister_driver(&gem_driver);
3201}
3202
3203module_init(gem_init);
3204module_exit(gem_cleanup);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-10 22:35:06 -0500