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authorJesse Huang <jesse@icplus.com.tw>2006-10-20 17:42:13 -0400
committerJeff Garzik <jeff@garzik.org>2006-12-02 00:12:02 -0500
commitacd70c2bfddb52aee27a4864c160bea7f0d117e1 (patch)
tree79d5f236d6ed31bc719a6f4f3494c5632119ac51 /drivers/net/sundance.c
parent6b655529c3d817ed1b69cf2dd29e2c3ce5148a2b (diff)
[PATCH] sundance: correct initial and close hardware step.
Correct initial and close hardware step. In some embedded system down and up IP100A will cause DMA crash. We add some for safe down and up IP100A. Signed-off-by: Jesse Huang <jesse@icplus.com.tw> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/sundance.c')
-rw-r--r--drivers/net/sundance.c8
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/net/sundance.c b/drivers/net/sundance.c
index 91cd2f52e628..fba64d39ba19 100644
--- a/drivers/net/sundance.c
+++ b/drivers/net/sundance.c
@@ -788,6 +788,7 @@ static int netdev_open(struct net_device *dev)
788{ 788{
789 struct netdev_private *np = netdev_priv(dev); 789 struct netdev_private *np = netdev_priv(dev);
790 void __iomem *ioaddr = np->base; 790 void __iomem *ioaddr = np->base;
791 unsigned long flags;
791 int i; 792 int i;
792 793
793 /* Do we need to reset the chip??? */ 794 /* Do we need to reset the chip??? */
@@ -832,6 +833,10 @@ static int netdev_open(struct net_device *dev)
832 iowrite8(0x01, ioaddr + DebugCtrl1); 833 iowrite8(0x01, ioaddr + DebugCtrl1);
833 netif_start_queue(dev); 834 netif_start_queue(dev);
834 835
836 spin_lock_irqsave(&np->lock, flags);
837 reset_tx(dev);
838 spin_unlock_irqrestore(&np->lock, flags);
839
835 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1); 840 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
836 841
837 if (netif_msg_ifup(np)) 842 if (netif_msg_ifup(np))
@@ -1651,6 +1656,9 @@ static int netdev_close(struct net_device *dev)
1651 /* Disable interrupts by clearing the interrupt mask. */ 1656 /* Disable interrupts by clearing the interrupt mask. */
1652 iowrite16(0x0000, ioaddr + IntrEnable); 1657 iowrite16(0x0000, ioaddr + IntrEnable);
1653 1658
1659 /* Disable Rx and Tx DMA for safely release resource */
1660 iowrite32(0x500, ioaddr + DMACtrl);
1661
1654 /* Stop the chip's Tx and Rx processes. */ 1662 /* Stop the chip's Tx and Rx processes. */
1655 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1); 1663 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1656 1664