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authorLinus Torvalds <torvalds@linux-foundation.org>2010-03-02 10:55:08 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2010-03-02 10:55:08 -0500
commit6d6b89bd2e316b78d668f761d380837b81fa71ef (patch)
tree7e63c58611fc6181153526abbdafdd846ed1a19d /drivers/net/stmmac
parent13dda80e48439b446d0bc9bab34b91484bc8f533 (diff)
parent2507c05ff55fbf38326b08ed27eaed233bc75042 (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next-2.6: (1341 commits) virtio_net: remove forgotten assignment be2net: fix tx completion polling sis190: fix cable detect via link status poll net: fix protocol sk_buff field bridge: Fix build error when IGMP_SNOOPING is not enabled bnx2x: Tx barriers and locks scm: Only support SCM_RIGHTS on unix domain sockets. vhost-net: restart tx poll on sk_sndbuf full vhost: fix get_user_pages_fast error handling vhost: initialize log eventfd context pointer vhost: logging thinko fix wireless: convert to use netdev_for_each_mc_addr ethtool: do not set some flags, if others failed ipoib: returned back addrlen check for mc addresses netlink: Adding inode field to /proc/net/netlink axnet_cs: add new id bridge: Make IGMP snooping depend upon BRIDGE. bridge: Add multicast count/interval sysfs entries bridge: Add hash elasticity/max sysfs entries bridge: Add multicast_snooping sysfs toggle ... Trivial conflicts in Documentation/feature-removal-schedule.txt
Diffstat (limited to 'drivers/net/stmmac')
-rw-r--r--drivers/net/stmmac/Kconfig8
-rw-r--r--drivers/net/stmmac/Makefile5
-rw-r--r--drivers/net/stmmac/common.h279
-rw-r--r--drivers/net/stmmac/descs.h4
-rw-r--r--drivers/net/stmmac/dwmac100.c (renamed from drivers/net/stmmac/mac100.c)212
-rw-r--r--drivers/net/stmmac/dwmac100.h (renamed from drivers/net/stmmac/mac100.h)0
-rw-r--r--drivers/net/stmmac/dwmac1000.h (renamed from drivers/net/stmmac/gmac.h)18
-rw-r--r--drivers/net/stmmac/dwmac1000_core.c243
-rw-r--r--drivers/net/stmmac/dwmac1000_dma.c (renamed from drivers/net/stmmac/gmac.c)351
-rw-r--r--drivers/net/stmmac/dwmac_dma.h107
-rw-r--r--drivers/net/stmmac/dwmac_lib.c263
-rw-r--r--drivers/net/stmmac/stmmac.h28
-rw-r--r--drivers/net/stmmac/stmmac_ethtool.c11
-rw-r--r--drivers/net/stmmac/stmmac_main.c436
-rw-r--r--drivers/net/stmmac/stmmac_mdio.c11
15 files changed, 1071 insertions, 905 deletions
diff --git a/drivers/net/stmmac/Kconfig b/drivers/net/stmmac/Kconfig
index 35eaa5251d7f..fb287649a305 100644
--- a/drivers/net/stmmac/Kconfig
+++ b/drivers/net/stmmac/Kconfig
@@ -4,8 +4,9 @@ config STMMAC_ETH
4 select PHYLIB 4 select PHYLIB
5 depends on NETDEVICES && CPU_SUBTYPE_ST40 5 depends on NETDEVICES && CPU_SUBTYPE_ST40
6 help 6 help
7 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet 7 This is the driver for the Ethernet IPs are built around a
8 controllers. ST Ethernet IPs are built around a Synopsys IP Core. 8 Synopsys IP Core and fully tested on the STMicroelectronics
9 platforms.
9 10
10if STMMAC_ETH 11if STMMAC_ETH
11 12
@@ -32,7 +33,8 @@ config STMMAC_TIMER
32 default n 33 default n
33 help 34 help
34 Use an external timer for mitigating the number of network 35 Use an external timer for mitigating the number of network
35 interrupts. 36 interrupts. Currently, for SH architectures, it is possible
37 to use the TMU channel 2 and the SH-RTC device.
36 38
37choice 39choice
38 prompt "Select Timer device" 40 prompt "Select Timer device"
diff --git a/drivers/net/stmmac/Makefile b/drivers/net/stmmac/Makefile
index b2d7a5564dfa..c776af15fe1a 100644
--- a/drivers/net/stmmac/Makefile
+++ b/drivers/net/stmmac/Makefile
@@ -1,4 +1,5 @@
1obj-$(CONFIG_STMMAC_ETH) += stmmac.o 1obj-$(CONFIG_STMMAC_ETH) += stmmac.o
2stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o 2stmmac-$(CONFIG_STMMAC_TIMER) += stmmac_timer.o
3stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o \ 3stmmac-objs:= stmmac_main.o stmmac_ethtool.o stmmac_mdio.o \
4 mac100.o gmac.o $(stmmac-y) 4 dwmac_lib.o dwmac1000_core.o dwmac1000_dma.o \
5 dwmac100.o $(stmmac-y)
diff --git a/drivers/net/stmmac/common.h b/drivers/net/stmmac/common.h
index e49e5188e887..2a58172e986a 100644
--- a/drivers/net/stmmac/common.h
+++ b/drivers/net/stmmac/common.h
@@ -23,132 +23,7 @@
23*******************************************************************************/ 23*******************************************************************************/
24 24
25#include "descs.h" 25#include "descs.h"
26#include <linux/io.h> 26#include <linux/netdevice.h>
27
28/* *********************************************
29 DMA CRS Control and Status Register Mapping
30 * *********************************************/
31#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
32#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
33#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
34#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
35#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
36#define DMA_STATUS 0x00001014 /* Status Register */
37#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
38#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
39#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
40#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
41#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
42
43/* ********************************
44 DMA Control register defines
45 * ********************************/
46#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
47#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
48
49/* **************************************
50 DMA Interrupt Enable register defines
51 * **************************************/
52/**** NORMAL INTERRUPT ****/
53#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
54#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
55#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
56#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
57#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
58
59#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
60 DMA_INTR_ENA_TIE)
61
62/**** ABNORMAL INTERRUPT ****/
63#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
64#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
65#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
66#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
67#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
68#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
69#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
70#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
71#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
72#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
73
74#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
75 DMA_INTR_ENA_UNE)
76
77/* DMA default interrupt mask */
78#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
79
80/* ****************************
81 * DMA Status register defines
82 * ****************************/
83#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
84#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
85#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int. */
86#define DMA_STATUS_GMI 0x08000000
87#define DMA_STATUS_GLI 0x04000000
88#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
89#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
90#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
91#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
92#define DMA_STATUS_TS_SHIFT 20
93#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
94#define DMA_STATUS_RS_SHIFT 17
95#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
96#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
97#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
98#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
99#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
100#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
101#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
102#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
103#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
104#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
105#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
106#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
107#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
108#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
109#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
110
111/* Other defines */
112#define HASH_TABLE_SIZE 64
113#define PAUSE_TIME 0x200
114
115/* Flow Control defines */
116#define FLOW_OFF 0
117#define FLOW_RX 1
118#define FLOW_TX 2
119#define FLOW_AUTO (FLOW_TX | FLOW_RX)
120
121/* DMA STORE-AND-FORWARD Operation Mode */
122#define SF_DMA_MODE 1
123
124#define HW_CSUM 1
125#define NO_HW_CSUM 0
126
127/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
128#define BUF_SIZE_16KiB 16384
129#define BUF_SIZE_8KiB 8192
130#define BUF_SIZE_4KiB 4096
131#define BUF_SIZE_2KiB 2048
132
133/* Power Down and WOL */
134#define PMT_NOT_SUPPORTED 0
135#define PMT_SUPPORTED 1
136
137/* Common MAC defines */
138#define MAC_CTRL_REG 0x00000000 /* MAC Control */
139#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
140#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
141
142/* MAC Management Counters register */
143#define MMC_CONTROL 0x00000100 /* MMC Control */
144#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
145#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
146#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
147#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
148
149#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
150#define MMC_CONTROL_MAX_FRM_SHIFT 3
151#define MMC_CONTROL_MAX_FRAME 0x7FF
152 27
153struct stmmac_extra_stats { 28struct stmmac_extra_stats {
154 /* Transmit errors */ 29 /* Transmit errors */
@@ -169,7 +44,7 @@ struct stmmac_extra_stats {
169 unsigned long rx_toolong; 44 unsigned long rx_toolong;
170 unsigned long rx_collision; 45 unsigned long rx_collision;
171 unsigned long rx_crc; 46 unsigned long rx_crc;
172 unsigned long rx_lenght; 47 unsigned long rx_length;
173 unsigned long rx_mii; 48 unsigned long rx_mii;
174 unsigned long rx_multicast; 49 unsigned long rx_multicast;
175 unsigned long rx_gmac_overflow; 50 unsigned long rx_gmac_overflow;
@@ -198,66 +73,62 @@ struct stmmac_extra_stats {
198 unsigned long normal_irq_n; 73 unsigned long normal_irq_n;
199}; 74};
200 75
201/* GMAC core can compute the checksums in HW. */ 76#define HASH_TABLE_SIZE 64
202enum rx_frame_status { 77#define PAUSE_TIME 0x200
78
79/* Flow Control defines */
80#define FLOW_OFF 0
81#define FLOW_RX 1
82#define FLOW_TX 2
83#define FLOW_AUTO (FLOW_TX | FLOW_RX)
84
85#define SF_DMA_MODE 1 /* DMA STORE-AND-FORWARD Operation Mode */
86
87#define HW_CSUM 1
88#define NO_HW_CSUM 0
89enum rx_frame_status { /* IPC status */
203 good_frame = 0, 90 good_frame = 0,
204 discard_frame = 1, 91 discard_frame = 1,
205 csum_none = 2, 92 csum_none = 2,
206}; 93};
207 94
208static inline void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6], 95enum tx_dma_irq_status {
209 unsigned int high, unsigned int low) 96 tx_hard_error = 1,
210{ 97 tx_hard_error_bump_tc = 2,
211 unsigned long data; 98 handle_tx_rx = 3,
212 99};
213 data = (addr[5] << 8) | addr[4];
214 writel(data, ioaddr + high);
215 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
216 writel(data, ioaddr + low);
217 100
218 return; 101/* GMAC TX FIFO is 8K, Rx FIFO is 16K */
219} 102#define BUF_SIZE_16KiB 16384
103#define BUF_SIZE_8KiB 8192
104#define BUF_SIZE_4KiB 4096
105#define BUF_SIZE_2KiB 2048
220 106
221static inline void stmmac_get_mac_addr(unsigned long ioaddr, 107/* Power Down and WOL */
222 unsigned char *addr, unsigned int high, 108#define PMT_NOT_SUPPORTED 0
223 unsigned int low) 109#define PMT_SUPPORTED 1
224{
225 unsigned int hi_addr, lo_addr;
226 110
227 /* Read the MAC address from the hardware */ 111/* Common MAC defines */
228 hi_addr = readl(ioaddr + high); 112#define MAC_CTRL_REG 0x00000000 /* MAC Control */
229 lo_addr = readl(ioaddr + low); 113#define MAC_ENABLE_TX 0x00000008 /* Transmitter Enable */
114#define MAC_RNABLE_RX 0x00000004 /* Receiver Enable */
230 115
231 /* Extract the MAC address from the high and low words */ 116/* MAC Management Counters register */
232 addr[0] = lo_addr & 0xff; 117#define MMC_CONTROL 0x00000100 /* MMC Control */
233 addr[1] = (lo_addr >> 8) & 0xff; 118#define MMC_HIGH_INTR 0x00000104 /* MMC High Interrupt */
234 addr[2] = (lo_addr >> 16) & 0xff; 119#define MMC_LOW_INTR 0x00000108 /* MMC Low Interrupt */
235 addr[3] = (lo_addr >> 24) & 0xff; 120#define MMC_HIGH_INTR_MASK 0x0000010c /* MMC High Interrupt Mask */
236 addr[4] = hi_addr & 0xff; 121#define MMC_LOW_INTR_MASK 0x00000110 /* MMC Low Interrupt Mask */
237 addr[5] = (hi_addr >> 8) & 0xff;
238 122
239 return; 123#define MMC_CONTROL_MAX_FRM_MASK 0x0003ff8 /* Maximum Frame Size */
240} 124#define MMC_CONTROL_MAX_FRM_SHIFT 3
125#define MMC_CONTROL_MAX_FRAME 0x7FF
241 126
242struct stmmac_ops { 127struct stmmac_desc_ops {
243 /* MAC core initialization */ 128 /* DMA RX descriptor ring initialization */
244 void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
245 /* DMA core initialization */
246 int (*dma_init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
247 /* Dump MAC registers */
248 void (*dump_mac_regs) (unsigned long ioaddr);
249 /* Dump DMA registers */
250 void (*dump_dma_regs) (unsigned long ioaddr);
251 /* Set tx/rx threshold in the csr6 register
252 * An invalid value enables the store-and-forward mode */
253 void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
254 /* To track extra statistic (if supported) */
255 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
256 unsigned long ioaddr);
257 /* RX descriptor ring initialization */
258 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size, 129 void (*init_rx_desc) (struct dma_desc *p, unsigned int ring_size,
259 int disable_rx_ic); 130 int disable_rx_ic);
260 /* TX descriptor ring initialization */ 131 /* DMA TX descriptor ring initialization */
261 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size); 132 void (*init_tx_desc) (struct dma_desc *p, unsigned int ring_size);
262 133
263 /* Invoked by the xmit function to prepare the tx descriptor */ 134 /* Invoked by the xmit function to prepare the tx descriptor */
@@ -281,7 +152,6 @@ struct stmmac_ops {
281 /* Get the buffer size from the descriptor */ 152 /* Get the buffer size from the descriptor */
282 int (*get_tx_len) (struct dma_desc *p); 153 int (*get_tx_len) (struct dma_desc *p);
283 /* Handle extra events on specific interrupts hw dependent */ 154 /* Handle extra events on specific interrupts hw dependent */
284 void (*host_irq_status) (unsigned long ioaddr);
285 int (*get_rx_owner) (struct dma_desc *p); 155 int (*get_rx_owner) (struct dma_desc *p);
286 void (*set_rx_owner) (struct dma_desc *p); 156 void (*set_rx_owner) (struct dma_desc *p);
287 /* Get the receive frame size */ 157 /* Get the receive frame size */
@@ -289,6 +159,37 @@ struct stmmac_ops {
289 /* Return the reception status looking at the RDES1 */ 159 /* Return the reception status looking at the RDES1 */
290 int (*rx_status) (void *data, struct stmmac_extra_stats *x, 160 int (*rx_status) (void *data, struct stmmac_extra_stats *x,
291 struct dma_desc *p); 161 struct dma_desc *p);
162};
163
164struct stmmac_dma_ops {
165 /* DMA core initialization */
166 int (*init) (unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx);
167 /* Dump DMA registers */
168 void (*dump_regs) (unsigned long ioaddr);
169 /* Set tx/rx threshold in the csr6 register
170 * An invalid value enables the store-and-forward mode */
171 void (*dma_mode) (unsigned long ioaddr, int txmode, int rxmode);
172 /* To track extra statistic (if supported) */
173 void (*dma_diagnostic_fr) (void *data, struct stmmac_extra_stats *x,
174 unsigned long ioaddr);
175 void (*enable_dma_transmission) (unsigned long ioaddr);
176 void (*enable_dma_irq) (unsigned long ioaddr);
177 void (*disable_dma_irq) (unsigned long ioaddr);
178 void (*start_tx) (unsigned long ioaddr);
179 void (*stop_tx) (unsigned long ioaddr);
180 void (*start_rx) (unsigned long ioaddr);
181 void (*stop_rx) (unsigned long ioaddr);
182 int (*dma_interrupt) (unsigned long ioaddr,
183 struct stmmac_extra_stats *x);
184};
185
186struct stmmac_ops {
187 /* MAC core initialization */
188 void (*core_init) (unsigned long ioaddr) ____cacheline_aligned;
189 /* Dump MAC registers */
190 void (*dump_regs) (unsigned long ioaddr);
191 /* Handle extra events on specific interrupts hw dependent */
192 void (*host_irq_status) (unsigned long ioaddr);
292 /* Multicast filter setting */ 193 /* Multicast filter setting */
293 void (*set_filter) (struct net_device *dev); 194 void (*set_filter) (struct net_device *dev);
294 /* Flow control setting */ 195 /* Flow control setting */
@@ -298,9 +199,9 @@ struct stmmac_ops {
298 void (*pmt) (unsigned long ioaddr, unsigned long mode); 199 void (*pmt) (unsigned long ioaddr, unsigned long mode);
299 /* Set/Get Unicast MAC addresses */ 200 /* Set/Get Unicast MAC addresses */
300 void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr, 201 void (*set_umac_addr) (unsigned long ioaddr, unsigned char *addr,
301 unsigned int reg_n); 202 unsigned int reg_n);
302 void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr, 203 void (*get_umac_addr) (unsigned long ioaddr, unsigned char *addr,
303 unsigned int reg_n); 204 unsigned int reg_n);
304}; 205};
305 206
306struct mac_link { 207struct mac_link {
@@ -314,17 +215,19 @@ struct mii_regs {
314 unsigned int data; /* MII Data */ 215 unsigned int data; /* MII Data */
315}; 216};
316 217
317struct hw_cap { 218struct mac_device_info {
318 unsigned int version; /* Core Version register (GMAC) */ 219 struct stmmac_ops *mac;
319 unsigned int pmt; /* Power-Down mode (GMAC) */ 220 struct stmmac_desc_ops *desc;
221 struct stmmac_dma_ops *dma;
222 unsigned int pmt; /* support Power-Down */
223 struct mii_regs mii; /* MII register Addresses */
320 struct mac_link link; 224 struct mac_link link;
321 struct mii_regs mii;
322}; 225};
323 226
324struct mac_device_info { 227struct mac_device_info *dwmac1000_setup(unsigned long addr);
325 struct hw_cap hw; 228struct mac_device_info *dwmac100_setup(unsigned long addr);
326 struct stmmac_ops *ops;
327};
328 229
329struct mac_device_info *gmac_setup(unsigned long addr); 230extern void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
330struct mac_device_info *mac100_setup(unsigned long addr); 231 unsigned int high, unsigned int low);
232extern void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
233 unsigned int high, unsigned int low);
diff --git a/drivers/net/stmmac/descs.h b/drivers/net/stmmac/descs.h
index 6d2a0b2f5e57..63a03e264694 100644
--- a/drivers/net/stmmac/descs.h
+++ b/drivers/net/stmmac/descs.h
@@ -1,6 +1,6 @@
1/******************************************************************************* 1/*******************************************************************************
2 Header File to describe the DMA descriptors 2 Header File to describe the DMA descriptors.
3 Use enhanced descriptors in case of GMAC Cores. 3 Enhanced descriptors have been in case of DWMAC1000 Cores.
4 4
5 This program is free software; you can redistribute it and/or modify it 5 This program is free software; you can redistribute it and/or modify it
6 under the terms and conditions of the GNU General Public License, 6 under the terms and conditions of the GNU General Public License,
diff --git a/drivers/net/stmmac/mac100.c b/drivers/net/stmmac/dwmac100.c
index 625171b6062b..803b0373d843 100644
--- a/drivers/net/stmmac/mac100.c
+++ b/drivers/net/stmmac/dwmac100.c
@@ -26,23 +26,23 @@
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27*******************************************************************************/ 27*******************************************************************************/
28 28
29#include <linux/netdevice.h>
30#include <linux/crc32.h> 29#include <linux/crc32.h>
31#include <linux/mii.h> 30#include <linux/mii.h>
32#include <linux/phy.h> 31#include <linux/phy.h>
33 32
34#include "common.h" 33#include "common.h"
35#include "mac100.h" 34#include "dwmac100.h"
35#include "dwmac_dma.h"
36 36
37#undef MAC100_DEBUG 37#undef DWMAC100_DEBUG
38/*#define MAC100_DEBUG*/ 38/*#define DWMAC100_DEBUG*/
39#ifdef MAC100_DEBUG 39#ifdef DWMAC100_DEBUG
40#define DBG(fmt, args...) printk(fmt, ## args) 40#define DBG(fmt, args...) printk(fmt, ## args)
41#else 41#else
42#define DBG(fmt, args...) do { } while (0) 42#define DBG(fmt, args...) do { } while (0)
43#endif 43#endif
44 44
45static void mac100_core_init(unsigned long ioaddr) 45static void dwmac100_core_init(unsigned long ioaddr)
46{ 46{
47 u32 value = readl(ioaddr + MAC_CONTROL); 47 u32 value = readl(ioaddr + MAC_CONTROL);
48 48
@@ -54,43 +54,43 @@ static void mac100_core_init(unsigned long ioaddr)
54 return; 54 return;
55} 55}
56 56
57static void mac100_dump_mac_regs(unsigned long ioaddr) 57static void dwmac100_dump_mac_regs(unsigned long ioaddr)
58{ 58{
59 pr_info("\t----------------------------------------------\n" 59 pr_info("\t----------------------------------------------\n"
60 "\t MAC100 CSR (base addr = 0x%8x)\n" 60 "\t DWMAC 100 CSR (base addr = 0x%8x)\n"
61 "\t----------------------------------------------\n", 61 "\t----------------------------------------------\n",
62 (unsigned int)ioaddr); 62 (unsigned int)ioaddr);
63 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL, 63 pr_info("\tcontrol reg (offset 0x%x): 0x%08x\n", MAC_CONTROL,
64 readl(ioaddr + MAC_CONTROL)); 64 readl(ioaddr + MAC_CONTROL));
65 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH, 65 pr_info("\taddr HI (offset 0x%x): 0x%08x\n ", MAC_ADDR_HIGH,
66 readl(ioaddr + MAC_ADDR_HIGH)); 66 readl(ioaddr + MAC_ADDR_HIGH));
67 pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW, 67 pr_info("\taddr LO (offset 0x%x): 0x%08x\n", MAC_ADDR_LOW,
68 readl(ioaddr + MAC_ADDR_LOW)); 68 readl(ioaddr + MAC_ADDR_LOW));
69 pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n", 69 pr_info("\tmulticast hash HI (offset 0x%x): 0x%08x\n",
70 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH)); 70 MAC_HASH_HIGH, readl(ioaddr + MAC_HASH_HIGH));
71 pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n", 71 pr_info("\tmulticast hash LO (offset 0x%x): 0x%08x\n",
72 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW)); 72 MAC_HASH_LOW, readl(ioaddr + MAC_HASH_LOW));
73 pr_info("\tflow control (offset 0x%x): 0x%08x\n", 73 pr_info("\tflow control (offset 0x%x): 0x%08x\n",
74 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL)); 74 MAC_FLOW_CTRL, readl(ioaddr + MAC_FLOW_CTRL));
75 pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1, 75 pr_info("\tVLAN1 tag (offset 0x%x): 0x%08x\n", MAC_VLAN1,
76 readl(ioaddr + MAC_VLAN1)); 76 readl(ioaddr + MAC_VLAN1));
77 pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2, 77 pr_info("\tVLAN2 tag (offset 0x%x): 0x%08x\n", MAC_VLAN2,
78 readl(ioaddr + MAC_VLAN2)); 78 readl(ioaddr + MAC_VLAN2));
79 pr_info("\n\tMAC management counter registers\n"); 79 pr_info("\n\tMAC management counter registers\n");
80 pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n", 80 pr_info("\t MMC crtl (offset 0x%x): 0x%08x\n",
81 MMC_CONTROL, readl(ioaddr + MMC_CONTROL)); 81 MMC_CONTROL, readl(ioaddr + MMC_CONTROL));
82 pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n", 82 pr_info("\t MMC High Interrupt (offset 0x%x): 0x%08x\n",
83 MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR)); 83 MMC_HIGH_INTR, readl(ioaddr + MMC_HIGH_INTR));
84 pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n", 84 pr_info("\t MMC Low Interrupt (offset 0x%x): 0x%08x\n",
85 MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR)); 85 MMC_LOW_INTR, readl(ioaddr + MMC_LOW_INTR));
86 pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n", 86 pr_info("\t MMC High Interrupt Mask (offset 0x%x): 0x%08x\n",
87 MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK)); 87 MMC_HIGH_INTR_MASK, readl(ioaddr + MMC_HIGH_INTR_MASK));
88 pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n", 88 pr_info("\t MMC Low Interrupt Mask (offset 0x%x): 0x%08x\n",
89 MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK)); 89 MMC_LOW_INTR_MASK, readl(ioaddr + MMC_LOW_INTR_MASK));
90 return; 90 return;
91} 91}
92 92
93static int mac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, 93static int dwmac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
94 u32 dma_rx) 94 u32 dma_rx)
95{ 95{
96 u32 value = readl(ioaddr + DMA_BUS_MODE); 96 u32 value = readl(ioaddr + DMA_BUS_MODE);
@@ -117,7 +117,7 @@ static int mac100_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
117/* Store and Forward capability is not used at all.. 117/* Store and Forward capability is not used at all..
118 * The transmit threshold can be programmed by 118 * The transmit threshold can be programmed by
119 * setting the TTC bits in the DMA control register.*/ 119 * setting the TTC bits in the DMA control register.*/
120static void mac100_dma_operation_mode(unsigned long ioaddr, int txmode, 120static void dwmac100_dma_operation_mode(unsigned long ioaddr, int txmode,
121 int rxmode) 121 int rxmode)
122{ 122{
123 u32 csr6 = readl(ioaddr + DMA_CONTROL); 123 u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -134,11 +134,11 @@ static void mac100_dma_operation_mode(unsigned long ioaddr, int txmode,
134 return; 134 return;
135} 135}
136 136
137static void mac100_dump_dma_regs(unsigned long ioaddr) 137static void dwmac100_dump_dma_regs(unsigned long ioaddr)
138{ 138{
139 int i; 139 int i;
140 140
141 DBG(KERN_DEBUG "MAC100 DMA CSR \n"); 141 DBG(KERN_DEBUG "DWMAC 100 DMA CSR \n");
142 for (i = 0; i < 9; i++) 142 for (i = 0; i < 9; i++)
143 pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i, 143 pr_debug("\t CSR%d (offset 0x%x): 0x%08x\n", i,
144 (DMA_BUS_MODE + i * 4), 144 (DMA_BUS_MODE + i * 4),
@@ -151,8 +151,9 @@ static void mac100_dump_dma_regs(unsigned long ioaddr)
151} 151}
152 152
153/* DMA controller has two counters to track the number of 153/* DMA controller has two counters to track the number of
154 the receive missed frames. */ 154 * the receive missed frames. */
155static void mac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 155static void dwmac100_dma_diagnostic_fr(void *data,
156 struct stmmac_extra_stats *x,
156 unsigned long ioaddr) 157 unsigned long ioaddr)
157{ 158{
158 struct net_device_stats *stats = (struct net_device_stats *)data; 159 struct net_device_stats *stats = (struct net_device_stats *)data;
@@ -181,7 +182,8 @@ static void mac100_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x,
181 return; 182 return;
182} 183}
183 184
184static int mac100_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, 185static int dwmac100_get_tx_frame_status(void *data,
186 struct stmmac_extra_stats *x,
185 struct dma_desc *p, unsigned long ioaddr) 187 struct dma_desc *p, unsigned long ioaddr)
186{ 188{
187 int ret = 0; 189 int ret = 0;
@@ -217,7 +219,7 @@ static int mac100_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
217 return ret; 219 return ret;
218} 220}
219 221
220static int mac100_get_tx_len(struct dma_desc *p) 222static int dwmac100_get_tx_len(struct dma_desc *p)
221{ 223{
222 return p->des01.tx.buffer1_size; 224 return p->des01.tx.buffer1_size;
223} 225}
@@ -226,14 +228,15 @@ static int mac100_get_tx_len(struct dma_desc *p)
226 * and, if required, updates the multicast statistics. 228 * and, if required, updates the multicast statistics.
227 * In case of success, it returns csum_none becasue the device 229 * In case of success, it returns csum_none becasue the device
228 * is not able to compute the csum in HW. */ 230 * is not able to compute the csum in HW. */
229static int mac100_get_rx_frame_status(void *data, struct stmmac_extra_stats *x, 231static int dwmac100_get_rx_frame_status(void *data,
232 struct stmmac_extra_stats *x,
230 struct dma_desc *p) 233 struct dma_desc *p)
231{ 234{
232 int ret = csum_none; 235 int ret = csum_none;
233 struct net_device_stats *stats = (struct net_device_stats *)data; 236 struct net_device_stats *stats = (struct net_device_stats *)data;
234 237
235 if (unlikely(p->des01.rx.last_descriptor == 0)) { 238 if (unlikely(p->des01.rx.last_descriptor == 0)) {
236 pr_warning("mac100 Error: Oversized Ethernet " 239 pr_warning("dwmac100 Error: Oversized Ethernet "
237 "frame spanned multiple buffers\n"); 240 "frame spanned multiple buffers\n");
238 stats->rx_length_errors++; 241 stats->rx_length_errors++;
239 return discard_frame; 242 return discard_frame;
@@ -262,7 +265,7 @@ static int mac100_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
262 ret = discard_frame; 265 ret = discard_frame;
263 266
264 if (unlikely(p->des01.rx.length_error)) { 267 if (unlikely(p->des01.rx.length_error)) {
265 x->rx_lenght++; 268 x->rx_length++;
266 ret = discard_frame; 269 ret = discard_frame;
267 } 270 }
268 if (unlikely(p->des01.rx.mii_error)) { 271 if (unlikely(p->des01.rx.mii_error)) {
@@ -276,24 +279,24 @@ static int mac100_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
276 return ret; 279 return ret;
277} 280}
278 281
279static void mac100_irq_status(unsigned long ioaddr) 282static void dwmac100_irq_status(unsigned long ioaddr)
280{ 283{
281 return; 284 return;
282} 285}
283 286
284static void mac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr, 287static void dwmac100_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
285 unsigned int reg_n) 288 unsigned int reg_n)
286{ 289{
287 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 290 stmmac_set_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
288} 291}
289 292
290static void mac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr, 293static void dwmac100_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
291 unsigned int reg_n) 294 unsigned int reg_n)
292{ 295{
293 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW); 296 stmmac_get_mac_addr(ioaddr, addr, MAC_ADDR_HIGH, MAC_ADDR_LOW);
294} 297}
295 298
296static void mac100_set_filter(struct net_device *dev) 299static void dwmac100_set_filter(struct net_device *dev)
297{ 300{
298 unsigned long ioaddr = dev->base_addr; 301 unsigned long ioaddr = dev->base_addr;
299 u32 value = readl(ioaddr + MAC_CONTROL); 302 u32 value = readl(ioaddr + MAC_CONTROL);
@@ -302,29 +305,27 @@ static void mac100_set_filter(struct net_device *dev)
302 value |= MAC_CONTROL_PR; 305 value |= MAC_CONTROL_PR;
303 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO | 306 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_IF | MAC_CONTROL_HO |
304 MAC_CONTROL_HP); 307 MAC_CONTROL_HP);
305 } else if ((dev->mc_count > HASH_TABLE_SIZE) 308 } else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
306 || (dev->flags & IFF_ALLMULTI)) { 309 || (dev->flags & IFF_ALLMULTI)) {
307 value |= MAC_CONTROL_PM; 310 value |= MAC_CONTROL_PM;
308 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO); 311 value &= ~(MAC_CONTROL_PR | MAC_CONTROL_IF | MAC_CONTROL_HO);
309 writel(0xffffffff, ioaddr + MAC_HASH_HIGH); 312 writel(0xffffffff, ioaddr + MAC_HASH_HIGH);
310 writel(0xffffffff, ioaddr + MAC_HASH_LOW); 313 writel(0xffffffff, ioaddr + MAC_HASH_LOW);
311 } else if (dev->mc_count == 0) { /* no multicast */ 314 } else if (netdev_mc_empty(dev)) { /* no multicast */
312 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF | 315 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF |
313 MAC_CONTROL_HO | MAC_CONTROL_HP); 316 MAC_CONTROL_HO | MAC_CONTROL_HP);
314 } else { 317 } else {
315 int i;
316 u32 mc_filter[2]; 318 u32 mc_filter[2];
317 struct dev_mc_list *mclist; 319 struct dev_mc_list *mclist;
318 320
319 /* Perfect filter mode for physical address and Hash 321 /* Perfect filter mode for physical address and Hash
320 filter for multicast */ 322 filter for multicast */
321 value |= MAC_CONTROL_HP; 323 value |= MAC_CONTROL_HP;
322 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR | MAC_CONTROL_IF 324 value &= ~(MAC_CONTROL_PM | MAC_CONTROL_PR |
323 | MAC_CONTROL_HO); 325 MAC_CONTROL_IF | MAC_CONTROL_HO);
324 326
325 memset(mc_filter, 0, sizeof(mc_filter)); 327 memset(mc_filter, 0, sizeof(mc_filter));
326 for (i = 0, mclist = dev->mc_list; 328 netdev_for_each_mc_addr(mclist, dev) {
327 mclist && i < dev->mc_count; i++, mclist = mclist->next) {
328 /* The upper 6 bits of the calculated CRC are used to 329 /* The upper 6 bits of the calculated CRC are used to
329 * index the contens of the hash table */ 330 * index the contens of the hash table */
330 int bit_nr = 331 int bit_nr =
@@ -347,7 +348,7 @@ static void mac100_set_filter(struct net_device *dev)
347 return; 348 return;
348} 349}
349 350
350static void mac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex, 351static void dwmac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
351 unsigned int fc, unsigned int pause_time) 352 unsigned int fc, unsigned int pause_time)
352{ 353{
353 unsigned int flow = MAC_FLOW_CTRL_ENABLE; 354 unsigned int flow = MAC_FLOW_CTRL_ENABLE;
@@ -359,13 +360,15 @@ static void mac100_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
359 return; 360 return;
360} 361}
361 362
362/* No PMT module supported in our SoC for the Ethernet Controller. */ 363/* No PMT module supported for this Ethernet Controller.
363static void mac100_pmt(unsigned long ioaddr, unsigned long mode) 364 * Tested on ST platforms only.
365 */
366static void dwmac100_pmt(unsigned long ioaddr, unsigned long mode)
364{ 367{
365 return; 368 return;
366} 369}
367 370
368static void mac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size, 371static void dwmac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
369 int disable_rx_ic) 372 int disable_rx_ic)
370{ 373{
371 int i; 374 int i;
@@ -381,7 +384,7 @@ static void mac100_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
381 return; 384 return;
382} 385}
383 386
384static void mac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size) 387static void dwmac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
385{ 388{
386 int i; 389 int i;
387 for (i = 0; i < ring_size; i++) { 390 for (i = 0; i < ring_size; i++) {
@@ -393,32 +396,32 @@ static void mac100_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
393 return; 396 return;
394} 397}
395 398
396static int mac100_get_tx_owner(struct dma_desc *p) 399static int dwmac100_get_tx_owner(struct dma_desc *p)
397{ 400{
398 return p->des01.tx.own; 401 return p->des01.tx.own;
399} 402}
400 403
401static int mac100_get_rx_owner(struct dma_desc *p) 404static int dwmac100_get_rx_owner(struct dma_desc *p)
402{ 405{
403 return p->des01.rx.own; 406 return p->des01.rx.own;
404} 407}
405 408
406static void mac100_set_tx_owner(struct dma_desc *p) 409static void dwmac100_set_tx_owner(struct dma_desc *p)
407{ 410{
408 p->des01.tx.own = 1; 411 p->des01.tx.own = 1;
409} 412}
410 413
411static void mac100_set_rx_owner(struct dma_desc *p) 414static void dwmac100_set_rx_owner(struct dma_desc *p)
412{ 415{
413 p->des01.rx.own = 1; 416 p->des01.rx.own = 1;
414} 417}
415 418
416static int mac100_get_tx_ls(struct dma_desc *p) 419static int dwmac100_get_tx_ls(struct dma_desc *p)
417{ 420{
418 return p->des01.tx.last_segment; 421 return p->des01.tx.last_segment;
419} 422}
420 423
421static void mac100_release_tx_desc(struct dma_desc *p) 424static void dwmac100_release_tx_desc(struct dma_desc *p)
422{ 425{
423 int ter = p->des01.tx.end_ring; 426 int ter = p->des01.tx.end_ring;
424 427
@@ -444,74 +447,91 @@ static void mac100_release_tx_desc(struct dma_desc *p)
444 return; 447 return;
445} 448}
446 449
447static void mac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 450static void dwmac100_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
448 int csum_flag) 451 int csum_flag)
449{ 452{
450 p->des01.tx.first_segment = is_fs; 453 p->des01.tx.first_segment = is_fs;
451 p->des01.tx.buffer1_size = len; 454 p->des01.tx.buffer1_size = len;
452} 455}
453 456
454static void mac100_clear_tx_ic(struct dma_desc *p) 457static void dwmac100_clear_tx_ic(struct dma_desc *p)
455{ 458{
456 p->des01.tx.interrupt = 0; 459 p->des01.tx.interrupt = 0;
457} 460}
458 461
459static void mac100_close_tx_desc(struct dma_desc *p) 462static void dwmac100_close_tx_desc(struct dma_desc *p)
460{ 463{
461 p->des01.tx.last_segment = 1; 464 p->des01.tx.last_segment = 1;
462 p->des01.tx.interrupt = 1; 465 p->des01.tx.interrupt = 1;
463} 466}
464 467
465static int mac100_get_rx_frame_len(struct dma_desc *p) 468static int dwmac100_get_rx_frame_len(struct dma_desc *p)
466{ 469{
467 return p->des01.rx.frame_length; 470 return p->des01.rx.frame_length;
468} 471}
469 472
470struct stmmac_ops mac100_driver = { 473struct stmmac_ops dwmac100_ops = {
471 .core_init = mac100_core_init, 474 .core_init = dwmac100_core_init,
472 .dump_mac_regs = mac100_dump_mac_regs, 475 .dump_regs = dwmac100_dump_mac_regs,
473 .dma_init = mac100_dma_init, 476 .host_irq_status = dwmac100_irq_status,
474 .dump_dma_regs = mac100_dump_dma_regs, 477 .set_filter = dwmac100_set_filter,
475 .dma_mode = mac100_dma_operation_mode, 478 .flow_ctrl = dwmac100_flow_ctrl,
476 .dma_diagnostic_fr = mac100_dma_diagnostic_fr, 479 .pmt = dwmac100_pmt,
477 .tx_status = mac100_get_tx_frame_status, 480 .set_umac_addr = dwmac100_set_umac_addr,
478 .rx_status = mac100_get_rx_frame_status, 481 .get_umac_addr = dwmac100_get_umac_addr,
479 .get_tx_len = mac100_get_tx_len,
480 .set_filter = mac100_set_filter,
481 .flow_ctrl = mac100_flow_ctrl,
482 .pmt = mac100_pmt,
483 .init_rx_desc = mac100_init_rx_desc,
484 .init_tx_desc = mac100_init_tx_desc,
485 .get_tx_owner = mac100_get_tx_owner,
486 .get_rx_owner = mac100_get_rx_owner,
487 .release_tx_desc = mac100_release_tx_desc,
488 .prepare_tx_desc = mac100_prepare_tx_desc,
489 .clear_tx_ic = mac100_clear_tx_ic,
490 .close_tx_desc = mac100_close_tx_desc,
491 .get_tx_ls = mac100_get_tx_ls,
492 .set_tx_owner = mac100_set_tx_owner,
493 .set_rx_owner = mac100_set_rx_owner,
494 .get_rx_frame_len = mac100_get_rx_frame_len,
495 .host_irq_status = mac100_irq_status,
496 .set_umac_addr = mac100_set_umac_addr,
497 .get_umac_addr = mac100_get_umac_addr,
498}; 482};
499 483
500struct mac_device_info *mac100_setup(unsigned long ioaddr) 484struct stmmac_dma_ops dwmac100_dma_ops = {
485 .init = dwmac100_dma_init,
486 .dump_regs = dwmac100_dump_dma_regs,
487 .dma_mode = dwmac100_dma_operation_mode,
488 .dma_diagnostic_fr = dwmac100_dma_diagnostic_fr,
489 .enable_dma_transmission = dwmac_enable_dma_transmission,
490 .enable_dma_irq = dwmac_enable_dma_irq,
491 .disable_dma_irq = dwmac_disable_dma_irq,
492 .start_tx = dwmac_dma_start_tx,
493 .stop_tx = dwmac_dma_stop_tx,
494 .start_rx = dwmac_dma_start_rx,
495 .stop_rx = dwmac_dma_stop_rx,
496 .dma_interrupt = dwmac_dma_interrupt,
497};
498
499struct stmmac_desc_ops dwmac100_desc_ops = {
500 .tx_status = dwmac100_get_tx_frame_status,
501 .rx_status = dwmac100_get_rx_frame_status,
502 .get_tx_len = dwmac100_get_tx_len,
503 .init_rx_desc = dwmac100_init_rx_desc,
504 .init_tx_desc = dwmac100_init_tx_desc,
505 .get_tx_owner = dwmac100_get_tx_owner,
506 .get_rx_owner = dwmac100_get_rx_owner,
507 .release_tx_desc = dwmac100_release_tx_desc,
508 .prepare_tx_desc = dwmac100_prepare_tx_desc,
509 .clear_tx_ic = dwmac100_clear_tx_ic,
510 .close_tx_desc = dwmac100_close_tx_desc,
511 .get_tx_ls = dwmac100_get_tx_ls,
512 .set_tx_owner = dwmac100_set_tx_owner,
513 .set_rx_owner = dwmac100_set_rx_owner,
514 .get_rx_frame_len = dwmac100_get_rx_frame_len,
515};
516
517struct mac_device_info *dwmac100_setup(unsigned long ioaddr)
501{ 518{
502 struct mac_device_info *mac; 519 struct mac_device_info *mac;
503 520
504 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); 521 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
505 522
506 pr_info("\tMAC 10/100\n"); 523 pr_info("\tDWMAC100\n");
524
525 mac->mac = &dwmac100_ops;
526 mac->desc = &dwmac100_desc_ops;
527 mac->dma = &dwmac100_dma_ops;
507 528
508 mac->ops = &mac100_driver; 529 mac->pmt = PMT_NOT_SUPPORTED;
509 mac->hw.pmt = PMT_NOT_SUPPORTED; 530 mac->link.port = MAC_CONTROL_PS;
510 mac->hw.link.port = MAC_CONTROL_PS; 531 mac->link.duplex = MAC_CONTROL_F;
511 mac->hw.link.duplex = MAC_CONTROL_F; 532 mac->link.speed = 0;
512 mac->hw.link.speed = 0; 533 mac->mii.addr = MAC_MII_ADDR;
513 mac->hw.mii.addr = MAC_MII_ADDR; 534 mac->mii.data = MAC_MII_DATA;
514 mac->hw.mii.data = MAC_MII_DATA;
515 535
516 return mac; 536 return mac;
517} 537}
diff --git a/drivers/net/stmmac/mac100.h b/drivers/net/stmmac/dwmac100.h
index 0f8f110d004a..0f8f110d004a 100644
--- a/drivers/net/stmmac/mac100.h
+++ b/drivers/net/stmmac/dwmac100.h
diff --git a/drivers/net/stmmac/gmac.h b/drivers/net/stmmac/dwmac1000.h
index 2e82d6c9a148..62dca0e384e7 100644
--- a/drivers/net/stmmac/gmac.h
+++ b/drivers/net/stmmac/dwmac1000.h
@@ -20,6 +20,9 @@
20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21*******************************************************************************/ 21*******************************************************************************/
22 22
23#include <linux/phy.h>
24#include "common.h"
25
23#define GMAC_CONTROL 0x00000000 /* Configuration */ 26#define GMAC_CONTROL 0x00000000 /* Configuration */
24#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */ 27#define GMAC_FRAME_FILTER 0x00000004 /* Frame Filter */
25#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */ 28#define GMAC_HASH_HIGH 0x00000008 /* Multicast Hash Table High */
@@ -32,7 +35,7 @@
32#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */ 35#define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
33 36
34#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */ 37#define GMAC_INT_STATUS 0x00000038 /* interrupt status register */
35enum gmac_irq_status { 38enum dwmac1000_irq_status {
36 time_stamp_irq = 0x0200, 39 time_stamp_irq = 0x0200,
37 mmc_rx_csum_offload_irq = 0x0080, 40 mmc_rx_csum_offload_irq = 0x0080,
38 mmc_tx_irq = 0x0040, 41 mmc_tx_irq = 0x0040,
@@ -202,3 +205,16 @@ enum rtc_control {
202#define GMAC_MMC_RX_INTR 0x104 205#define GMAC_MMC_RX_INTR 0x104
203#define GMAC_MMC_TX_INTR 0x108 206#define GMAC_MMC_TX_INTR 0x108
204#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208 207#define GMAC_MMC_RX_CSUM_OFFLOAD 0x208
208
209#undef DWMAC1000_DEBUG
210/* #define DWMAC1000__DEBUG */
211#undef FRAME_FILTER_DEBUG
212/* #define FRAME_FILTER_DEBUG */
213#ifdef DWMAC1000__DEBUG
214#define DBG(fmt, args...) printk(fmt, ## args)
215#else
216#define DBG(fmt, args...) do { } while (0)
217#endif
218
219extern struct stmmac_dma_ops dwmac1000_dma_ops;
220extern struct stmmac_desc_ops dwmac1000_desc_ops;
diff --git a/drivers/net/stmmac/dwmac1000_core.c b/drivers/net/stmmac/dwmac1000_core.c
new file mode 100644
index 000000000000..a6538ae4694c
--- /dev/null
+++ b/drivers/net/stmmac/dwmac1000_core.c
@@ -0,0 +1,243 @@
1/*******************************************************************************
2 This is the driver for the GMAC on-chip Ethernet controller for ST SoCs.
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
4 developing this code.
5
6 This only implements the mac core functions for this chip.
7
8 Copyright (C) 2007-2009 STMicroelectronics Ltd
9
10 This program is free software; you can redistribute it and/or modify it
11 under the terms and conditions of the GNU General Public License,
12 version 2, as published by the Free Software Foundation.
13
14 This program is distributed in the hope it will be useful, but WITHOUT
15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 more details.
18
19 You should have received a copy of the GNU General Public License along with
20 this program; if not, write to the Free Software Foundation, Inc.,
21 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
22
23 The full GNU General Public License is included in this distribution in
24 the file called "COPYING".
25
26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
27*******************************************************************************/
28
29#include <linux/crc32.h>
30#include "dwmac1000.h"
31
32static void dwmac1000_core_init(unsigned long ioaddr)
33{
34 u32 value = readl(ioaddr + GMAC_CONTROL);
35 value |= GMAC_CORE_INIT;
36 writel(value, ioaddr + GMAC_CONTROL);
37
38 /* STBus Bridge Configuration */
39 /*writel(0xc5608, ioaddr + 0x00007000);*/
40
41 /* Freeze MMC counters */
42 writel(0x8, ioaddr + GMAC_MMC_CTRL);
43 /* Mask GMAC interrupts */
44 writel(0x207, ioaddr + GMAC_INT_MASK);
45
46#ifdef STMMAC_VLAN_TAG_USED
47 /* Tag detection without filtering */
48 writel(0x0, ioaddr + GMAC_VLAN_TAG);
49#endif
50 return;
51}
52
53static void dwmac1000_dump_regs(unsigned long ioaddr)
54{
55 int i;
56 pr_info("\tDWMAC1000 regs (base addr = 0x%8x)\n", (unsigned int)ioaddr);
57
58 for (i = 0; i < 55; i++) {
59 int offset = i * 4;
60 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
61 offset, readl(ioaddr + offset));
62 }
63 return;
64}
65
66static void dwmac1000_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
67 unsigned int reg_n)
68{
69 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
70 GMAC_ADDR_LOW(reg_n));
71}
72
73static void dwmac1000_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
74 unsigned int reg_n)
75{
76 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
77 GMAC_ADDR_LOW(reg_n));
78}
79
80static void dwmac1000_set_filter(struct net_device *dev)
81{
82 unsigned long ioaddr = dev->base_addr;
83 unsigned int value = 0;
84
85 DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
86 __func__, netdev_mc_count(dev), netdev_uc_count(dev));
87
88 if (dev->flags & IFF_PROMISC)
89 value = GMAC_FRAME_FILTER_PR;
90 else if ((netdev_mc_count(dev) > HASH_TABLE_SIZE)
91 || (dev->flags & IFF_ALLMULTI)) {
92 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
93 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
94 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
95 } else if (!netdev_mc_empty(dev)) {
96 u32 mc_filter[2];
97 struct dev_mc_list *mclist;
98
99 /* Hash filter for multicast */
100 value = GMAC_FRAME_FILTER_HMC;
101
102 memset(mc_filter, 0, sizeof(mc_filter));
103 netdev_for_each_mc_addr(mclist, dev) {
104 /* The upper 6 bits of the calculated CRC are used to
105 index the contens of the hash table */
106 int bit_nr =
107 bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
108 /* The most significant bit determines the register to
109 * use (H/L) while the other 5 bits determine the bit
110 * within the register. */
111 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
112 }
113 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
114 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
115 }
116
117 /* Handle multiple unicast addresses (perfect filtering)*/
118 if (netdev_uc_count(dev) > GMAC_MAX_UNICAST_ADDRESSES)
119 /* Switch to promiscuous mode is more than 16 addrs
120 are required */
121 value |= GMAC_FRAME_FILTER_PR;
122 else {
123 int reg = 1;
124 struct netdev_hw_addr *ha;
125
126 netdev_for_each_uc_addr(ha, dev) {
127 dwmac1000_set_umac_addr(ioaddr, ha->addr, reg);
128 reg++;
129 }
130 }
131
132#ifdef FRAME_FILTER_DEBUG
133 /* Enable Receive all mode (to debug filtering_fail errors) */
134 value |= GMAC_FRAME_FILTER_RA;
135#endif
136 writel(value, ioaddr + GMAC_FRAME_FILTER);
137
138 DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
139 "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
140 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
141
142 return;
143}
144
145static void dwmac1000_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
146 unsigned int fc, unsigned int pause_time)
147{
148 unsigned int flow = 0;
149
150 DBG(KERN_DEBUG "GMAC Flow-Control:\n");
151 if (fc & FLOW_RX) {
152 DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
153 flow |= GMAC_FLOW_CTRL_RFE;
154 }
155 if (fc & FLOW_TX) {
156 DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
157 flow |= GMAC_FLOW_CTRL_TFE;
158 }
159
160 if (duplex) {
161 DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
162 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
163 }
164
165 writel(flow, ioaddr + GMAC_FLOW_CTRL);
166 return;
167}
168
169static void dwmac1000_pmt(unsigned long ioaddr, unsigned long mode)
170{
171 unsigned int pmt = 0;
172
173 if (mode == WAKE_MAGIC) {
174 DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
175 pmt |= power_down | magic_pkt_en;
176 } else if (mode == WAKE_UCAST) {
177 DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
178 pmt |= global_unicast;
179 }
180
181 writel(pmt, ioaddr + GMAC_PMT);
182 return;
183}
184
185
186static void dwmac1000_irq_status(unsigned long ioaddr)
187{
188 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
189
190 /* Not used events (e.g. MMC interrupts) are not handled. */
191 if ((intr_status & mmc_tx_irq))
192 DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
193 readl(ioaddr + GMAC_MMC_TX_INTR));
194 if (unlikely(intr_status & mmc_rx_irq))
195 DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
196 readl(ioaddr + GMAC_MMC_RX_INTR));
197 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
198 DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
199 readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
200 if (unlikely(intr_status & pmt_irq)) {
201 DBG(KERN_DEBUG "GMAC: received Magic frame\n");
202 /* clear the PMT bits 5 and 6 by reading the PMT
203 * status register. */
204 readl(ioaddr + GMAC_PMT);
205 }
206
207 return;
208}
209
210struct stmmac_ops dwmac1000_ops = {
211 .core_init = dwmac1000_core_init,
212 .dump_regs = dwmac1000_dump_regs,
213 .host_irq_status = dwmac1000_irq_status,
214 .set_filter = dwmac1000_set_filter,
215 .flow_ctrl = dwmac1000_flow_ctrl,
216 .pmt = dwmac1000_pmt,
217 .set_umac_addr = dwmac1000_set_umac_addr,
218 .get_umac_addr = dwmac1000_get_umac_addr,
219};
220
221struct mac_device_info *dwmac1000_setup(unsigned long ioaddr)
222{
223 struct mac_device_info *mac;
224 u32 uid = readl(ioaddr + GMAC_VERSION);
225
226 pr_info("\tDWMAC1000 - user ID: 0x%x, Synopsys ID: 0x%x\n",
227 ((uid & 0x0000ff00) >> 8), (uid & 0x000000ff));
228
229 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL);
230
231 mac->mac = &dwmac1000_ops;
232 mac->desc = &dwmac1000_desc_ops;
233 mac->dma = &dwmac1000_dma_ops;
234
235 mac->pmt = PMT_SUPPORTED;
236 mac->link.port = GMAC_CONTROL_PS;
237 mac->link.duplex = GMAC_CONTROL_DM;
238 mac->link.speed = GMAC_CONTROL_FES;
239 mac->mii.addr = GMAC_MII_ADDR;
240 mac->mii.data = GMAC_MII_DATA;
241
242 return mac;
243}
diff --git a/drivers/net/stmmac/gmac.c b/drivers/net/stmmac/dwmac1000_dma.c
index 52586ee68953..39d436a2da68 100644
--- a/drivers/net/stmmac/gmac.c
+++ b/drivers/net/stmmac/dwmac1000_dma.c
@@ -3,6 +3,8 @@
3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for 3 DWC Ether MAC 10/100/1000 Universal version 3.41a has been used for
4 developing this code. 4 developing this code.
5 5
6 This contains the functions to handle the dma and descriptors.
7
6 Copyright (C) 2007-2009 STMicroelectronics Ltd 8 Copyright (C) 2007-2009 STMicroelectronics Ltd
7 9
8 This program is free software; you can redistribute it and/or modify it 10 This program is free software; you can redistribute it and/or modify it
@@ -24,41 +26,11 @@
24 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 26 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25*******************************************************************************/ 27*******************************************************************************/
26 28
27#include <linux/netdevice.h> 29#include "dwmac1000.h"
28#include <linux/crc32.h> 30#include "dwmac_dma.h"
29#include <linux/mii.h>
30#include <linux/phy.h>
31
32#include "stmmac.h"
33#include "gmac.h"
34
35#undef GMAC_DEBUG
36/*#define GMAC_DEBUG*/
37#undef FRAME_FILTER_DEBUG
38/*#define FRAME_FILTER_DEBUG*/
39#ifdef GMAC_DEBUG
40#define DBG(fmt, args...) printk(fmt, ## args)
41#else
42#define DBG(fmt, args...) do { } while (0)
43#endif
44 31
45static void gmac_dump_regs(unsigned long ioaddr) 32static int dwmac1000_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx,
46{ 33 u32 dma_rx)
47 int i;
48 pr_info("\t----------------------------------------------\n"
49 "\t GMAC registers (base addr = 0x%8x)\n"
50 "\t----------------------------------------------\n",
51 (unsigned int)ioaddr);
52
53 for (i = 0; i < 55; i++) {
54 int offset = i * 4;
55 pr_info("\tReg No. %d (offset 0x%x): 0x%08x\n", i,
56 offset, readl(ioaddr + offset));
57 }
58 return;
59}
60
61static int gmac_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx)
62{ 34{
63 u32 value = readl(ioaddr + DMA_BUS_MODE); 35 u32 value = readl(ioaddr + DMA_BUS_MODE);
64 /* DMA SW reset */ 36 /* DMA SW reset */
@@ -87,7 +59,7 @@ static int gmac_dma_init(unsigned long ioaddr, int pbl, u32 dma_tx, u32 dma_rx)
87} 59}
88 60
89/* Transmit FIFO flush operation */ 61/* Transmit FIFO flush operation */
90static void gmac_flush_tx_fifo(unsigned long ioaddr) 62static void dwmac1000_flush_tx_fifo(unsigned long ioaddr)
91{ 63{
92 u32 csr6 = readl(ioaddr + DMA_CONTROL); 64 u32 csr6 = readl(ioaddr + DMA_CONTROL);
93 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL); 65 writel((csr6 | DMA_CONTROL_FTF), ioaddr + DMA_CONTROL);
@@ -95,7 +67,7 @@ static void gmac_flush_tx_fifo(unsigned long ioaddr)
95 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF)); 67 do {} while ((readl(ioaddr + DMA_CONTROL) & DMA_CONTROL_FTF));
96} 68}
97 69
98static void gmac_dma_operation_mode(unsigned long ioaddr, int txmode, 70static void dwmac1000_dma_operation_mode(unsigned long ioaddr, int txmode,
99 int rxmode) 71 int rxmode)
100{ 72{
101 u32 csr6 = readl(ioaddr + DMA_CONTROL); 73 u32 csr6 = readl(ioaddr + DMA_CONTROL);
@@ -148,13 +120,13 @@ static void gmac_dma_operation_mode(unsigned long ioaddr, int txmode,
148} 120}
149 121
150/* Not yet implemented --- no RMON module */ 122/* Not yet implemented --- no RMON module */
151static void gmac_dma_diagnostic_fr(void *data, struct stmmac_extra_stats *x, 123static void dwmac1000_dma_diagnostic_fr(void *data,
152 unsigned long ioaddr) 124 struct stmmac_extra_stats *x, unsigned long ioaddr)
153{ 125{
154 return; 126 return;
155} 127}
156 128
157static void gmac_dump_dma_regs(unsigned long ioaddr) 129static void dwmac1000_dump_dma_regs(unsigned long ioaddr)
158{ 130{
159 int i; 131 int i;
160 pr_info(" DMA registers\n"); 132 pr_info(" DMA registers\n");
@@ -169,8 +141,9 @@ static void gmac_dump_dma_regs(unsigned long ioaddr)
169 return; 141 return;
170} 142}
171 143
172static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x, 144static int dwmac1000_get_tx_frame_status(void *data,
173 struct dma_desc *p, unsigned long ioaddr) 145 struct stmmac_extra_stats *x,
146 struct dma_desc *p, unsigned long ioaddr)
174{ 147{
175 int ret = 0; 148 int ret = 0;
176 struct net_device_stats *stats = (struct net_device_stats *)data; 149 struct net_device_stats *stats = (struct net_device_stats *)data;
@@ -185,7 +158,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
185 if (unlikely(p->des01.etx.frame_flushed)) { 158 if (unlikely(p->des01.etx.frame_flushed)) {
186 DBG(KERN_ERR "\tframe_flushed error\n"); 159 DBG(KERN_ERR "\tframe_flushed error\n");
187 x->tx_frame_flushed++; 160 x->tx_frame_flushed++;
188 gmac_flush_tx_fifo(ioaddr); 161 dwmac1000_flush_tx_fifo(ioaddr);
189 } 162 }
190 163
191 if (unlikely(p->des01.etx.loss_carrier)) { 164 if (unlikely(p->des01.etx.loss_carrier)) {
@@ -213,7 +186,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
213 186
214 if (unlikely(p->des01.etx.underflow_error)) { 187 if (unlikely(p->des01.etx.underflow_error)) {
215 DBG(KERN_ERR "\tunderflow error\n"); 188 DBG(KERN_ERR "\tunderflow error\n");
216 gmac_flush_tx_fifo(ioaddr); 189 dwmac1000_flush_tx_fifo(ioaddr);
217 x->tx_underflow++; 190 x->tx_underflow++;
218 } 191 }
219 192
@@ -225,7 +198,7 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
225 if (unlikely(p->des01.etx.payload_error)) { 198 if (unlikely(p->des01.etx.payload_error)) {
226 DBG(KERN_ERR "\tAddr/Payload csum error\n"); 199 DBG(KERN_ERR "\tAddr/Payload csum error\n");
227 x->tx_payload_error++; 200 x->tx_payload_error++;
228 gmac_flush_tx_fifo(ioaddr); 201 dwmac1000_flush_tx_fifo(ioaddr);
229 } 202 }
230 203
231 ret = -1; 204 ret = -1;
@@ -245,19 +218,19 @@ static int gmac_get_tx_frame_status(void *data, struct stmmac_extra_stats *x,
245 return ret; 218 return ret;
246} 219}
247 220
248static int gmac_get_tx_len(struct dma_desc *p) 221static int dwmac1000_get_tx_len(struct dma_desc *p)
249{ 222{
250 return p->des01.etx.buffer1_size; 223 return p->des01.etx.buffer1_size;
251} 224}
252 225
253static int gmac_coe_rdes0(int ipc_err, int type, int payload_err) 226static int dwmac1000_coe_rdes0(int ipc_err, int type, int payload_err)
254{ 227{
255 int ret = good_frame; 228 int ret = good_frame;
256 u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7; 229 u32 status = (type << 2 | ipc_err << 1 | payload_err) & 0x7;
257 230
258 /* bits 5 7 0 | Frame status 231 /* bits 5 7 0 | Frame status
259 * ---------------------------------------------------------- 232 * ----------------------------------------------------------
260 * 0 0 0 | IEEE 802.3 Type frame (lenght < 1536 octects) 233 * 0 0 0 | IEEE 802.3 Type frame (length < 1536 octects)
261 * 1 0 0 | IPv4/6 No CSUM errorS. 234 * 1 0 0 | IPv4/6 No CSUM errorS.
262 * 1 0 1 | IPv4/6 CSUM PAYLOAD error 235 * 1 0 1 | IPv4/6 CSUM PAYLOAD error
263 * 1 1 0 | IPv4/6 CSUM IP HR error 236 * 1 1 0 | IPv4/6 CSUM IP HR error
@@ -293,8 +266,8 @@ static int gmac_coe_rdes0(int ipc_err, int type, int payload_err)
293 return ret; 266 return ret;
294} 267}
295 268
296static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x, 269static int dwmac1000_get_rx_frame_status(void *data,
297 struct dma_desc *p) 270 struct stmmac_extra_stats *x, struct dma_desc *p)
298{ 271{
299 int ret = good_frame; 272 int ret = good_frame;
300 struct net_device_stats *stats = (struct net_device_stats *)data; 273 struct net_device_stats *stats = (struct net_device_stats *)data;
@@ -339,7 +312,7 @@ static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
339 * It doesn't match with the information reported into the databook. 312 * It doesn't match with the information reported into the databook.
340 * At any rate, we need to understand if the CSUM hw computation is ok 313 * At any rate, we need to understand if the CSUM hw computation is ok
341 * and report this info to the upper layers. */ 314 * and report this info to the upper layers. */
342 ret = gmac_coe_rdes0(p->des01.erx.ipc_csum_error, 315 ret = dwmac1000_coe_rdes0(p->des01.erx.ipc_csum_error,
343 p->des01.erx.frame_type, p->des01.erx.payload_csum_error); 316 p->des01.erx.frame_type, p->des01.erx.payload_csum_error);
344 317
345 if (unlikely(p->des01.erx.dribbling)) { 318 if (unlikely(p->des01.erx.dribbling)) {
@@ -358,7 +331,7 @@ static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
358 } 331 }
359 if (unlikely(p->des01.erx.length_error)) { 332 if (unlikely(p->des01.erx.length_error)) {
360 DBG(KERN_ERR "GMAC RX: length_error error\n"); 333 DBG(KERN_ERR "GMAC RX: length_error error\n");
361 x->rx_lenght++; 334 x->rx_length++;
362 ret = discard_frame; 335 ret = discard_frame;
363 } 336 }
364#ifdef STMMAC_VLAN_TAG_USED 337#ifdef STMMAC_VLAN_TAG_USED
@@ -370,181 +343,7 @@ static int gmac_get_rx_frame_status(void *data, struct stmmac_extra_stats *x,
370 return ret; 343 return ret;
371} 344}
372 345
373static void gmac_irq_status(unsigned long ioaddr) 346static void dwmac1000_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
374{
375 u32 intr_status = readl(ioaddr + GMAC_INT_STATUS);
376
377 /* Not used events (e.g. MMC interrupts) are not handled. */
378 if ((intr_status & mmc_tx_irq))
379 DBG(KERN_DEBUG "GMAC: MMC tx interrupt: 0x%08x\n",
380 readl(ioaddr + GMAC_MMC_TX_INTR));
381 if (unlikely(intr_status & mmc_rx_irq))
382 DBG(KERN_DEBUG "GMAC: MMC rx interrupt: 0x%08x\n",
383 readl(ioaddr + GMAC_MMC_RX_INTR));
384 if (unlikely(intr_status & mmc_rx_csum_offload_irq))
385 DBG(KERN_DEBUG "GMAC: MMC rx csum offload: 0x%08x\n",
386 readl(ioaddr + GMAC_MMC_RX_CSUM_OFFLOAD));
387 if (unlikely(intr_status & pmt_irq)) {
388 DBG(KERN_DEBUG "GMAC: received Magic frame\n");
389 /* clear the PMT bits 5 and 6 by reading the PMT
390 * status register. */
391 readl(ioaddr + GMAC_PMT);
392 }
393
394 return;
395}
396
397static void gmac_core_init(unsigned long ioaddr)
398{
399 u32 value = readl(ioaddr + GMAC_CONTROL);
400 value |= GMAC_CORE_INIT;
401 writel(value, ioaddr + GMAC_CONTROL);
402
403 /* STBus Bridge Configuration */
404 /*writel(0xc5608, ioaddr + 0x00007000);*/
405
406 /* Freeze MMC counters */
407 writel(0x8, ioaddr + GMAC_MMC_CTRL);
408 /* Mask GMAC interrupts */
409 writel(0x207, ioaddr + GMAC_INT_MASK);
410
411#ifdef STMMAC_VLAN_TAG_USED
412 /* Tag detection without filtering */
413 writel(0x0, ioaddr + GMAC_VLAN_TAG);
414#endif
415 return;
416}
417
418static void gmac_set_umac_addr(unsigned long ioaddr, unsigned char *addr,
419 unsigned int reg_n)
420{
421 stmmac_set_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
422 GMAC_ADDR_LOW(reg_n));
423}
424
425static void gmac_get_umac_addr(unsigned long ioaddr, unsigned char *addr,
426 unsigned int reg_n)
427{
428 stmmac_get_mac_addr(ioaddr, addr, GMAC_ADDR_HIGH(reg_n),
429 GMAC_ADDR_LOW(reg_n));
430}
431
432static void gmac_set_filter(struct net_device *dev)
433{
434 unsigned long ioaddr = dev->base_addr;
435 unsigned int value = 0;
436
437 DBG(KERN_INFO "%s: # mcasts %d, # unicast %d\n",
438 __func__, dev->mc_count, dev->uc_count);
439
440 if (dev->flags & IFF_PROMISC)
441 value = GMAC_FRAME_FILTER_PR;
442 else if ((dev->mc_count > HASH_TABLE_SIZE)
443 || (dev->flags & IFF_ALLMULTI)) {
444 value = GMAC_FRAME_FILTER_PM; /* pass all multi */
445 writel(0xffffffff, ioaddr + GMAC_HASH_HIGH);
446 writel(0xffffffff, ioaddr + GMAC_HASH_LOW);
447 } else if (dev->mc_count > 0) {
448 int i;
449 u32 mc_filter[2];
450 struct dev_mc_list *mclist;
451
452 /* Hash filter for multicast */
453 value = GMAC_FRAME_FILTER_HMC;
454
455 memset(mc_filter, 0, sizeof(mc_filter));
456 for (i = 0, mclist = dev->mc_list;
457 mclist && i < dev->mc_count; i++, mclist = mclist->next) {
458 /* The upper 6 bits of the calculated CRC are used to
459 index the contens of the hash table */
460 int bit_nr =
461 bitrev32(~crc32_le(~0, mclist->dmi_addr, 6)) >> 26;
462 /* The most significant bit determines the register to
463 * use (H/L) while the other 5 bits determine the bit
464 * within the register. */
465 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
466 }
467 writel(mc_filter[0], ioaddr + GMAC_HASH_LOW);
468 writel(mc_filter[1], ioaddr + GMAC_HASH_HIGH);
469 }
470
471 /* Handle multiple unicast addresses (perfect filtering)*/
472 if (dev->uc_count > GMAC_MAX_UNICAST_ADDRESSES)
473 /* Switch to promiscuous mode is more than 16 addrs
474 are required */
475 value |= GMAC_FRAME_FILTER_PR;
476 else {
477 int i;
478 struct dev_addr_list *uc_ptr = dev->uc_list;
479
480 for (i = 0; i < dev->uc_count; i++) {
481 gmac_set_umac_addr(ioaddr, uc_ptr->da_addr,
482 i + 1);
483
484 DBG(KERN_INFO "\t%d "
485 "- Unicast addr %02x:%02x:%02x:%02x:%02x:"
486 "%02x\n", i + 1,
487 uc_ptr->da_addr[0], uc_ptr->da_addr[1],
488 uc_ptr->da_addr[2], uc_ptr->da_addr[3],
489 uc_ptr->da_addr[4], uc_ptr->da_addr[5]);
490 uc_ptr = uc_ptr->next;
491 }
492 }
493
494#ifdef FRAME_FILTER_DEBUG
495 /* Enable Receive all mode (to debug filtering_fail errors) */
496 value |= GMAC_FRAME_FILTER_RA;
497#endif
498 writel(value, ioaddr + GMAC_FRAME_FILTER);
499
500 DBG(KERN_INFO "\tFrame Filter reg: 0x%08x\n\tHash regs: "
501 "HI 0x%08x, LO 0x%08x\n", readl(ioaddr + GMAC_FRAME_FILTER),
502 readl(ioaddr + GMAC_HASH_HIGH), readl(ioaddr + GMAC_HASH_LOW));
503
504 return;
505}
506
507static void gmac_flow_ctrl(unsigned long ioaddr, unsigned int duplex,
508 unsigned int fc, unsigned int pause_time)
509{
510 unsigned int flow = 0;
511
512 DBG(KERN_DEBUG "GMAC Flow-Control:\n");
513 if (fc & FLOW_RX) {
514 DBG(KERN_DEBUG "\tReceive Flow-Control ON\n");
515 flow |= GMAC_FLOW_CTRL_RFE;
516 }
517 if (fc & FLOW_TX) {
518 DBG(KERN_DEBUG "\tTransmit Flow-Control ON\n");
519 flow |= GMAC_FLOW_CTRL_TFE;
520 }
521
522 if (duplex) {
523 DBG(KERN_DEBUG "\tduplex mode: pause time: %d\n", pause_time);
524 flow |= (pause_time << GMAC_FLOW_CTRL_PT_SHIFT);
525 }
526
527 writel(flow, ioaddr + GMAC_FLOW_CTRL);
528 return;
529}
530
531static void gmac_pmt(unsigned long ioaddr, unsigned long mode)
532{
533 unsigned int pmt = 0;
534
535 if (mode == WAKE_MAGIC) {
536 DBG(KERN_DEBUG "GMAC: WOL Magic frame\n");
537 pmt |= power_down | magic_pkt_en;
538 } else if (mode == WAKE_UCAST) {
539 DBG(KERN_DEBUG "GMAC: WOL on global unicast\n");
540 pmt |= global_unicast;
541 }
542
543 writel(pmt, ioaddr + GMAC_PMT);
544 return;
545}
546
547static void gmac_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
548 int disable_rx_ic) 347 int disable_rx_ic)
549{ 348{
550 int i; 349 int i;
@@ -562,7 +361,7 @@ static void gmac_init_rx_desc(struct dma_desc *p, unsigned int ring_size,
562 return; 361 return;
563} 362}
564 363
565static void gmac_init_tx_desc(struct dma_desc *p, unsigned int ring_size) 364static void dwmac1000_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
566{ 365{
567 int i; 366 int i;
568 367
@@ -576,32 +375,32 @@ static void gmac_init_tx_desc(struct dma_desc *p, unsigned int ring_size)
576 return; 375 return;
577} 376}
578 377
579static int gmac_get_tx_owner(struct dma_desc *p) 378static int dwmac1000_get_tx_owner(struct dma_desc *p)
580{ 379{
581 return p->des01.etx.own; 380 return p->des01.etx.own;
582} 381}
583 382
584static int gmac_get_rx_owner(struct dma_desc *p) 383static int dwmac1000_get_rx_owner(struct dma_desc *p)
585{ 384{
586 return p->des01.erx.own; 385 return p->des01.erx.own;
587} 386}
588 387
589static void gmac_set_tx_owner(struct dma_desc *p) 388static void dwmac1000_set_tx_owner(struct dma_desc *p)
590{ 389{
591 p->des01.etx.own = 1; 390 p->des01.etx.own = 1;
592} 391}
593 392
594static void gmac_set_rx_owner(struct dma_desc *p) 393static void dwmac1000_set_rx_owner(struct dma_desc *p)
595{ 394{
596 p->des01.erx.own = 1; 395 p->des01.erx.own = 1;
597} 396}
598 397
599static int gmac_get_tx_ls(struct dma_desc *p) 398static int dwmac1000_get_tx_ls(struct dma_desc *p)
600{ 399{
601 return p->des01.etx.last_segment; 400 return p->des01.etx.last_segment;
602} 401}
603 402
604static void gmac_release_tx_desc(struct dma_desc *p) 403static void dwmac1000_release_tx_desc(struct dma_desc *p)
605{ 404{
606 int ter = p->des01.etx.end_ring; 405 int ter = p->des01.etx.end_ring;
607 406
@@ -611,7 +410,7 @@ static void gmac_release_tx_desc(struct dma_desc *p)
611 return; 410 return;
612} 411}
613 412
614static void gmac_prepare_tx_desc(struct dma_desc *p, int is_fs, int len, 413static void dwmac1000_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
615 int csum_flag) 414 int csum_flag)
616{ 415{
617 p->des01.etx.first_segment = is_fs; 416 p->des01.etx.first_segment = is_fs;
@@ -625,69 +424,51 @@ static void gmac_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
625 p->des01.etx.checksum_insertion = cic_full; 424 p->des01.etx.checksum_insertion = cic_full;
626} 425}
627 426
628static void gmac_clear_tx_ic(struct dma_desc *p) 427static void dwmac1000_clear_tx_ic(struct dma_desc *p)
629{ 428{
630 p->des01.etx.interrupt = 0; 429 p->des01.etx.interrupt = 0;
631} 430}
632 431
633static void gmac_close_tx_desc(struct dma_desc *p) 432static void dwmac1000_close_tx_desc(struct dma_desc *p)
634{ 433{
635 p->des01.etx.last_segment = 1; 434 p->des01.etx.last_segment = 1;
636 p->des01.etx.interrupt = 1; 435 p->des01.etx.interrupt = 1;
637} 436}
638 437
639static int gmac_get_rx_frame_len(struct dma_desc *p) 438static int dwmac1000_get_rx_frame_len(struct dma_desc *p)
640{ 439{
641 return p->des01.erx.frame_length; 440 return p->des01.erx.frame_length;
642} 441}
643 442
644struct stmmac_ops gmac_driver = { 443struct stmmac_dma_ops dwmac1000_dma_ops = {
645 .core_init = gmac_core_init, 444 .init = dwmac1000_dma_init,
646 .dump_mac_regs = gmac_dump_regs, 445 .dump_regs = dwmac1000_dump_dma_regs,
647 .dma_init = gmac_dma_init, 446 .dma_mode = dwmac1000_dma_operation_mode,
648 .dump_dma_regs = gmac_dump_dma_regs, 447 .dma_diagnostic_fr = dwmac1000_dma_diagnostic_fr,
649 .dma_mode = gmac_dma_operation_mode, 448 .enable_dma_transmission = dwmac_enable_dma_transmission,
650 .dma_diagnostic_fr = gmac_dma_diagnostic_fr, 449 .enable_dma_irq = dwmac_enable_dma_irq,
651 .tx_status = gmac_get_tx_frame_status, 450 .disable_dma_irq = dwmac_disable_dma_irq,
652 .rx_status = gmac_get_rx_frame_status, 451 .start_tx = dwmac_dma_start_tx,
653 .get_tx_len = gmac_get_tx_len, 452 .stop_tx = dwmac_dma_stop_tx,
654 .set_filter = gmac_set_filter, 453 .start_rx = dwmac_dma_start_rx,
655 .flow_ctrl = gmac_flow_ctrl, 454 .stop_rx = dwmac_dma_stop_rx,
656 .pmt = gmac_pmt, 455 .dma_interrupt = dwmac_dma_interrupt,
657 .init_rx_desc = gmac_init_rx_desc,
658 .init_tx_desc = gmac_init_tx_desc,
659 .get_tx_owner = gmac_get_tx_owner,
660 .get_rx_owner = gmac_get_rx_owner,
661 .release_tx_desc = gmac_release_tx_desc,
662 .prepare_tx_desc = gmac_prepare_tx_desc,
663 .clear_tx_ic = gmac_clear_tx_ic,
664 .close_tx_desc = gmac_close_tx_desc,
665 .get_tx_ls = gmac_get_tx_ls,
666 .set_tx_owner = gmac_set_tx_owner,
667 .set_rx_owner = gmac_set_rx_owner,
668 .get_rx_frame_len = gmac_get_rx_frame_len,
669 .host_irq_status = gmac_irq_status,
670 .set_umac_addr = gmac_set_umac_addr,
671 .get_umac_addr = gmac_get_umac_addr,
672}; 456};
673 457
674struct mac_device_info *gmac_setup(unsigned long ioaddr) 458struct stmmac_desc_ops dwmac1000_desc_ops = {
675{ 459 .tx_status = dwmac1000_get_tx_frame_status,
676 struct mac_device_info *mac; 460 .rx_status = dwmac1000_get_rx_frame_status,
677 u32 uid = readl(ioaddr + GMAC_VERSION); 461 .get_tx_len = dwmac1000_get_tx_len,
678 462 .init_rx_desc = dwmac1000_init_rx_desc,
679 pr_info("\tGMAC - user ID: 0x%x, Synopsys ID: 0x%x\n", 463 .init_tx_desc = dwmac1000_init_tx_desc,
680 ((uid & 0x0000ff00) >> 8), (uid & 0x000000ff)); 464 .get_tx_owner = dwmac1000_get_tx_owner,
681 465 .get_rx_owner = dwmac1000_get_rx_owner,
682 mac = kzalloc(sizeof(const struct mac_device_info), GFP_KERNEL); 466 .release_tx_desc = dwmac1000_release_tx_desc,
683 467 .prepare_tx_desc = dwmac1000_prepare_tx_desc,
684 mac->ops = &gmac_driver; 468 .clear_tx_ic = dwmac1000_clear_tx_ic,
685 mac->hw.pmt = PMT_SUPPORTED; 469 .close_tx_desc = dwmac1000_close_tx_desc,
686 mac->hw.link.port = GMAC_CONTROL_PS; 470 .get_tx_ls = dwmac1000_get_tx_ls,
687 mac->hw.link.duplex = GMAC_CONTROL_DM; 471 .set_tx_owner = dwmac1000_set_tx_owner,
688 mac->hw.link.speed = GMAC_CONTROL_FES; 472 .set_rx_owner = dwmac1000_set_rx_owner,
689 mac->hw.mii.addr = GMAC_MII_ADDR; 473 .get_rx_frame_len = dwmac1000_get_rx_frame_len,
690 mac->hw.mii.data = GMAC_MII_DATA; 474};
691
692 return mac;
693}
diff --git a/drivers/net/stmmac/dwmac_dma.h b/drivers/net/stmmac/dwmac_dma.h
new file mode 100644
index 000000000000..de848d9f6060
--- /dev/null
+++ b/drivers/net/stmmac/dwmac_dma.h
@@ -0,0 +1,107 @@
1/*******************************************************************************
2 DWMAC DMA Header file.
3
4 Copyright (C) 2007-2009 STMicroelectronics Ltd
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
23*******************************************************************************/
24
25/* DMA CRS Control and Status Register Mapping */
26#define DMA_BUS_MODE 0x00001000 /* Bus Mode */
27#define DMA_XMT_POLL_DEMAND 0x00001004 /* Transmit Poll Demand */
28#define DMA_RCV_POLL_DEMAND 0x00001008 /* Received Poll Demand */
29#define DMA_RCV_BASE_ADDR 0x0000100c /* Receive List Base */
30#define DMA_TX_BASE_ADDR 0x00001010 /* Transmit List Base */
31#define DMA_STATUS 0x00001014 /* Status Register */
32#define DMA_CONTROL 0x00001018 /* Ctrl (Operational Mode) */
33#define DMA_INTR_ENA 0x0000101c /* Interrupt Enable */
34#define DMA_MISSED_FRAME_CTR 0x00001020 /* Missed Frame Counter */
35#define DMA_CUR_TX_BUF_ADDR 0x00001050 /* Current Host Tx Buffer */
36#define DMA_CUR_RX_BUF_ADDR 0x00001054 /* Current Host Rx Buffer */
37
38/* DMA Control register defines */
39#define DMA_CONTROL_ST 0x00002000 /* Start/Stop Transmission */
40#define DMA_CONTROL_SR 0x00000002 /* Start/Stop Receive */
41
42/* DMA Normal interrupt */
43#define DMA_INTR_ENA_NIE 0x00010000 /* Normal Summary */
44#define DMA_INTR_ENA_TIE 0x00000001 /* Transmit Interrupt */
45#define DMA_INTR_ENA_TUE 0x00000004 /* Transmit Buffer Unavailable */
46#define DMA_INTR_ENA_RIE 0x00000040 /* Receive Interrupt */
47#define DMA_INTR_ENA_ERE 0x00004000 /* Early Receive */
48
49#define DMA_INTR_NORMAL (DMA_INTR_ENA_NIE | DMA_INTR_ENA_RIE | \
50 DMA_INTR_ENA_TIE)
51
52/* DMA Abnormal interrupt */
53#define DMA_INTR_ENA_AIE 0x00008000 /* Abnormal Summary */
54#define DMA_INTR_ENA_FBE 0x00002000 /* Fatal Bus Error */
55#define DMA_INTR_ENA_ETE 0x00000400 /* Early Transmit */
56#define DMA_INTR_ENA_RWE 0x00000200 /* Receive Watchdog */
57#define DMA_INTR_ENA_RSE 0x00000100 /* Receive Stopped */
58#define DMA_INTR_ENA_RUE 0x00000080 /* Receive Buffer Unavailable */
59#define DMA_INTR_ENA_UNE 0x00000020 /* Tx Underflow */
60#define DMA_INTR_ENA_OVE 0x00000010 /* Receive Overflow */
61#define DMA_INTR_ENA_TJE 0x00000008 /* Transmit Jabber */
62#define DMA_INTR_ENA_TSE 0x00000002 /* Transmit Stopped */
63
64#define DMA_INTR_ABNORMAL (DMA_INTR_ENA_AIE | DMA_INTR_ENA_FBE | \
65 DMA_INTR_ENA_UNE)
66
67/* DMA default interrupt mask */
68#define DMA_INTR_DEFAULT_MASK (DMA_INTR_NORMAL | DMA_INTR_ABNORMAL)
69
70/* DMA Status register defines */
71#define DMA_STATUS_GPI 0x10000000 /* PMT interrupt */
72#define DMA_STATUS_GMI 0x08000000 /* MMC interrupt */
73#define DMA_STATUS_GLI 0x04000000 /* GMAC Line interface int */
74#define DMA_STATUS_GMI 0x08000000
75#define DMA_STATUS_GLI 0x04000000
76#define DMA_STATUS_EB_MASK 0x00380000 /* Error Bits Mask */
77#define DMA_STATUS_EB_TX_ABORT 0x00080000 /* Error Bits - TX Abort */
78#define DMA_STATUS_EB_RX_ABORT 0x00100000 /* Error Bits - RX Abort */
79#define DMA_STATUS_TS_MASK 0x00700000 /* Transmit Process State */
80#define DMA_STATUS_TS_SHIFT 20
81#define DMA_STATUS_RS_MASK 0x000e0000 /* Receive Process State */
82#define DMA_STATUS_RS_SHIFT 17
83#define DMA_STATUS_NIS 0x00010000 /* Normal Interrupt Summary */
84#define DMA_STATUS_AIS 0x00008000 /* Abnormal Interrupt Summary */
85#define DMA_STATUS_ERI 0x00004000 /* Early Receive Interrupt */
86#define DMA_STATUS_FBI 0x00002000 /* Fatal Bus Error Interrupt */
87#define DMA_STATUS_ETI 0x00000400 /* Early Transmit Interrupt */
88#define DMA_STATUS_RWT 0x00000200 /* Receive Watchdog Timeout */
89#define DMA_STATUS_RPS 0x00000100 /* Receive Process Stopped */
90#define DMA_STATUS_RU 0x00000080 /* Receive Buffer Unavailable */
91#define DMA_STATUS_RI 0x00000040 /* Receive Interrupt */
92#define DMA_STATUS_UNF 0x00000020 /* Transmit Underflow */
93#define DMA_STATUS_OVF 0x00000010 /* Receive Overflow */
94#define DMA_STATUS_TJT 0x00000008 /* Transmit Jabber Timeout */
95#define DMA_STATUS_TU 0x00000004 /* Transmit Buffer Unavailable */
96#define DMA_STATUS_TPS 0x00000002 /* Transmit Process Stopped */
97#define DMA_STATUS_TI 0x00000001 /* Transmit Interrupt */
98
99extern void dwmac_enable_dma_transmission(unsigned long ioaddr);
100extern void dwmac_enable_dma_irq(unsigned long ioaddr);
101extern void dwmac_disable_dma_irq(unsigned long ioaddr);
102extern void dwmac_dma_start_tx(unsigned long ioaddr);
103extern void dwmac_dma_stop_tx(unsigned long ioaddr);
104extern void dwmac_dma_start_rx(unsigned long ioaddr);
105extern void dwmac_dma_stop_rx(unsigned long ioaddr);
106extern int dwmac_dma_interrupt(unsigned long ioaddr,
107 struct stmmac_extra_stats *x);
diff --git a/drivers/net/stmmac/dwmac_lib.c b/drivers/net/stmmac/dwmac_lib.c
new file mode 100644
index 000000000000..d4adb1eaa447
--- /dev/null
+++ b/drivers/net/stmmac/dwmac_lib.c
@@ -0,0 +1,263 @@
1/*******************************************************************************
2 Copyright (C) 2007-2009 STMicroelectronics Ltd
3
4 This program is free software; you can redistribute it and/or modify it
5 under the terms and conditions of the GNU General Public License,
6 version 2, as published by the Free Software Foundation.
7
8 This program is distributed in the hope it will be useful, but WITHOUT
9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 more details.
12
13 You should have received a copy of the GNU General Public License along with
14 this program; if not, write to the Free Software Foundation, Inc.,
15 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
16
17 The full GNU General Public License is included in this distribution in
18 the file called "COPYING".
19
20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21*******************************************************************************/
22
23#include <linux/io.h>
24#include "common.h"
25#include "dwmac_dma.h"
26
27#undef DWMAC_DMA_DEBUG
28#ifdef DWMAC_DMA_DEBUG
29#define DBG(fmt, args...) printk(fmt, ## args)
30#else
31#define DBG(fmt, args...) do { } while (0)
32#endif
33
34/* CSR1 enables the transmit DMA to check for new descriptor */
35void dwmac_enable_dma_transmission(unsigned long ioaddr)
36{
37 writel(1, ioaddr + DMA_XMT_POLL_DEMAND);
38}
39
40void dwmac_enable_dma_irq(unsigned long ioaddr)
41{
42 writel(DMA_INTR_DEFAULT_MASK, ioaddr + DMA_INTR_ENA);
43}
44
45void dwmac_disable_dma_irq(unsigned long ioaddr)
46{
47 writel(0, ioaddr + DMA_INTR_ENA);
48}
49
50void dwmac_dma_start_tx(unsigned long ioaddr)
51{
52 u32 value = readl(ioaddr + DMA_CONTROL);
53 value |= DMA_CONTROL_ST;
54 writel(value, ioaddr + DMA_CONTROL);
55 return;
56}
57
58void dwmac_dma_stop_tx(unsigned long ioaddr)
59{
60 u32 value = readl(ioaddr + DMA_CONTROL);
61 value &= ~DMA_CONTROL_ST;
62 writel(value, ioaddr + DMA_CONTROL);
63 return;
64}
65
66void dwmac_dma_start_rx(unsigned long ioaddr)
67{
68 u32 value = readl(ioaddr + DMA_CONTROL);
69 value |= DMA_CONTROL_SR;
70 writel(value, ioaddr + DMA_CONTROL);
71
72 return;
73}
74
75void dwmac_dma_stop_rx(unsigned long ioaddr)
76{
77 u32 value = readl(ioaddr + DMA_CONTROL);
78 value &= ~DMA_CONTROL_SR;
79 writel(value, ioaddr + DMA_CONTROL);
80
81 return;
82}
83
84#ifdef DWMAC_DMA_DEBUG
85static void show_tx_process_state(unsigned int status)
86{
87 unsigned int state;
88 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
89
90 switch (state) {
91 case 0:
92 pr_info("- TX (Stopped): Reset or Stop command\n");
93 break;
94 case 1:
95 pr_info("- TX (Running):Fetching the Tx desc\n");
96 break;
97 case 2:
98 pr_info("- TX (Running): Waiting for end of tx\n");
99 break;
100 case 3:
101 pr_info("- TX (Running): Reading the data "
102 "and queuing the data into the Tx buf\n");
103 break;
104 case 6:
105 pr_info("- TX (Suspended): Tx Buff Underflow "
106 "or an unavailable Transmit descriptor\n");
107 break;
108 case 7:
109 pr_info("- TX (Running): Closing Tx descriptor\n");
110 break;
111 default:
112 break;
113 }
114 return;
115}
116
117static void show_rx_process_state(unsigned int status)
118{
119 unsigned int state;
120 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
121
122 switch (state) {
123 case 0:
124 pr_info("- RX (Stopped): Reset or Stop command\n");
125 break;
126 case 1:
127 pr_info("- RX (Running): Fetching the Rx desc\n");
128 break;
129 case 2:
130 pr_info("- RX (Running):Checking for end of pkt\n");
131 break;
132 case 3:
133 pr_info("- RX (Running): Waiting for Rx pkt\n");
134 break;
135 case 4:
136 pr_info("- RX (Suspended): Unavailable Rx buf\n");
137 break;
138 case 5:
139 pr_info("- RX (Running): Closing Rx descriptor\n");
140 break;
141 case 6:
142 pr_info("- RX(Running): Flushing the current frame"
143 " from the Rx buf\n");
144 break;
145 case 7:
146 pr_info("- RX (Running): Queuing the Rx frame"
147 " from the Rx buf into memory\n");
148 break;
149 default:
150 break;
151 }
152 return;
153}
154#endif
155
156int dwmac_dma_interrupt(unsigned long ioaddr,
157 struct stmmac_extra_stats *x)
158{
159 int ret = 0;
160 /* read the status register (CSR5) */
161 u32 intr_status = readl(ioaddr + DMA_STATUS);
162
163 DBG(INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
164#ifdef DWMAC_DMA_DEBUG
165 /* It displays the DMA process states (CSR5 register) */
166 show_tx_process_state(intr_status);
167 show_rx_process_state(intr_status);
168#endif
169 /* ABNORMAL interrupts */
170 if (unlikely(intr_status & DMA_STATUS_AIS)) {
171 DBG(INFO, "CSR5[15] DMA ABNORMAL IRQ: ");
172 if (unlikely(intr_status & DMA_STATUS_UNF)) {
173 DBG(INFO, "transmit underflow\n");
174 ret = tx_hard_error_bump_tc;
175 x->tx_undeflow_irq++;
176 }
177 if (unlikely(intr_status & DMA_STATUS_TJT)) {
178 DBG(INFO, "transmit jabber\n");
179 x->tx_jabber_irq++;
180 }
181 if (unlikely(intr_status & DMA_STATUS_OVF)) {
182 DBG(INFO, "recv overflow\n");
183 x->rx_overflow_irq++;
184 }
185 if (unlikely(intr_status & DMA_STATUS_RU)) {
186 DBG(INFO, "receive buffer unavailable\n");
187 x->rx_buf_unav_irq++;
188 }
189 if (unlikely(intr_status & DMA_STATUS_RPS)) {
190 DBG(INFO, "receive process stopped\n");
191 x->rx_process_stopped_irq++;
192 }
193 if (unlikely(intr_status & DMA_STATUS_RWT)) {
194 DBG(INFO, "receive watchdog\n");
195 x->rx_watchdog_irq++;
196 }
197 if (unlikely(intr_status & DMA_STATUS_ETI)) {
198 DBG(INFO, "transmit early interrupt\n");
199 x->tx_early_irq++;
200 }
201 if (unlikely(intr_status & DMA_STATUS_TPS)) {
202 DBG(INFO, "transmit process stopped\n");
203 x->tx_process_stopped_irq++;
204 ret = tx_hard_error;
205 }
206 if (unlikely(intr_status & DMA_STATUS_FBI)) {
207 DBG(INFO, "fatal bus error\n");
208 x->fatal_bus_error_irq++;
209 ret = tx_hard_error;
210 }
211 }
212 /* TX/RX NORMAL interrupts */
213 if (intr_status & DMA_STATUS_NIS) {
214 x->normal_irq_n++;
215 if (likely((intr_status & DMA_STATUS_RI) ||
216 (intr_status & (DMA_STATUS_TI))))
217 ret = handle_tx_rx;
218 }
219 /* Optional hardware blocks, interrupts should be disabled */
220 if (unlikely(intr_status &
221 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
222 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
223 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
224 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
225
226 DBG(INFO, "\n\n");
227 return ret;
228}
229
230
231void stmmac_set_mac_addr(unsigned long ioaddr, u8 addr[6],
232 unsigned int high, unsigned int low)
233{
234 unsigned long data;
235
236 data = (addr[5] << 8) | addr[4];
237 writel(data, ioaddr + high);
238 data = (addr[3] << 24) | (addr[2] << 16) | (addr[1] << 8) | addr[0];
239 writel(data, ioaddr + low);
240
241 return;
242}
243
244void stmmac_get_mac_addr(unsigned long ioaddr, unsigned char *addr,
245 unsigned int high, unsigned int low)
246{
247 unsigned int hi_addr, lo_addr;
248
249 /* Read the MAC address from the hardware */
250 hi_addr = readl(ioaddr + high);
251 lo_addr = readl(ioaddr + low);
252
253 /* Extract the MAC address from the high and low words */
254 addr[0] = lo_addr & 0xff;
255 addr[1] = (lo_addr >> 8) & 0xff;
256 addr[2] = (lo_addr >> 16) & 0xff;
257 addr[3] = (lo_addr >> 24) & 0xff;
258 addr[4] = hi_addr & 0xff;
259 addr[5] = (hi_addr >> 8) & 0xff;
260
261 return;
262}
263
diff --git a/drivers/net/stmmac/stmmac.h b/drivers/net/stmmac/stmmac.h
index 6d2eae3040e5..ba35e6943cf4 100644
--- a/drivers/net/stmmac/stmmac.h
+++ b/drivers/net/stmmac/stmmac.h
@@ -20,7 +20,8 @@
20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 20 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
21*******************************************************************************/ 21*******************************************************************************/
22 22
23#define DRV_MODULE_VERSION "Oct_09" 23#define DRV_MODULE_VERSION "Jan_2010"
24#include <linux/stmmac.h>
24 25
25#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE) 26#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
26#define STMMAC_VLAN_TAG_USED 27#define STMMAC_VLAN_TAG_USED
@@ -57,7 +58,7 @@ struct stmmac_priv {
57 int rx_csum; 58 int rx_csum;
58 unsigned int dma_buf_sz; 59 unsigned int dma_buf_sz;
59 struct device *device; 60 struct device *device;
60 struct mac_device_info *mac_type; 61 struct mac_device_info *hw;
61 62
62 struct stmmac_extra_stats xstats; 63 struct stmmac_extra_stats xstats;
63 struct napi_struct napi; 64 struct napi_struct napi;
@@ -69,6 +70,7 @@ struct stmmac_priv {
69 int phy_mask; 70 int phy_mask;
70 int (*phy_reset) (void *priv); 71 int (*phy_reset) (void *priv);
71 void (*fix_mac_speed) (void *priv, unsigned int speed); 72 void (*fix_mac_speed) (void *priv, unsigned int speed);
73 void (*bus_setup)(unsigned long ioaddr);
72 void *bsp_priv; 74 void *bsp_priv;
73 75
74 int phy_irq; 76 int phy_irq;
@@ -93,6 +95,28 @@ struct stmmac_priv {
93#endif 95#endif
94}; 96};
95 97
98#ifdef CONFIG_STM_DRIVERS
99#include <linux/stm/pad.h>
100static inline int stmmac_claim_resource(struct platform_device *pdev)
101{
102 int ret = 0;
103 struct plat_stmmacenet_data *plat_dat = pdev->dev.platform_data;
104
105 /* Pad routing setup */
106 if (IS_ERR(devm_stm_pad_claim(&pdev->dev, plat_dat->pad_config,
107 dev_name(&pdev->dev)))) {
108 printk(KERN_ERR "%s: Failed to request pads!\n", __func__);
109 ret = -ENODEV;
110 }
111 return ret;
112}
113#else
114static inline int stmmac_claim_resource(struct platform_device *pdev)
115{
116 return 0;
117}
118#endif
119
96extern int stmmac_mdio_unregister(struct net_device *ndev); 120extern int stmmac_mdio_unregister(struct net_device *ndev);
97extern int stmmac_mdio_register(struct net_device *ndev); 121extern int stmmac_mdio_register(struct net_device *ndev);
98extern void stmmac_set_ethtool_ops(struct net_device *netdev); 122extern void stmmac_set_ethtool_ops(struct net_device *netdev);
diff --git a/drivers/net/stmmac/stmmac_ethtool.c b/drivers/net/stmmac/stmmac_ethtool.c
index 694ebe6a0758..c021eaa3ca69 100644
--- a/drivers/net/stmmac/stmmac_ethtool.c
+++ b/drivers/net/stmmac/stmmac_ethtool.c
@@ -28,6 +28,7 @@
28#include <linux/phy.h> 28#include <linux/phy.h>
29 29
30#include "stmmac.h" 30#include "stmmac.h"
31#include "dwmac_dma.h"
31 32
32#define REG_SPACE_SIZE 0x1054 33#define REG_SPACE_SIZE 0x1054
33#define MAC100_ETHTOOL_NAME "st_mac100" 34#define MAC100_ETHTOOL_NAME "st_mac100"
@@ -61,7 +62,7 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
61 STMMAC_STAT(rx_toolong), 62 STMMAC_STAT(rx_toolong),
62 STMMAC_STAT(rx_collision), 63 STMMAC_STAT(rx_collision),
63 STMMAC_STAT(rx_crc), 64 STMMAC_STAT(rx_crc),
64 STMMAC_STAT(rx_lenght), 65 STMMAC_STAT(rx_length),
65 STMMAC_STAT(rx_mii), 66 STMMAC_STAT(rx_mii),
66 STMMAC_STAT(rx_multicast), 67 STMMAC_STAT(rx_multicast),
67 STMMAC_STAT(rx_gmac_overflow), 68 STMMAC_STAT(rx_gmac_overflow),
@@ -268,8 +269,8 @@ stmmac_set_pauseparam(struct net_device *netdev,
268 } 269 }
269 } else { 270 } else {
270 unsigned long ioaddr = netdev->base_addr; 271 unsigned long ioaddr = netdev->base_addr;
271 priv->mac_type->ops->flow_ctrl(ioaddr, phy->duplex, 272 priv->hw->mac->flow_ctrl(ioaddr, phy->duplex,
272 priv->flow_ctrl, priv->pause); 273 priv->flow_ctrl, priv->pause);
273 } 274 }
274 spin_unlock(&priv->lock); 275 spin_unlock(&priv->lock);
275 return ret; 276 return ret;
@@ -283,8 +284,8 @@ static void stmmac_get_ethtool_stats(struct net_device *dev,
283 int i; 284 int i;
284 285
285 /* Update HW stats if supported */ 286 /* Update HW stats if supported */
286 priv->mac_type->ops->dma_diagnostic_fr(&dev->stats, &priv->xstats, 287 priv->hw->dma->dma_diagnostic_fr(&dev->stats, (void *) &priv->xstats,
287 ioaddr); 288 ioaddr);
288 289
289 for (i = 0; i < STMMAC_STATS_LEN; i++) { 290 for (i = 0; i < STMMAC_STATS_LEN; i++) {
290 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset; 291 char *p = (char *)priv + stmmac_gstrings_stats[i].stat_offset;
diff --git a/drivers/net/stmmac/stmmac_main.c b/drivers/net/stmmac/stmmac_main.c
index 508fba8fa07f..a6733612d64a 100644
--- a/drivers/net/stmmac/stmmac_main.c
+++ b/drivers/net/stmmac/stmmac_main.c
@@ -32,7 +32,6 @@
32#include <linux/init.h> 32#include <linux/init.h>
33#include <linux/kernel.h> 33#include <linux/kernel.h>
34#include <linux/interrupt.h> 34#include <linux/interrupt.h>
35#include <linux/netdevice.h>
36#include <linux/etherdevice.h> 35#include <linux/etherdevice.h>
37#include <linux/platform_device.h> 36#include <linux/platform_device.h>
38#include <linux/ip.h> 37#include <linux/ip.h>
@@ -45,7 +44,6 @@
45#include <linux/phy.h> 44#include <linux/phy.h>
46#include <linux/if_vlan.h> 45#include <linux/if_vlan.h>
47#include <linux/dma-mapping.h> 46#include <linux/dma-mapping.h>
48#include <linux/stm/soc.h>
49#include "stmmac.h" 47#include "stmmac.h"
50 48
51#define STMMAC_RESOURCE_NAME "stmmaceth" 49#define STMMAC_RESOURCE_NAME "stmmaceth"
@@ -226,41 +224,38 @@ static void stmmac_adjust_link(struct net_device *dev)
226 if (phydev->duplex != priv->oldduplex) { 224 if (phydev->duplex != priv->oldduplex) {
227 new_state = 1; 225 new_state = 1;
228 if (!(phydev->duplex)) 226 if (!(phydev->duplex))
229 ctrl &= ~priv->mac_type->hw.link.duplex; 227 ctrl &= ~priv->hw->link.duplex;
230 else 228 else
231 ctrl |= priv->mac_type->hw.link.duplex; 229 ctrl |= priv->hw->link.duplex;
232 priv->oldduplex = phydev->duplex; 230 priv->oldduplex = phydev->duplex;
233 } 231 }
234 /* Flow Control operation */ 232 /* Flow Control operation */
235 if (phydev->pause) 233 if (phydev->pause)
236 priv->mac_type->ops->flow_ctrl(ioaddr, phydev->duplex, 234 priv->hw->mac->flow_ctrl(ioaddr, phydev->duplex,
237 fc, pause_time); 235 fc, pause_time);
238 236
239 if (phydev->speed != priv->speed) { 237 if (phydev->speed != priv->speed) {
240 new_state = 1; 238 new_state = 1;
241 switch (phydev->speed) { 239 switch (phydev->speed) {
242 case 1000: 240 case 1000:
243 if (likely(priv->is_gmac)) 241 if (likely(priv->is_gmac))
244 ctrl &= ~priv->mac_type->hw.link.port; 242 ctrl &= ~priv->hw->link.port;
245 break; 243 break;
246 case 100: 244 case 100:
247 case 10: 245 case 10:
248 if (priv->is_gmac) { 246 if (priv->is_gmac) {
249 ctrl |= priv->mac_type->hw.link.port; 247 ctrl |= priv->hw->link.port;
250 if (phydev->speed == SPEED_100) { 248 if (phydev->speed == SPEED_100) {
251 ctrl |= 249 ctrl |= priv->hw->link.speed;
252 priv->mac_type->hw.link.
253 speed;
254 } else { 250 } else {
255 ctrl &= 251 ctrl &= ~(priv->hw->link.speed);
256 ~(priv->mac_type->hw.
257 link.speed);
258 } 252 }
259 } else { 253 } else {
260 ctrl &= ~priv->mac_type->hw.link.port; 254 ctrl &= ~priv->hw->link.port;
261 } 255 }
262 priv->fix_mac_speed(priv->bsp_priv, 256 if (likely(priv->fix_mac_speed))
263 phydev->speed); 257 priv->fix_mac_speed(priv->bsp_priv,
258 phydev->speed);
264 break; 259 break;
265 default: 260 default:
266 if (netif_msg_link(priv)) 261 if (netif_msg_link(priv))
@@ -305,8 +300,8 @@ static int stmmac_init_phy(struct net_device *dev)
305{ 300{
306 struct stmmac_priv *priv = netdev_priv(dev); 301 struct stmmac_priv *priv = netdev_priv(dev);
307 struct phy_device *phydev; 302 struct phy_device *phydev;
308 char phy_id[BUS_ID_SIZE]; /* PHY to connect */ 303 char phy_id[MII_BUS_ID_SIZE + 3];
309 char bus_id[BUS_ID_SIZE]; 304 char bus_id[MII_BUS_ID_SIZE];
310 305
311 priv->oldlink = 0; 306 priv->oldlink = 0;
312 priv->speed = 0; 307 priv->speed = 0;
@@ -318,7 +313,8 @@ static int stmmac_init_phy(struct net_device *dev)
318 } 313 }
319 314
320 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id); 315 snprintf(bus_id, MII_BUS_ID_SIZE, "%x", priv->bus_id);
321 snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, bus_id, priv->phy_addr); 316 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id,
317 priv->phy_addr);
322 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); 318 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id);
323 319
324 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, 320 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0,
@@ -508,8 +504,8 @@ static void init_dma_desc_rings(struct net_device *dev)
508 priv->cur_tx = 0; 504 priv->cur_tx = 0;
509 505
510 /* Clear the Rx/Tx descriptors */ 506 /* Clear the Rx/Tx descriptors */
511 priv->mac_type->ops->init_rx_desc(priv->dma_rx, rxsize, dis_ic); 507 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic);
512 priv->mac_type->ops->init_tx_desc(priv->dma_tx, txsize); 508 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize);
513 509
514 if (netif_msg_hw(priv)) { 510 if (netif_msg_hw(priv)) {
515 pr_info("RX descriptor ring:\n"); 511 pr_info("RX descriptor ring:\n");
@@ -544,8 +540,8 @@ static void dma_free_tx_skbufs(struct stmmac_priv *priv)
544 struct dma_desc *p = priv->dma_tx + i; 540 struct dma_desc *p = priv->dma_tx + i;
545 if (p->des2) 541 if (p->des2)
546 dma_unmap_single(priv->device, p->des2, 542 dma_unmap_single(priv->device, p->des2,
547 priv->mac_type->ops->get_tx_len(p), 543 priv->hw->desc->get_tx_len(p),
548 DMA_TO_DEVICE); 544 DMA_TO_DEVICE);
549 dev_kfree_skb_any(priv->tx_skbuff[i]); 545 dev_kfree_skb_any(priv->tx_skbuff[i]);
550 priv->tx_skbuff[i] = NULL; 546 priv->tx_skbuff[i] = NULL;
551 } 547 }
@@ -575,50 +571,6 @@ static void free_dma_desc_resources(struct stmmac_priv *priv)
575} 571}
576 572
577/** 573/**
578 * stmmac_dma_start_tx
579 * @ioaddr: device I/O address
580 * Description: this function starts the DMA tx process.
581 */
582static void stmmac_dma_start_tx(unsigned long ioaddr)
583{
584 u32 value = readl(ioaddr + DMA_CONTROL);
585 value |= DMA_CONTROL_ST;
586 writel(value, ioaddr + DMA_CONTROL);
587 return;
588}
589
590static void stmmac_dma_stop_tx(unsigned long ioaddr)
591{
592 u32 value = readl(ioaddr + DMA_CONTROL);
593 value &= ~DMA_CONTROL_ST;
594 writel(value, ioaddr + DMA_CONTROL);
595 return;
596}
597
598/**
599 * stmmac_dma_start_rx
600 * @ioaddr: device I/O address
601 * Description: this function starts the DMA rx process.
602 */
603static void stmmac_dma_start_rx(unsigned long ioaddr)
604{
605 u32 value = readl(ioaddr + DMA_CONTROL);
606 value |= DMA_CONTROL_SR;
607 writel(value, ioaddr + DMA_CONTROL);
608
609 return;
610}
611
612static void stmmac_dma_stop_rx(unsigned long ioaddr)
613{
614 u32 value = readl(ioaddr + DMA_CONTROL);
615 value &= ~DMA_CONTROL_SR;
616 writel(value, ioaddr + DMA_CONTROL);
617
618 return;
619}
620
621/**
622 * stmmac_dma_operation_mode - HW DMA operation mode 574 * stmmac_dma_operation_mode - HW DMA operation mode
623 * @priv : pointer to the private device structure. 575 * @priv : pointer to the private device structure.
624 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 576 * Description: it sets the DMA operation mode: tx/rx DMA thresholds
@@ -629,18 +581,18 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
629{ 581{
630 if (!priv->is_gmac) { 582 if (!priv->is_gmac) {
631 /* MAC 10/100 */ 583 /* MAC 10/100 */
632 priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc, 0); 584 priv->hw->dma->dma_mode(priv->dev->base_addr, tc, 0);
633 priv->tx_coe = NO_HW_CSUM; 585 priv->tx_coe = NO_HW_CSUM;
634 } else { 586 } else {
635 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) { 587 if ((priv->dev->mtu <= ETH_DATA_LEN) && (tx_coe)) {
636 priv->mac_type->ops->dma_mode(priv->dev->base_addr, 588 priv->hw->dma->dma_mode(priv->dev->base_addr,
637 SF_DMA_MODE, SF_DMA_MODE); 589 SF_DMA_MODE, SF_DMA_MODE);
638 tc = SF_DMA_MODE; 590 tc = SF_DMA_MODE;
639 priv->tx_coe = HW_CSUM; 591 priv->tx_coe = HW_CSUM;
640 } else { 592 } else {
641 /* Checksum computation is performed in software. */ 593 /* Checksum computation is performed in software. */
642 priv->mac_type->ops->dma_mode(priv->dev->base_addr, tc, 594 priv->hw->dma->dma_mode(priv->dev->base_addr, tc,
643 SF_DMA_MODE); 595 SF_DMA_MODE);
644 priv->tx_coe = NO_HW_CSUM; 596 priv->tx_coe = NO_HW_CSUM;
645 } 597 }
646 } 598 }
@@ -649,88 +601,6 @@ static void stmmac_dma_operation_mode(struct stmmac_priv *priv)
649 return; 601 return;
650} 602}
651 603
652#ifdef STMMAC_DEBUG
653/**
654 * show_tx_process_state
655 * @status: tx descriptor status field
656 * Description: it shows the Transmit Process State for CSR5[22:20]
657 */
658static void show_tx_process_state(unsigned int status)
659{
660 unsigned int state;
661 state = (status & DMA_STATUS_TS_MASK) >> DMA_STATUS_TS_SHIFT;
662
663 switch (state) {
664 case 0:
665 pr_info("- TX (Stopped): Reset or Stop command\n");
666 break;
667 case 1:
668 pr_info("- TX (Running):Fetching the Tx desc\n");
669 break;
670 case 2:
671 pr_info("- TX (Running): Waiting for end of tx\n");
672 break;
673 case 3:
674 pr_info("- TX (Running): Reading the data "
675 "and queuing the data into the Tx buf\n");
676 break;
677 case 6:
678 pr_info("- TX (Suspended): Tx Buff Underflow "
679 "or an unavailable Transmit descriptor\n");
680 break;
681 case 7:
682 pr_info("- TX (Running): Closing Tx descriptor\n");
683 break;
684 default:
685 break;
686 }
687 return;
688}
689
690/**
691 * show_rx_process_state
692 * @status: rx descriptor status field
693 * Description: it shows the Receive Process State for CSR5[19:17]
694 */
695static void show_rx_process_state(unsigned int status)
696{
697 unsigned int state;
698 state = (status & DMA_STATUS_RS_MASK) >> DMA_STATUS_RS_SHIFT;
699
700 switch (state) {
701 case 0:
702 pr_info("- RX (Stopped): Reset or Stop command\n");
703 break;
704 case 1:
705 pr_info("- RX (Running): Fetching the Rx desc\n");
706 break;
707 case 2:
708 pr_info("- RX (Running):Checking for end of pkt\n");
709 break;
710 case 3:
711 pr_info("- RX (Running): Waiting for Rx pkt\n");
712 break;
713 case 4:
714 pr_info("- RX (Suspended): Unavailable Rx buf\n");
715 break;
716 case 5:
717 pr_info("- RX (Running): Closing Rx descriptor\n");
718 break;
719 case 6:
720 pr_info("- RX(Running): Flushing the current frame"
721 " from the Rx buf\n");
722 break;
723 case 7:
724 pr_info("- RX (Running): Queuing the Rx frame"
725 " from the Rx buf into memory\n");
726 break;
727 default:
728 break;
729 }
730 return;
731}
732#endif
733
734/** 604/**
735 * stmmac_tx: 605 * stmmac_tx:
736 * @priv: private driver structure 606 * @priv: private driver structure
@@ -748,16 +618,16 @@ static void stmmac_tx(struct stmmac_priv *priv)
748 struct dma_desc *p = priv->dma_tx + entry; 618 struct dma_desc *p = priv->dma_tx + entry;
749 619
750 /* Check if the descriptor is owned by the DMA. */ 620 /* Check if the descriptor is owned by the DMA. */
751 if (priv->mac_type->ops->get_tx_owner(p)) 621 if (priv->hw->desc->get_tx_owner(p))
752 break; 622 break;
753 623
754 /* Verify tx error by looking at the last segment */ 624 /* Verify tx error by looking at the last segment */
755 last = priv->mac_type->ops->get_tx_ls(p); 625 last = priv->hw->desc->get_tx_ls(p);
756 if (likely(last)) { 626 if (likely(last)) {
757 int tx_error = 627 int tx_error =
758 priv->mac_type->ops->tx_status(&priv->dev->stats, 628 priv->hw->desc->tx_status(&priv->dev->stats,
759 &priv->xstats, 629 &priv->xstats, p,
760 p, ioaddr); 630 ioaddr);
761 if (likely(tx_error == 0)) { 631 if (likely(tx_error == 0)) {
762 priv->dev->stats.tx_packets++; 632 priv->dev->stats.tx_packets++;
763 priv->xstats.tx_pkt_n++; 633 priv->xstats.tx_pkt_n++;
@@ -769,7 +639,7 @@ static void stmmac_tx(struct stmmac_priv *priv)
769 639
770 if (likely(p->des2)) 640 if (likely(p->des2))
771 dma_unmap_single(priv->device, p->des2, 641 dma_unmap_single(priv->device, p->des2,
772 priv->mac_type->ops->get_tx_len(p), 642 priv->hw->desc->get_tx_len(p),
773 DMA_TO_DEVICE); 643 DMA_TO_DEVICE);
774 if (unlikely(p->des3)) 644 if (unlikely(p->des3))
775 p->des3 = 0; 645 p->des3 = 0;
@@ -790,7 +660,7 @@ static void stmmac_tx(struct stmmac_priv *priv)
790 priv->tx_skbuff[entry] = NULL; 660 priv->tx_skbuff[entry] = NULL;
791 } 661 }
792 662
793 priv->mac_type->ops->release_tx_desc(p); 663 priv->hw->desc->release_tx_desc(p);
794 664
795 entry = (++priv->dirty_tx) % txsize; 665 entry = (++priv->dirty_tx) % txsize;
796 } 666 }
@@ -814,7 +684,7 @@ static inline void stmmac_enable_irq(struct stmmac_priv *priv)
814 priv->tm->timer_start(tmrate); 684 priv->tm->timer_start(tmrate);
815 else 685 else
816#endif 686#endif
817 writel(DMA_INTR_DEFAULT_MASK, priv->dev->base_addr + DMA_INTR_ENA); 687 priv->hw->dma->enable_dma_irq(priv->dev->base_addr);
818} 688}
819 689
820static inline void stmmac_disable_irq(struct stmmac_priv *priv) 690static inline void stmmac_disable_irq(struct stmmac_priv *priv)
@@ -824,7 +694,7 @@ static inline void stmmac_disable_irq(struct stmmac_priv *priv)
824 priv->tm->timer_stop(); 694 priv->tm->timer_stop();
825 else 695 else
826#endif 696#endif
827 writel(0, priv->dev->base_addr + DMA_INTR_ENA); 697 priv->hw->dma->disable_dma_irq(priv->dev->base_addr);
828} 698}
829 699
830static int stmmac_has_work(struct stmmac_priv *priv) 700static int stmmac_has_work(struct stmmac_priv *priv)
@@ -832,7 +702,7 @@ static int stmmac_has_work(struct stmmac_priv *priv)
832 unsigned int has_work = 0; 702 unsigned int has_work = 0;
833 int rxret, tx_work = 0; 703 int rxret, tx_work = 0;
834 704
835 rxret = priv->mac_type->ops->get_rx_owner(priv->dma_rx + 705 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx +
836 (priv->cur_rx % priv->dma_rx_size)); 706 (priv->cur_rx % priv->dma_rx_size));
837 707
838 if (priv->dirty_tx != priv->cur_tx) 708 if (priv->dirty_tx != priv->cur_tx)
@@ -883,12 +753,12 @@ static void stmmac_tx_err(struct stmmac_priv *priv)
883{ 753{
884 netif_stop_queue(priv->dev); 754 netif_stop_queue(priv->dev);
885 755
886 stmmac_dma_stop_tx(priv->dev->base_addr); 756 priv->hw->dma->stop_tx(priv->dev->base_addr);
887 dma_free_tx_skbufs(priv); 757 dma_free_tx_skbufs(priv);
888 priv->mac_type->ops->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 758 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
889 priv->dirty_tx = 0; 759 priv->dirty_tx = 0;
890 priv->cur_tx = 0; 760 priv->cur_tx = 0;
891 stmmac_dma_start_tx(priv->dev->base_addr); 761 priv->hw->dma->start_tx(priv->dev->base_addr);
892 762
893 priv->dev->stats.tx_errors++; 763 priv->dev->stats.tx_errors++;
894 netif_wake_queue(priv->dev); 764 netif_wake_queue(priv->dev);
@@ -896,95 +766,27 @@ static void stmmac_tx_err(struct stmmac_priv *priv)
896 return; 766 return;
897} 767}
898 768
899/**
900 * stmmac_dma_interrupt - Interrupt handler for the driver
901 * @dev: net device structure
902 * Description: Interrupt handler for the driver (DMA).
903 */
904static void stmmac_dma_interrupt(struct net_device *dev)
905{
906 unsigned long ioaddr = dev->base_addr;
907 struct stmmac_priv *priv = netdev_priv(dev);
908 /* read the status register (CSR5) */
909 u32 intr_status = readl(ioaddr + DMA_STATUS);
910
911 DBG(intr, INFO, "%s: [CSR5: 0x%08x]\n", __func__, intr_status);
912 769
913#ifdef STMMAC_DEBUG 770static void stmmac_dma_interrupt(struct stmmac_priv *priv)
914 /* It displays the DMA transmit process state (CSR5 register) */ 771{
915 if (netif_msg_tx_done(priv)) 772 unsigned long ioaddr = priv->dev->base_addr;
916 show_tx_process_state(intr_status); 773 int status;
917 if (netif_msg_rx_status(priv)) 774
918 show_rx_process_state(intr_status); 775 status = priv->hw->dma->dma_interrupt(priv->dev->base_addr,
919#endif 776 &priv->xstats);
920 /* ABNORMAL interrupts */ 777 if (likely(status == handle_tx_rx))
921 if (unlikely(intr_status & DMA_STATUS_AIS)) { 778 _stmmac_schedule(priv);
922 DBG(intr, INFO, "CSR5[15] DMA ABNORMAL IRQ: "); 779
923 if (unlikely(intr_status & DMA_STATUS_UNF)) { 780 else if (unlikely(status == tx_hard_error_bump_tc)) {
924 DBG(intr, INFO, "transmit underflow\n"); 781 /* Try to bump up the dma threshold on this failure */
925 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 782 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) {
926 /* Try to bump up the threshold */ 783 tc += 64;
927 tc += 64; 784 priv->hw->dma->dma_mode(ioaddr, tc, SF_DMA_MODE);
928 priv->mac_type->ops->dma_mode(ioaddr, tc, 785 priv->xstats.threshold = tc;
929 SF_DMA_MODE);
930 priv->xstats.threshold = tc;
931 }
932 stmmac_tx_err(priv);
933 priv->xstats.tx_undeflow_irq++;
934 }
935 if (unlikely(intr_status & DMA_STATUS_TJT)) {
936 DBG(intr, INFO, "transmit jabber\n");
937 priv->xstats.tx_jabber_irq++;
938 }
939 if (unlikely(intr_status & DMA_STATUS_OVF)) {
940 DBG(intr, INFO, "recv overflow\n");
941 priv->xstats.rx_overflow_irq++;
942 }
943 if (unlikely(intr_status & DMA_STATUS_RU)) {
944 DBG(intr, INFO, "receive buffer unavailable\n");
945 priv->xstats.rx_buf_unav_irq++;
946 }
947 if (unlikely(intr_status & DMA_STATUS_RPS)) {
948 DBG(intr, INFO, "receive process stopped\n");
949 priv->xstats.rx_process_stopped_irq++;
950 }
951 if (unlikely(intr_status & DMA_STATUS_RWT)) {
952 DBG(intr, INFO, "receive watchdog\n");
953 priv->xstats.rx_watchdog_irq++;
954 }
955 if (unlikely(intr_status & DMA_STATUS_ETI)) {
956 DBG(intr, INFO, "transmit early interrupt\n");
957 priv->xstats.tx_early_irq++;
958 }
959 if (unlikely(intr_status & DMA_STATUS_TPS)) {
960 DBG(intr, INFO, "transmit process stopped\n");
961 priv->xstats.tx_process_stopped_irq++;
962 stmmac_tx_err(priv);
963 }
964 if (unlikely(intr_status & DMA_STATUS_FBI)) {
965 DBG(intr, INFO, "fatal bus error\n");
966 priv->xstats.fatal_bus_error_irq++;
967 stmmac_tx_err(priv);
968 } 786 }
969 } 787 stmmac_tx_err(priv);
970 788 } else if (unlikely(status == tx_hard_error))
971 /* TX/RX NORMAL interrupts */ 789 stmmac_tx_err(priv);
972 if (intr_status & DMA_STATUS_NIS) {
973 priv->xstats.normal_irq_n++;
974 if (likely((intr_status & DMA_STATUS_RI) ||
975 (intr_status & (DMA_STATUS_TI))))
976 _stmmac_schedule(priv);
977 }
978
979 /* Optional hardware blocks, interrupts should be disabled */
980 if (unlikely(intr_status &
981 (DMA_STATUS_GPI | DMA_STATUS_GMI | DMA_STATUS_GLI)))
982 pr_info("%s: unexpected status %08x\n", __func__, intr_status);
983
984 /* Clear the interrupt by writing a logic 1 to the CSR5[15-0] */
985 writel((intr_status & 0x1ffff), ioaddr + DMA_STATUS);
986
987 DBG(intr, INFO, "\n\n");
988 790
989 return; 791 return;
990} 792}
@@ -1058,17 +860,20 @@ static int stmmac_open(struct net_device *dev)
1058 init_dma_desc_rings(dev); 860 init_dma_desc_rings(dev);
1059 861
1060 /* DMA initialization and SW reset */ 862 /* DMA initialization and SW reset */
1061 if (unlikely(priv->mac_type->ops->dma_init(ioaddr, 863 if (unlikely(priv->hw->dma->init(ioaddr, priv->pbl, priv->dma_tx_phy,
1062 priv->pbl, priv->dma_tx_phy, priv->dma_rx_phy) < 0)) { 864 priv->dma_rx_phy) < 0)) {
1063 865
1064 pr_err("%s: DMA initialization failed\n", __func__); 866 pr_err("%s: DMA initialization failed\n", __func__);
1065 return -1; 867 return -1;
1066 } 868 }
1067 869
1068 /* Copy the MAC addr into the HW */ 870 /* Copy the MAC addr into the HW */
1069 priv->mac_type->ops->set_umac_addr(ioaddr, dev->dev_addr, 0); 871 priv->hw->mac->set_umac_addr(ioaddr, dev->dev_addr, 0);
872 /* If required, perform hw setup of the bus. */
873 if (priv->bus_setup)
874 priv->bus_setup(ioaddr);
1070 /* Initialize the MAC Core */ 875 /* Initialize the MAC Core */
1071 priv->mac_type->ops->core_init(ioaddr); 876 priv->hw->mac->core_init(ioaddr);
1072 877
1073 priv->shutdown = 0; 878 priv->shutdown = 0;
1074 879
@@ -1089,16 +894,16 @@ static int stmmac_open(struct net_device *dev)
1089 894
1090 /* Start the ball rolling... */ 895 /* Start the ball rolling... */
1091 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); 896 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name);
1092 stmmac_dma_start_tx(ioaddr); 897 priv->hw->dma->start_tx(ioaddr);
1093 stmmac_dma_start_rx(ioaddr); 898 priv->hw->dma->start_rx(ioaddr);
1094 899
1095#ifdef CONFIG_STMMAC_TIMER 900#ifdef CONFIG_STMMAC_TIMER
1096 priv->tm->timer_start(tmrate); 901 priv->tm->timer_start(tmrate);
1097#endif 902#endif
1098 /* Dump DMA/MAC registers */ 903 /* Dump DMA/MAC registers */
1099 if (netif_msg_hw(priv)) { 904 if (netif_msg_hw(priv)) {
1100 priv->mac_type->ops->dump_mac_regs(ioaddr); 905 priv->hw->mac->dump_regs(ioaddr);
1101 priv->mac_type->ops->dump_dma_regs(ioaddr); 906 priv->hw->dma->dump_regs(ioaddr);
1102 } 907 }
1103 908
1104 if (priv->phydev) 909 if (priv->phydev)
@@ -1142,8 +947,8 @@ static int stmmac_release(struct net_device *dev)
1142 free_irq(dev->irq, dev); 947 free_irq(dev->irq, dev);
1143 948
1144 /* Stop TX/RX DMA and clear the descriptors */ 949 /* Stop TX/RX DMA and clear the descriptors */
1145 stmmac_dma_stop_tx(dev->base_addr); 950 priv->hw->dma->stop_tx(dev->base_addr);
1146 stmmac_dma_stop_rx(dev->base_addr); 951 priv->hw->dma->stop_rx(dev->base_addr);
1147 952
1148 /* Release and free the Rx/Tx resources */ 953 /* Release and free the Rx/Tx resources */
1149 free_dma_desc_resources(priv); 954 free_dma_desc_resources(priv);
@@ -1214,8 +1019,8 @@ static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1214 desc->des2 = dma_map_single(priv->device, skb->data, 1019 desc->des2 = dma_map_single(priv->device, skb->data,
1215 BUF_SIZE_8KiB, DMA_TO_DEVICE); 1020 BUF_SIZE_8KiB, DMA_TO_DEVICE);
1216 desc->des3 = desc->des2 + BUF_SIZE_4KiB; 1021 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1217 priv->mac_type->ops->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB, 1022 priv->hw->desc->prepare_tx_desc(desc, 1, BUF_SIZE_8KiB,
1218 csum_insertion); 1023 csum_insertion);
1219 1024
1220 entry = (++priv->cur_tx) % txsize; 1025 entry = (++priv->cur_tx) % txsize;
1221 desc = priv->dma_tx + entry; 1026 desc = priv->dma_tx + entry;
@@ -1224,16 +1029,16 @@ static unsigned int stmmac_handle_jumbo_frames(struct sk_buff *skb,
1224 skb->data + BUF_SIZE_8KiB, 1029 skb->data + BUF_SIZE_8KiB,
1225 buf2_size, DMA_TO_DEVICE); 1030 buf2_size, DMA_TO_DEVICE);
1226 desc->des3 = desc->des2 + BUF_SIZE_4KiB; 1031 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1227 priv->mac_type->ops->prepare_tx_desc(desc, 0, 1032 priv->hw->desc->prepare_tx_desc(desc, 0, buf2_size,
1228 buf2_size, csum_insertion); 1033 csum_insertion);
1229 priv->mac_type->ops->set_tx_owner(desc); 1034 priv->hw->desc->set_tx_owner(desc);
1230 priv->tx_skbuff[entry] = NULL; 1035 priv->tx_skbuff[entry] = NULL;
1231 } else { 1036 } else {
1232 desc->des2 = dma_map_single(priv->device, skb->data, 1037 desc->des2 = dma_map_single(priv->device, skb->data,
1233 nopaged_len, DMA_TO_DEVICE); 1038 nopaged_len, DMA_TO_DEVICE);
1234 desc->des3 = desc->des2 + BUF_SIZE_4KiB; 1039 desc->des3 = desc->des2 + BUF_SIZE_4KiB;
1235 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len, 1040 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1236 csum_insertion); 1041 csum_insertion);
1237 } 1042 }
1238 return entry; 1043 return entry;
1239} 1044}
@@ -1301,8 +1106,8 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1301 unsigned int nopaged_len = skb_headlen(skb); 1106 unsigned int nopaged_len = skb_headlen(skb);
1302 desc->des2 = dma_map_single(priv->device, skb->data, 1107 desc->des2 = dma_map_single(priv->device, skb->data,
1303 nopaged_len, DMA_TO_DEVICE); 1108 nopaged_len, DMA_TO_DEVICE);
1304 priv->mac_type->ops->prepare_tx_desc(desc, 1, nopaged_len, 1109 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len,
1305 csum_insertion); 1110 csum_insertion);
1306 } 1111 }
1307 1112
1308 for (i = 0; i < nfrags; i++) { 1113 for (i = 0; i < nfrags; i++) {
@@ -1317,21 +1122,20 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1317 frag->page_offset, 1122 frag->page_offset,
1318 len, DMA_TO_DEVICE); 1123 len, DMA_TO_DEVICE);
1319 priv->tx_skbuff[entry] = NULL; 1124 priv->tx_skbuff[entry] = NULL;
1320 priv->mac_type->ops->prepare_tx_desc(desc, 0, len, 1125 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion);
1321 csum_insertion); 1126 priv->hw->desc->set_tx_owner(desc);
1322 priv->mac_type->ops->set_tx_owner(desc);
1323 } 1127 }
1324 1128
1325 /* Interrupt on completition only for the latest segment */ 1129 /* Interrupt on completition only for the latest segment */
1326 priv->mac_type->ops->close_tx_desc(desc); 1130 priv->hw->desc->close_tx_desc(desc);
1327 1131
1328#ifdef CONFIG_STMMAC_TIMER 1132#ifdef CONFIG_STMMAC_TIMER
1329 /* Clean IC while using timer */ 1133 /* Clean IC while using timer */
1330 if (likely(priv->tm->enable)) 1134 if (likely(priv->tm->enable))
1331 priv->mac_type->ops->clear_tx_ic(desc); 1135 priv->hw->desc->clear_tx_ic(desc);
1332#endif 1136#endif
1333 /* To avoid raise condition */ 1137 /* To avoid raise condition */
1334 priv->mac_type->ops->set_tx_owner(first); 1138 priv->hw->desc->set_tx_owner(first);
1335 1139
1336 priv->cur_tx++; 1140 priv->cur_tx++;
1337 1141
@@ -1353,8 +1157,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
1353 1157
1354 dev->stats.tx_bytes += skb->len; 1158 dev->stats.tx_bytes += skb->len;
1355 1159
1356 /* CSR1 enables the transmit DMA to check for new descriptor */ 1160 priv->hw->dma->enable_dma_transmission(dev->base_addr);
1357 writel(1, dev->base_addr + DMA_XMT_POLL_DEMAND);
1358 1161
1359 return NETDEV_TX_OK; 1162 return NETDEV_TX_OK;
1360} 1163}
@@ -1391,7 +1194,7 @@ static inline void stmmac_rx_refill(struct stmmac_priv *priv)
1391 } 1194 }
1392 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); 1195 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry);
1393 } 1196 }
1394 priv->mac_type->ops->set_rx_owner(p + entry); 1197 priv->hw->desc->set_rx_owner(p + entry);
1395 } 1198 }
1396 return; 1199 return;
1397} 1200}
@@ -1412,7 +1215,7 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
1412 } 1215 }
1413#endif 1216#endif
1414 count = 0; 1217 count = 0;
1415 while (!priv->mac_type->ops->get_rx_owner(p)) { 1218 while (!priv->hw->desc->get_rx_owner(p)) {
1416 int status; 1219 int status;
1417 1220
1418 if (count >= limit) 1221 if (count >= limit)
@@ -1425,15 +1228,14 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
1425 prefetch(p_next); 1228 prefetch(p_next);
1426 1229
1427 /* read the status of the incoming frame */ 1230 /* read the status of the incoming frame */
1428 status = (priv->mac_type->ops->rx_status(&priv->dev->stats, 1231 status = (priv->hw->desc->rx_status(&priv->dev->stats,
1429 &priv->xstats, p)); 1232 &priv->xstats, p));
1430 if (unlikely(status == discard_frame)) 1233 if (unlikely(status == discard_frame))
1431 priv->dev->stats.rx_errors++; 1234 priv->dev->stats.rx_errors++;
1432 else { 1235 else {
1433 struct sk_buff *skb; 1236 struct sk_buff *skb;
1434 /* Length should omit the CRC */ 1237 /* Length should omit the CRC */
1435 int frame_len = 1238 int frame_len = priv->hw->desc->get_rx_frame_len(p) - 4;
1436 priv->mac_type->ops->get_rx_frame_len(p) - 4;
1437 1239
1438#ifdef STMMAC_RX_DEBUG 1240#ifdef STMMAC_RX_DEBUG
1439 if (frame_len > ETH_FRAME_LEN) 1241 if (frame_len > ETH_FRAME_LEN)
@@ -1569,7 +1371,7 @@ static void stmmac_multicast_list(struct net_device *dev)
1569 struct stmmac_priv *priv = netdev_priv(dev); 1371 struct stmmac_priv *priv = netdev_priv(dev);
1570 1372
1571 spin_lock(&priv->lock); 1373 spin_lock(&priv->lock);
1572 priv->mac_type->ops->set_filter(dev); 1374 priv->hw->mac->set_filter(dev);
1573 spin_unlock(&priv->lock); 1375 spin_unlock(&priv->lock);
1574 return; 1376 return;
1575} 1377}
@@ -1623,9 +1425,10 @@ static irqreturn_t stmmac_interrupt(int irq, void *dev_id)
1623 if (priv->is_gmac) { 1425 if (priv->is_gmac) {
1624 unsigned long ioaddr = dev->base_addr; 1426 unsigned long ioaddr = dev->base_addr;
1625 /* To handle GMAC own interrupts */ 1427 /* To handle GMAC own interrupts */
1626 priv->mac_type->ops->host_irq_status(ioaddr); 1428 priv->hw->mac->host_irq_status(ioaddr);
1627 } 1429 }
1628 stmmac_dma_interrupt(dev); 1430
1431 stmmac_dma_interrupt(priv);
1629 1432
1630 return IRQ_HANDLED; 1433 return IRQ_HANDLED;
1631} 1434}
@@ -1744,7 +1547,7 @@ static int stmmac_probe(struct net_device *dev)
1744 netif_napi_add(dev, &priv->napi, stmmac_poll, 64); 1547 netif_napi_add(dev, &priv->napi, stmmac_poll, 64);
1745 1548
1746 /* Get the MAC address */ 1549 /* Get the MAC address */
1747 priv->mac_type->ops->get_umac_addr(dev->base_addr, dev->dev_addr, 0); 1550 priv->hw->mac->get_umac_addr(dev->base_addr, dev->dev_addr, 0);
1748 1551
1749 if (!is_valid_ether_addr(dev->dev_addr)) 1552 if (!is_valid_ether_addr(dev->dev_addr))
1750 pr_warning("\tno valid MAC address;" 1553 pr_warning("\tno valid MAC address;"
@@ -1779,16 +1582,16 @@ static int stmmac_mac_device_setup(struct net_device *dev)
1779 struct mac_device_info *device; 1582 struct mac_device_info *device;
1780 1583
1781 if (priv->is_gmac) 1584 if (priv->is_gmac)
1782 device = gmac_setup(ioaddr); 1585 device = dwmac1000_setup(ioaddr);
1783 else 1586 else
1784 device = mac100_setup(ioaddr); 1587 device = dwmac100_setup(ioaddr);
1785 1588
1786 if (!device) 1589 if (!device)
1787 return -ENOMEM; 1590 return -ENOMEM;
1788 1591
1789 priv->mac_type = device; 1592 priv->hw = device;
1790 1593
1791 priv->wolenabled = priv->mac_type->hw.pmt; /* PMT supported */ 1594 priv->wolenabled = priv->hw->pmt; /* PMT supported */
1792 if (priv->wolenabled == PMT_SUPPORTED) 1595 if (priv->wolenabled == PMT_SUPPORTED)
1793 priv->wolopts = WAKE_MAGIC; /* Magic Frame */ 1596 priv->wolopts = WAKE_MAGIC; /* Magic Frame */
1794 1597
@@ -1797,8 +1600,7 @@ static int stmmac_mac_device_setup(struct net_device *dev)
1797 1600
1798static int stmmacphy_dvr_probe(struct platform_device *pdev) 1601static int stmmacphy_dvr_probe(struct platform_device *pdev)
1799{ 1602{
1800 struct plat_stmmacphy_data *plat_dat; 1603 struct plat_stmmacphy_data *plat_dat = pdev->dev.platform_data;
1801 plat_dat = (struct plat_stmmacphy_data *)((pdev->dev).platform_data);
1802 1604
1803 pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n", 1605 pr_debug("stmmacphy_dvr_probe: added phy for bus %d\n",
1804 plat_dat->bus_id); 1606 plat_dat->bus_id);
@@ -1830,9 +1632,7 @@ static struct platform_driver stmmacphy_driver = {
1830static int stmmac_associate_phy(struct device *dev, void *data) 1632static int stmmac_associate_phy(struct device *dev, void *data)
1831{ 1633{
1832 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1634 struct stmmac_priv *priv = (struct stmmac_priv *)data;
1833 struct plat_stmmacphy_data *plat_dat; 1635 struct plat_stmmacphy_data *plat_dat = dev->platform_data;
1834
1835 plat_dat = (struct plat_stmmacphy_data *)(dev->platform_data);
1836 1636
1837 DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__, 1637 DBG(probe, DEBUG, "%s: checking phy for bus %d\n", __func__,
1838 plat_dat->bus_id); 1638 plat_dat->bus_id);
@@ -1922,7 +1722,7 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
1922 priv = netdev_priv(ndev); 1722 priv = netdev_priv(ndev);
1923 priv->device = &(pdev->dev); 1723 priv->device = &(pdev->dev);
1924 priv->dev = ndev; 1724 priv->dev = ndev;
1925 plat_dat = (struct plat_stmmacenet_data *)((pdev->dev).platform_data); 1725 plat_dat = pdev->dev.platform_data;
1926 priv->bus_id = plat_dat->bus_id; 1726 priv->bus_id = plat_dat->bus_id;
1927 priv->pbl = plat_dat->pbl; /* TLI */ 1727 priv->pbl = plat_dat->pbl; /* TLI */
1928 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */ 1728 priv->is_gmac = plat_dat->has_gmac; /* GMAC is on board */
@@ -1932,6 +1732,11 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
1932 /* Set the I/O base addr */ 1732 /* Set the I/O base addr */
1933 ndev->base_addr = (unsigned long)addr; 1733 ndev->base_addr = (unsigned long)addr;
1934 1734
1735 /* Verify embedded resource for the platform */
1736 ret = stmmac_claim_resource(pdev);
1737 if (ret < 0)
1738 goto out;
1739
1935 /* MAC HW revice detection */ 1740 /* MAC HW revice detection */
1936 ret = stmmac_mac_device_setup(ndev); 1741 ret = stmmac_mac_device_setup(ndev);
1937 if (ret < 0) 1742 if (ret < 0)
@@ -1952,6 +1757,7 @@ static int stmmac_dvr_probe(struct platform_device *pdev)
1952 } 1757 }
1953 1758
1954 priv->fix_mac_speed = plat_dat->fix_mac_speed; 1759 priv->fix_mac_speed = plat_dat->fix_mac_speed;
1760 priv->bus_setup = plat_dat->bus_setup;
1955 priv->bsp_priv = plat_dat->bsp_priv; 1761 priv->bsp_priv = plat_dat->bsp_priv;
1956 1762
1957 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n" 1763 pr_info("\t%s - (dev. name: %s - id: %d, IRQ #%d\n"
@@ -1986,12 +1792,13 @@ out:
1986static int stmmac_dvr_remove(struct platform_device *pdev) 1792static int stmmac_dvr_remove(struct platform_device *pdev)
1987{ 1793{
1988 struct net_device *ndev = platform_get_drvdata(pdev); 1794 struct net_device *ndev = platform_get_drvdata(pdev);
1795 struct stmmac_priv *priv = netdev_priv(ndev);
1989 struct resource *res; 1796 struct resource *res;
1990 1797
1991 pr_info("%s:\n\tremoving driver", __func__); 1798 pr_info("%s:\n\tremoving driver", __func__);
1992 1799
1993 stmmac_dma_stop_rx(ndev->base_addr); 1800 priv->hw->dma->stop_rx(ndev->base_addr);
1994 stmmac_dma_stop_tx(ndev->base_addr); 1801 priv->hw->dma->stop_tx(ndev->base_addr);
1995 1802
1996 stmmac_mac_disable_rx(ndev->base_addr); 1803 stmmac_mac_disable_rx(ndev->base_addr);
1997 stmmac_mac_disable_tx(ndev->base_addr); 1804 stmmac_mac_disable_tx(ndev->base_addr);
@@ -2038,21 +1845,20 @@ static int stmmac_suspend(struct platform_device *pdev, pm_message_t state)
2038 napi_disable(&priv->napi); 1845 napi_disable(&priv->napi);
2039 1846
2040 /* Stop TX/RX DMA */ 1847 /* Stop TX/RX DMA */
2041 stmmac_dma_stop_tx(dev->base_addr); 1848 priv->hw->dma->stop_tx(dev->base_addr);
2042 stmmac_dma_stop_rx(dev->base_addr); 1849 priv->hw->dma->stop_rx(dev->base_addr);
2043 /* Clear the Rx/Tx descriptors */ 1850 /* Clear the Rx/Tx descriptors */
2044 priv->mac_type->ops->init_rx_desc(priv->dma_rx, 1851 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size,
2045 priv->dma_rx_size, dis_ic); 1852 dis_ic);
2046 priv->mac_type->ops->init_tx_desc(priv->dma_tx, 1853 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size);
2047 priv->dma_tx_size);
2048 1854
2049 stmmac_mac_disable_tx(dev->base_addr); 1855 stmmac_mac_disable_tx(dev->base_addr);
2050 1856
2051 if (device_may_wakeup(&(pdev->dev))) { 1857 if (device_may_wakeup(&(pdev->dev))) {
2052 /* Enable Power down mode by programming the PMT regs */ 1858 /* Enable Power down mode by programming the PMT regs */
2053 if (priv->wolenabled == PMT_SUPPORTED) 1859 if (priv->wolenabled == PMT_SUPPORTED)
2054 priv->mac_type->ops->pmt(dev->base_addr, 1860 priv->hw->mac->pmt(dev->base_addr,
2055 priv->wolopts); 1861 priv->wolopts);
2056 } else { 1862 } else {
2057 stmmac_mac_disable_rx(dev->base_addr); 1863 stmmac_mac_disable_rx(dev->base_addr);
2058 } 1864 }
@@ -2093,15 +1899,15 @@ static int stmmac_resume(struct platform_device *pdev)
2093 * from another devices (e.g. serial console). */ 1899 * from another devices (e.g. serial console). */
2094 if (device_may_wakeup(&(pdev->dev))) 1900 if (device_may_wakeup(&(pdev->dev)))
2095 if (priv->wolenabled == PMT_SUPPORTED) 1901 if (priv->wolenabled == PMT_SUPPORTED)
2096 priv->mac_type->ops->pmt(dev->base_addr, 0); 1902 priv->hw->mac->pmt(dev->base_addr, 0);
2097 1903
2098 netif_device_attach(dev); 1904 netif_device_attach(dev);
2099 1905
2100 /* Enable the MAC and DMA */ 1906 /* Enable the MAC and DMA */
2101 stmmac_mac_enable_rx(ioaddr); 1907 stmmac_mac_enable_rx(ioaddr);
2102 stmmac_mac_enable_tx(ioaddr); 1908 stmmac_mac_enable_tx(ioaddr);
2103 stmmac_dma_start_tx(ioaddr); 1909 priv->hw->dma->start_tx(ioaddr);
2104 stmmac_dma_start_rx(ioaddr); 1910 priv->hw->dma->start_rx(ioaddr);
2105 1911
2106#ifdef CONFIG_STMMAC_TIMER 1912#ifdef CONFIG_STMMAC_TIMER
2107 priv->tm->timer_start(tmrate); 1913 priv->tm->timer_start(tmrate);
diff --git a/drivers/net/stmmac/stmmac_mdio.c b/drivers/net/stmmac/stmmac_mdio.c
index 8498552a22fc..fffe1d037fe6 100644
--- a/drivers/net/stmmac/stmmac_mdio.c
+++ b/drivers/net/stmmac/stmmac_mdio.c
@@ -24,7 +24,6 @@
24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com>
25*******************************************************************************/ 25*******************************************************************************/
26 26
27#include <linux/netdevice.h>
28#include <linux/mii.h> 27#include <linux/mii.h>
29#include <linux/phy.h> 28#include <linux/phy.h>
30 29
@@ -48,8 +47,8 @@ static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg)
48 struct net_device *ndev = bus->priv; 47 struct net_device *ndev = bus->priv;
49 struct stmmac_priv *priv = netdev_priv(ndev); 48 struct stmmac_priv *priv = netdev_priv(ndev);
50 unsigned long ioaddr = ndev->base_addr; 49 unsigned long ioaddr = ndev->base_addr;
51 unsigned int mii_address = priv->mac_type->hw.mii.addr; 50 unsigned int mii_address = priv->hw->mii.addr;
52 unsigned int mii_data = priv->mac_type->hw.mii.data; 51 unsigned int mii_data = priv->hw->mii.data;
53 52
54 int data; 53 int data;
55 u16 regValue = (((phyaddr << 11) & (0x0000F800)) | 54 u16 regValue = (((phyaddr << 11) & (0x0000F800)) |
@@ -80,8 +79,8 @@ static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg,
80 struct net_device *ndev = bus->priv; 79 struct net_device *ndev = bus->priv;
81 struct stmmac_priv *priv = netdev_priv(ndev); 80 struct stmmac_priv *priv = netdev_priv(ndev);
82 unsigned long ioaddr = ndev->base_addr; 81 unsigned long ioaddr = ndev->base_addr;
83 unsigned int mii_address = priv->mac_type->hw.mii.addr; 82 unsigned int mii_address = priv->hw->mii.addr;
84 unsigned int mii_data = priv->mac_type->hw.mii.data; 83 unsigned int mii_data = priv->hw->mii.data;
85 84
86 u16 value = 85 u16 value =
87 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0))) 86 (((phyaddr << 11) & (0x0000F800)) | ((phyreg << 6) & (0x000007C0)))
@@ -112,7 +111,7 @@ static int stmmac_mdio_reset(struct mii_bus *bus)
112 struct net_device *ndev = bus->priv; 111 struct net_device *ndev = bus->priv;
113 struct stmmac_priv *priv = netdev_priv(ndev); 112 struct stmmac_priv *priv = netdev_priv(ndev);
114 unsigned long ioaddr = ndev->base_addr; 113 unsigned long ioaddr = ndev->base_addr;
115 unsigned int mii_address = priv->mac_type->hw.mii.addr; 114 unsigned int mii_address = priv->hw->mii.addr;
116 115
117 if (priv->phy_reset) { 116 if (priv->phy_reset) {
118 pr_debug("stmmac_mdio_reset: calling phy_reset\n"); 117 pr_debug("stmmac_mdio_reset: calling phy_reset\n");
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-10 10:29:55 -0400