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authorEric Miao <eric.miao@marvell.com>2008-06-24 04:14:26 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2008-07-12 16:52:41 -0400
commit38fd6c3846a5657ef6950e3c1582a866cf42888f (patch)
tree269c2cbe16f3eaeebff202ed37a359a99a1bd00a /drivers/net/smc91x.h
parent3aed74cdea09831db04bd0bdfc2f377f731c1879 (diff)
[ARM] pxa: make mainstone to use the new smc91x platform data
Signed-off-by: Eric Miao <eric.miao@marvell.com> Acked-by: Nicolas Pitre <nico@cam.org> Acked-by: Jeff Garzik <jgarzik@pobox.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'drivers/net/smc91x.h')
-rw-r--r--drivers/net/smc91x.h33
1 files changed, 27 insertions, 6 deletions
diff --git a/drivers/net/smc91x.h b/drivers/net/smc91x.h
index a9c41d421c37..5518c51bfd81 100644
--- a/drivers/net/smc91x.h
+++ b/drivers/net/smc91x.h
@@ -40,22 +40,44 @@
40 * Define your architecture specific bus configuration parameters here. 40 * Define your architecture specific bus configuration parameters here.
41 */ 41 */
42 42
43#if defined(CONFIG_ARCH_LUBBOCK) 43#if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE)
44 45
45/* We can only do 16-bit reads and writes in the static memory space. */ 46#include <asm/mach-types.h>
46#define SMC_CAN_USE_8BIT 0 47
48/* Now the bus width is specified in the platform data
49 * pretend here to support all I/O access types
50 */
51#define SMC_CAN_USE_8BIT 1
47#define SMC_CAN_USE_16BIT 1 52#define SMC_CAN_USE_16BIT 1
48#define SMC_CAN_USE_32BIT 0 53#define SMC_CAN_USE_32BIT 1
49#define SMC_NOWAIT 1 54#define SMC_NOWAIT 1
50 55
51#define SMC_IO_SHIFT (lp->io_shift) 56#define SMC_IO_SHIFT (lp->io_shift)
52 57
58#define SMC_inb(a, r) readb((a) + (r))
53#define SMC_inw(a, r) readw((a) + (r)) 59#define SMC_inw(a, r) readw((a) + (r))
54#define SMC_outw(v, a, r) writew(v, (a) + (r)) 60#define SMC_inl(a, r) readl((a) + (r))
61#define SMC_outb(v, a, r) writeb(v, (a) + (r))
62#define SMC_outl(v, a, r) writel(v, (a) + (r))
55#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) 63#define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
56#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 64#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
65#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
66#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
57#define SMC_IRQ_FLAGS (-1) /* from resource */ 67#define SMC_IRQ_FLAGS (-1) /* from resource */
58 68
69/* We actually can't write halfwords properly if not word aligned */
70static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
71{
72 if (machine_is_mainstone() && reg & 2) {
73 unsigned int v = val << 16;
74 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
75 writel(v, ioaddr + (reg & ~2));
76 } else {
77 writew(val, ioaddr + reg);
78 }
79}
80
59#elif defined(CONFIG_BLACKFIN) 81#elif defined(CONFIG_BLACKFIN)
60 82
61#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH 83#define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
@@ -194,7 +216,6 @@
194#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) 216#define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
195 217
196#elif defined(CONFIG_ARCH_INNOKOM) || \ 218#elif defined(CONFIG_ARCH_INNOKOM) || \
197 defined(CONFIG_MACH_MAINSTONE) || \
198 defined(CONFIG_ARCH_PXA_IDP) || \ 219 defined(CONFIG_ARCH_PXA_IDP) || \
199 defined(CONFIG_ARCH_RAMSES) || \ 220 defined(CONFIG_ARCH_RAMSES) || \
200 defined(CONFIG_ARCH_PCM027) 221 defined(CONFIG_ARCH_PCM027)