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authorMagnus Damm <magnus.damm@gmail.com>2008-02-22 05:55:05 -0500
committerJeff Garzik <jeff@garzik.org>2008-03-17 07:49:27 -0400
commitcfdfa86536d2fbc8102780ec15faea185e957d3d (patch)
tree4ec492270e502d912b6cbaebea91d6d2df20f7e8 /drivers/net/smc91x.c
parentcf374a855363ea2ad06a1c08fc513024295334cc (diff)
smc91x: pass along private data V2
Pass a private data pointer to macros and functions. This makes it easy to later on make run time decisions. This patch does not change any logic. These changes should be optimized away during compilation. V2 changes the macro argument name from "priv" to "lp". Signed-off-by: Magnus Damm <damm@igel.co.jp> Acked-by: Nicolas Pitre <nico@cam.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/smc91x.c')
-rw-r--r--drivers/net/smc91x.c301
1 files changed, 151 insertions, 150 deletions
diff --git a/drivers/net/smc91x.c b/drivers/net/smc91x.c
index 4020e9e955b3..d0ef80ae018a 100644
--- a/drivers/net/smc91x.c
+++ b/drivers/net/smc91x.c
@@ -220,22 +220,22 @@ static void PRINT_PKT(u_char *buf, int length)
220 220
221 221
222/* this enables an interrupt in the interrupt mask register */ 222/* this enables an interrupt in the interrupt mask register */
223#define SMC_ENABLE_INT(x) do { \ 223#define SMC_ENABLE_INT(lp, x) do { \
224 unsigned char mask; \ 224 unsigned char mask; \
225 spin_lock_irq(&lp->lock); \ 225 spin_lock_irq(&lp->lock); \
226 mask = SMC_GET_INT_MASK(); \ 226 mask = SMC_GET_INT_MASK(lp); \
227 mask |= (x); \ 227 mask |= (x); \
228 SMC_SET_INT_MASK(mask); \ 228 SMC_SET_INT_MASK(lp, mask); \
229 spin_unlock_irq(&lp->lock); \ 229 spin_unlock_irq(&lp->lock); \
230} while (0) 230} while (0)
231 231
232/* this disables an interrupt from the interrupt mask register */ 232/* this disables an interrupt from the interrupt mask register */
233#define SMC_DISABLE_INT(x) do { \ 233#define SMC_DISABLE_INT(lp, x) do { \
234 unsigned char mask; \ 234 unsigned char mask; \
235 spin_lock_irq(&lp->lock); \ 235 spin_lock_irq(&lp->lock); \
236 mask = SMC_GET_INT_MASK(); \ 236 mask = SMC_GET_INT_MASK(lp); \
237 mask &= ~(x); \ 237 mask &= ~(x); \
238 SMC_SET_INT_MASK(mask); \ 238 SMC_SET_INT_MASK(lp, mask); \
239 spin_unlock_irq(&lp->lock); \ 239 spin_unlock_irq(&lp->lock); \
240} while (0) 240} while (0)
241 241
@@ -244,10 +244,10 @@ static void PRINT_PKT(u_char *buf, int length)
244 * if at all, but let's avoid deadlocking the system if the hardware 244 * if at all, but let's avoid deadlocking the system if the hardware
245 * decides to go south. 245 * decides to go south.
246 */ 246 */
247#define SMC_WAIT_MMU_BUSY() do { \ 247#define SMC_WAIT_MMU_BUSY(lp) do { \
248 if (unlikely(SMC_GET_MMU_CMD() & MC_BUSY)) { \ 248 if (unlikely(SMC_GET_MMU_CMD(lp) & MC_BUSY)) { \
249 unsigned long timeout = jiffies + 2; \ 249 unsigned long timeout = jiffies + 2; \
250 while (SMC_GET_MMU_CMD() & MC_BUSY) { \ 250 while (SMC_GET_MMU_CMD(lp) & MC_BUSY) { \
251 if (time_after(jiffies, timeout)) { \ 251 if (time_after(jiffies, timeout)) { \
252 printk("%s: timeout %s line %d\n", \ 252 printk("%s: timeout %s line %d\n", \
253 dev->name, __FILE__, __LINE__); \ 253 dev->name, __FILE__, __LINE__); \
@@ -273,8 +273,8 @@ static void smc_reset(struct net_device *dev)
273 273
274 /* Disable all interrupts, block TX tasklet */ 274 /* Disable all interrupts, block TX tasklet */
275 spin_lock_irq(&lp->lock); 275 spin_lock_irq(&lp->lock);
276 SMC_SELECT_BANK(2); 276 SMC_SELECT_BANK(lp, 2);
277 SMC_SET_INT_MASK(0); 277 SMC_SET_INT_MASK(lp, 0);
278 pending_skb = lp->pending_tx_skb; 278 pending_skb = lp->pending_tx_skb;
279 lp->pending_tx_skb = NULL; 279 lp->pending_tx_skb = NULL;
280 spin_unlock_irq(&lp->lock); 280 spin_unlock_irq(&lp->lock);
@@ -290,15 +290,15 @@ static void smc_reset(struct net_device *dev)
290 * This resets the registers mostly to defaults, but doesn't 290 * This resets the registers mostly to defaults, but doesn't
291 * affect EEPROM. That seems unnecessary 291 * affect EEPROM. That seems unnecessary
292 */ 292 */
293 SMC_SELECT_BANK(0); 293 SMC_SELECT_BANK(lp, 0);
294 SMC_SET_RCR(RCR_SOFTRST); 294 SMC_SET_RCR(lp, RCR_SOFTRST);
295 295
296 /* 296 /*
297 * Setup the Configuration Register 297 * Setup the Configuration Register
298 * This is necessary because the CONFIG_REG is not affected 298 * This is necessary because the CONFIG_REG is not affected
299 * by a soft reset 299 * by a soft reset
300 */ 300 */
301 SMC_SELECT_BANK(1); 301 SMC_SELECT_BANK(lp, 1);
302 302
303 cfg = CONFIG_DEFAULT; 303 cfg = CONFIG_DEFAULT;
304 304
@@ -316,7 +316,7 @@ static void smc_reset(struct net_device *dev)
316 */ 316 */
317 cfg |= CONFIG_EPH_POWER_EN; 317 cfg |= CONFIG_EPH_POWER_EN;
318 318
319 SMC_SET_CONFIG(cfg); 319 SMC_SET_CONFIG(lp, cfg);
320 320
321 /* this should pause enough for the chip to be happy */ 321 /* this should pause enough for the chip to be happy */
322 /* 322 /*
@@ -329,12 +329,12 @@ static void smc_reset(struct net_device *dev)
329 udelay(1); 329 udelay(1);
330 330
331 /* Disable transmit and receive functionality */ 331 /* Disable transmit and receive functionality */
332 SMC_SELECT_BANK(0); 332 SMC_SELECT_BANK(lp, 0);
333 SMC_SET_RCR(RCR_CLEAR); 333 SMC_SET_RCR(lp, RCR_CLEAR);
334 SMC_SET_TCR(TCR_CLEAR); 334 SMC_SET_TCR(lp, TCR_CLEAR);
335 335
336 SMC_SELECT_BANK(1); 336 SMC_SELECT_BANK(lp, 1);
337 ctl = SMC_GET_CTL() | CTL_LE_ENABLE; 337 ctl = SMC_GET_CTL(lp) | CTL_LE_ENABLE;
338 338
339 /* 339 /*
340 * Set the control register to automatically release successfully 340 * Set the control register to automatically release successfully
@@ -345,12 +345,12 @@ static void smc_reset(struct net_device *dev)
345 ctl |= CTL_AUTO_RELEASE; 345 ctl |= CTL_AUTO_RELEASE;
346 else 346 else
347 ctl &= ~CTL_AUTO_RELEASE; 347 ctl &= ~CTL_AUTO_RELEASE;
348 SMC_SET_CTL(ctl); 348 SMC_SET_CTL(lp, ctl);
349 349
350 /* Reset the MMU */ 350 /* Reset the MMU */
351 SMC_SELECT_BANK(2); 351 SMC_SELECT_BANK(lp, 2);
352 SMC_SET_MMU_CMD(MC_RESET); 352 SMC_SET_MMU_CMD(lp, MC_RESET);
353 SMC_WAIT_MMU_BUSY(); 353 SMC_WAIT_MMU_BUSY(lp);
354} 354}
355 355
356/* 356/*
@@ -365,19 +365,19 @@ static void smc_enable(struct net_device *dev)
365 DBG(2, "%s: %s\n", dev->name, __FUNCTION__); 365 DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
366 366
367 /* see the header file for options in TCR/RCR DEFAULT */ 367 /* see the header file for options in TCR/RCR DEFAULT */
368 SMC_SELECT_BANK(0); 368 SMC_SELECT_BANK(lp, 0);
369 SMC_SET_TCR(lp->tcr_cur_mode); 369 SMC_SET_TCR(lp, lp->tcr_cur_mode);
370 SMC_SET_RCR(lp->rcr_cur_mode); 370 SMC_SET_RCR(lp, lp->rcr_cur_mode);
371 371
372 SMC_SELECT_BANK(1); 372 SMC_SELECT_BANK(lp, 1);
373 SMC_SET_MAC_ADDR(dev->dev_addr); 373 SMC_SET_MAC_ADDR(lp, dev->dev_addr);
374 374
375 /* now, enable interrupts */ 375 /* now, enable interrupts */
376 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT; 376 mask = IM_EPH_INT|IM_RX_OVRN_INT|IM_RCV_INT;
377 if (lp->version >= (CHIP_91100 << 4)) 377 if (lp->version >= (CHIP_91100 << 4))
378 mask |= IM_MDINT; 378 mask |= IM_MDINT;
379 SMC_SELECT_BANK(2); 379 SMC_SELECT_BANK(lp, 2);
380 SMC_SET_INT_MASK(mask); 380 SMC_SET_INT_MASK(lp, mask);
381 381
382 /* 382 /*
383 * From this point the register bank must _NOT_ be switched away 383 * From this point the register bank must _NOT_ be switched away
@@ -400,8 +400,8 @@ static void smc_shutdown(struct net_device *dev)
400 400
401 /* no more interrupts for me */ 401 /* no more interrupts for me */
402 spin_lock_irq(&lp->lock); 402 spin_lock_irq(&lp->lock);
403 SMC_SELECT_BANK(2); 403 SMC_SELECT_BANK(lp, 2);
404 SMC_SET_INT_MASK(0); 404 SMC_SET_INT_MASK(lp, 0);
405 pending_skb = lp->pending_tx_skb; 405 pending_skb = lp->pending_tx_skb;
406 lp->pending_tx_skb = NULL; 406 lp->pending_tx_skb = NULL;
407 spin_unlock_irq(&lp->lock); 407 spin_unlock_irq(&lp->lock);
@@ -409,14 +409,14 @@ static void smc_shutdown(struct net_device *dev)
409 dev_kfree_skb(pending_skb); 409 dev_kfree_skb(pending_skb);
410 410
411 /* and tell the card to stay away from that nasty outside world */ 411 /* and tell the card to stay away from that nasty outside world */
412 SMC_SELECT_BANK(0); 412 SMC_SELECT_BANK(lp, 0);
413 SMC_SET_RCR(RCR_CLEAR); 413 SMC_SET_RCR(lp, RCR_CLEAR);
414 SMC_SET_TCR(TCR_CLEAR); 414 SMC_SET_TCR(lp, TCR_CLEAR);
415 415
416#ifdef POWER_DOWN 416#ifdef POWER_DOWN
417 /* finally, shut the chip down */ 417 /* finally, shut the chip down */
418 SMC_SELECT_BANK(1); 418 SMC_SELECT_BANK(lp, 1);
419 SMC_SET_CONFIG(SMC_GET_CONFIG() & ~CONFIG_EPH_POWER_EN); 419 SMC_SET_CONFIG(lp, SMC_GET_CONFIG(lp) & ~CONFIG_EPH_POWER_EN);
420#endif 420#endif
421} 421}
422 422
@@ -431,17 +431,17 @@ static inline void smc_rcv(struct net_device *dev)
431 431
432 DBG(3, "%s: %s\n", dev->name, __FUNCTION__); 432 DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
433 433
434 packet_number = SMC_GET_RXFIFO(); 434 packet_number = SMC_GET_RXFIFO(lp);
435 if (unlikely(packet_number & RXFIFO_REMPTY)) { 435 if (unlikely(packet_number & RXFIFO_REMPTY)) {
436 PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name); 436 PRINTK("%s: smc_rcv with nothing on FIFO.\n", dev->name);
437 return; 437 return;
438 } 438 }
439 439
440 /* read from start of packet */ 440 /* read from start of packet */
441 SMC_SET_PTR(PTR_READ | PTR_RCV | PTR_AUTOINC); 441 SMC_SET_PTR(lp, PTR_READ | PTR_RCV | PTR_AUTOINC);
442 442
443 /* First two words are status and packet length */ 443 /* First two words are status and packet length */
444 SMC_GET_PKT_HDR(status, packet_len); 444 SMC_GET_PKT_HDR(lp, status, packet_len);
445 packet_len &= 0x07ff; /* mask off top bits */ 445 packet_len &= 0x07ff; /* mask off top bits */
446 DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n", 446 DBG(2, "%s: RX PNR 0x%x STATUS 0x%04x LENGTH 0x%04x (%d)\n",
447 dev->name, packet_number, status, 447 dev->name, packet_number, status,
@@ -460,8 +460,8 @@ static inline void smc_rcv(struct net_device *dev)
460 dev->name, packet_len, status); 460 dev->name, packet_len, status);
461 status |= RS_TOOSHORT; 461 status |= RS_TOOSHORT;
462 } 462 }
463 SMC_WAIT_MMU_BUSY(); 463 SMC_WAIT_MMU_BUSY(lp);
464 SMC_SET_MMU_CMD(MC_RELEASE); 464 SMC_SET_MMU_CMD(lp, MC_RELEASE);
465 dev->stats.rx_errors++; 465 dev->stats.rx_errors++;
466 if (status & RS_ALGNERR) 466 if (status & RS_ALGNERR)
467 dev->stats.rx_frame_errors++; 467 dev->stats.rx_frame_errors++;
@@ -490,8 +490,8 @@ static inline void smc_rcv(struct net_device *dev)
490 if (unlikely(skb == NULL)) { 490 if (unlikely(skb == NULL)) {
491 printk(KERN_NOTICE "%s: Low memory, packet dropped.\n", 491 printk(KERN_NOTICE "%s: Low memory, packet dropped.\n",
492 dev->name); 492 dev->name);
493 SMC_WAIT_MMU_BUSY(); 493 SMC_WAIT_MMU_BUSY(lp);
494 SMC_SET_MMU_CMD(MC_RELEASE); 494 SMC_SET_MMU_CMD(lp, MC_RELEASE);
495 dev->stats.rx_dropped++; 495 dev->stats.rx_dropped++;
496 return; 496 return;
497 } 497 }
@@ -510,10 +510,10 @@ static inline void smc_rcv(struct net_device *dev)
510 */ 510 */
511 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6); 511 data_len = packet_len - ((status & RS_ODDFRAME) ? 5 : 6);
512 data = skb_put(skb, data_len); 512 data = skb_put(skb, data_len);
513 SMC_PULL_DATA(data, packet_len - 4); 513 SMC_PULL_DATA(lp, data, packet_len - 4);
514 514
515 SMC_WAIT_MMU_BUSY(); 515 SMC_WAIT_MMU_BUSY(lp);
516 SMC_SET_MMU_CMD(MC_RELEASE); 516 SMC_SET_MMU_CMD(lp, MC_RELEASE);
517 517
518 PRINT_PKT(data, packet_len - 4); 518 PRINT_PKT(data, packet_len - 4);
519 519
@@ -591,7 +591,7 @@ static void smc_hardware_send_pkt(unsigned long data)
591 } 591 }
592 lp->pending_tx_skb = NULL; 592 lp->pending_tx_skb = NULL;
593 593
594 packet_no = SMC_GET_AR(); 594 packet_no = SMC_GET_AR(lp);
595 if (unlikely(packet_no & AR_FAILED)) { 595 if (unlikely(packet_no & AR_FAILED)) {
596 printk("%s: Memory allocation failed.\n", dev->name); 596 printk("%s: Memory allocation failed.\n", dev->name);
597 dev->stats.tx_errors++; 597 dev->stats.tx_errors++;
@@ -601,8 +601,8 @@ static void smc_hardware_send_pkt(unsigned long data)
601 } 601 }
602 602
603 /* point to the beginning of the packet */ 603 /* point to the beginning of the packet */
604 SMC_SET_PN(packet_no); 604 SMC_SET_PN(lp, packet_no);
605 SMC_SET_PTR(PTR_AUTOINC); 605 SMC_SET_PTR(lp, PTR_AUTOINC);
606 606
607 buf = skb->data; 607 buf = skb->data;
608 len = skb->len; 608 len = skb->len;
@@ -614,13 +614,13 @@ static void smc_hardware_send_pkt(unsigned long data)
614 * Send the packet length (+6 for status words, length, and ctl. 614 * Send the packet length (+6 for status words, length, and ctl.
615 * The card will pad to 64 bytes with zeroes if packet is too small. 615 * The card will pad to 64 bytes with zeroes if packet is too small.
616 */ 616 */
617 SMC_PUT_PKT_HDR(0, len + 6); 617 SMC_PUT_PKT_HDR(lp, 0, len + 6);
618 618
619 /* send the actual data */ 619 /* send the actual data */
620 SMC_PUSH_DATA(buf, len & ~1); 620 SMC_PUSH_DATA(lp, buf, len & ~1);
621 621
622 /* Send final ctl word with the last byte if there is one */ 622 /* Send final ctl word with the last byte if there is one */
623 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG); 623 SMC_outw(((len & 1) ? (0x2000 | buf[len-1]) : 0), ioaddr, DATA_REG(lp));
624 624
625 /* 625 /*
626 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will 626 * If THROTTLE_TX_PKTS is set, we stop the queue here. This will
@@ -634,14 +634,14 @@ static void smc_hardware_send_pkt(unsigned long data)
634 netif_stop_queue(dev); 634 netif_stop_queue(dev);
635 635
636 /* queue the packet for TX */ 636 /* queue the packet for TX */
637 SMC_SET_MMU_CMD(MC_ENQUEUE); 637 SMC_SET_MMU_CMD(lp, MC_ENQUEUE);
638 smc_special_unlock(&lp->lock); 638 smc_special_unlock(&lp->lock);
639 639
640 dev->trans_start = jiffies; 640 dev->trans_start = jiffies;
641 dev->stats.tx_packets++; 641 dev->stats.tx_packets++;
642 dev->stats.tx_bytes += len; 642 dev->stats.tx_bytes += len;
643 643
644 SMC_ENABLE_INT(IM_TX_INT | IM_TX_EMPTY_INT); 644 SMC_ENABLE_INT(lp, IM_TX_INT | IM_TX_EMPTY_INT);
645 645
646done: if (!THROTTLE_TX_PKTS) 646done: if (!THROTTLE_TX_PKTS)
647 netif_wake_queue(dev); 647 netif_wake_queue(dev);
@@ -688,7 +688,7 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
688 smc_special_lock(&lp->lock); 688 smc_special_lock(&lp->lock);
689 689
690 /* now, try to allocate the memory */ 690 /* now, try to allocate the memory */
691 SMC_SET_MMU_CMD(MC_ALLOC | numPages); 691 SMC_SET_MMU_CMD(lp, MC_ALLOC | numPages);
692 692
693 /* 693 /*
694 * Poll the chip for a short amount of time in case the 694 * Poll the chip for a short amount of time in case the
@@ -696,9 +696,9 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
696 */ 696 */
697 poll_count = MEMORY_WAIT_TIME; 697 poll_count = MEMORY_WAIT_TIME;
698 do { 698 do {
699 status = SMC_GET_INT(); 699 status = SMC_GET_INT(lp);
700 if (status & IM_ALLOC_INT) { 700 if (status & IM_ALLOC_INT) {
701 SMC_ACK_INT(IM_ALLOC_INT); 701 SMC_ACK_INT(lp, IM_ALLOC_INT);
702 break; 702 break;
703 } 703 }
704 } while (--poll_count); 704 } while (--poll_count);
@@ -710,7 +710,7 @@ static int smc_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
710 /* oh well, wait until the chip finds memory later */ 710 /* oh well, wait until the chip finds memory later */
711 netif_stop_queue(dev); 711 netif_stop_queue(dev);
712 DBG(2, "%s: TX memory allocation deferred.\n", dev->name); 712 DBG(2, "%s: TX memory allocation deferred.\n", dev->name);
713 SMC_ENABLE_INT(IM_ALLOC_INT); 713 SMC_ENABLE_INT(lp, IM_ALLOC_INT);
714 } else { 714 } else {
715 /* 715 /*
716 * Allocation succeeded: push packet to the chip's own memory 716 * Allocation succeeded: push packet to the chip's own memory
@@ -736,19 +736,19 @@ static void smc_tx(struct net_device *dev)
736 DBG(3, "%s: %s\n", dev->name, __FUNCTION__); 736 DBG(3, "%s: %s\n", dev->name, __FUNCTION__);
737 737
738 /* If the TX FIFO is empty then nothing to do */ 738 /* If the TX FIFO is empty then nothing to do */
739 packet_no = SMC_GET_TXFIFO(); 739 packet_no = SMC_GET_TXFIFO(lp);
740 if (unlikely(packet_no & TXFIFO_TEMPTY)) { 740 if (unlikely(packet_no & TXFIFO_TEMPTY)) {
741 PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name); 741 PRINTK("%s: smc_tx with nothing on FIFO.\n", dev->name);
742 return; 742 return;
743 } 743 }
744 744
745 /* select packet to read from */ 745 /* select packet to read from */
746 saved_packet = SMC_GET_PN(); 746 saved_packet = SMC_GET_PN(lp);
747 SMC_SET_PN(packet_no); 747 SMC_SET_PN(lp, packet_no);
748 748
749 /* read the first word (status word) from this packet */ 749 /* read the first word (status word) from this packet */
750 SMC_SET_PTR(PTR_AUTOINC | PTR_READ); 750 SMC_SET_PTR(lp, PTR_AUTOINC | PTR_READ);
751 SMC_GET_PKT_HDR(tx_status, pkt_len); 751 SMC_GET_PKT_HDR(lp, tx_status, pkt_len);
752 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n", 752 DBG(2, "%s: TX STATUS 0x%04x PNR 0x%02x\n",
753 dev->name, tx_status, packet_no); 753 dev->name, tx_status, packet_no);
754 754
@@ -771,17 +771,17 @@ static void smc_tx(struct net_device *dev)
771 } 771 }
772 772
773 /* kill the packet */ 773 /* kill the packet */
774 SMC_WAIT_MMU_BUSY(); 774 SMC_WAIT_MMU_BUSY(lp);
775 SMC_SET_MMU_CMD(MC_FREEPKT); 775 SMC_SET_MMU_CMD(lp, MC_FREEPKT);
776 776
777 /* Don't restore Packet Number Reg until busy bit is cleared */ 777 /* Don't restore Packet Number Reg until busy bit is cleared */
778 SMC_WAIT_MMU_BUSY(); 778 SMC_WAIT_MMU_BUSY(lp);
779 SMC_SET_PN(saved_packet); 779 SMC_SET_PN(lp, saved_packet);
780 780
781 /* re-enable transmit */ 781 /* re-enable transmit */
782 SMC_SELECT_BANK(0); 782 SMC_SELECT_BANK(lp, 0);
783 SMC_SET_TCR(lp->tcr_cur_mode); 783 SMC_SET_TCR(lp, lp->tcr_cur_mode);
784 SMC_SELECT_BANK(2); 784 SMC_SELECT_BANK(lp, 2);
785} 785}
786 786
787 787
@@ -793,7 +793,7 @@ static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
793 void __iomem *ioaddr = lp->base; 793 void __iomem *ioaddr = lp->base;
794 unsigned int mii_reg, mask; 794 unsigned int mii_reg, mask;
795 795
796 mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); 796 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
797 mii_reg |= MII_MDOE; 797 mii_reg |= MII_MDOE;
798 798
799 for (mask = 1 << (bits - 1); mask; mask >>= 1) { 799 for (mask = 1 << (bits - 1); mask; mask >>= 1) {
@@ -802,9 +802,9 @@ static void smc_mii_out(struct net_device *dev, unsigned int val, int bits)
802 else 802 else
803 mii_reg &= ~MII_MDO; 803 mii_reg &= ~MII_MDO;
804 804
805 SMC_SET_MII(mii_reg); 805 SMC_SET_MII(lp, mii_reg);
806 udelay(MII_DELAY); 806 udelay(MII_DELAY);
807 SMC_SET_MII(mii_reg | MII_MCLK); 807 SMC_SET_MII(lp, mii_reg | MII_MCLK);
808 udelay(MII_DELAY); 808 udelay(MII_DELAY);
809 } 809 }
810} 810}
@@ -815,16 +815,16 @@ static unsigned int smc_mii_in(struct net_device *dev, int bits)
815 void __iomem *ioaddr = lp->base; 815 void __iomem *ioaddr = lp->base;
816 unsigned int mii_reg, mask, val; 816 unsigned int mii_reg, mask, val;
817 817
818 mii_reg = SMC_GET_MII() & ~(MII_MCLK | MII_MDOE | MII_MDO); 818 mii_reg = SMC_GET_MII(lp) & ~(MII_MCLK | MII_MDOE | MII_MDO);
819 SMC_SET_MII(mii_reg); 819 SMC_SET_MII(lp, mii_reg);
820 820
821 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) { 821 for (mask = 1 << (bits - 1), val = 0; mask; mask >>= 1) {
822 if (SMC_GET_MII() & MII_MDI) 822 if (SMC_GET_MII(lp) & MII_MDI)
823 val |= mask; 823 val |= mask;
824 824
825 SMC_SET_MII(mii_reg); 825 SMC_SET_MII(lp, mii_reg);
826 udelay(MII_DELAY); 826 udelay(MII_DELAY);
827 SMC_SET_MII(mii_reg | MII_MCLK); 827 SMC_SET_MII(lp, mii_reg | MII_MCLK);
828 udelay(MII_DELAY); 828 udelay(MII_DELAY);
829 } 829 }
830 830
@@ -840,7 +840,7 @@ static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
840 void __iomem *ioaddr = lp->base; 840 void __iomem *ioaddr = lp->base;
841 unsigned int phydata; 841 unsigned int phydata;
842 842
843 SMC_SELECT_BANK(3); 843 SMC_SELECT_BANK(lp, 3);
844 844
845 /* Idle - 32 ones */ 845 /* Idle - 32 ones */
846 smc_mii_out(dev, 0xffffffff, 32); 846 smc_mii_out(dev, 0xffffffff, 32);
@@ -852,12 +852,12 @@ static int smc_phy_read(struct net_device *dev, int phyaddr, int phyreg)
852 phydata = smc_mii_in(dev, 18); 852 phydata = smc_mii_in(dev, 18);
853 853
854 /* Return to idle state */ 854 /* Return to idle state */
855 SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); 855 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
856 856
857 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 857 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
858 __FUNCTION__, phyaddr, phyreg, phydata); 858 __FUNCTION__, phyaddr, phyreg, phydata);
859 859
860 SMC_SELECT_BANK(2); 860 SMC_SELECT_BANK(lp, 2);
861 return phydata; 861 return phydata;
862} 862}
863 863
@@ -870,7 +870,7 @@ static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
870 struct smc_local *lp = netdev_priv(dev); 870 struct smc_local *lp = netdev_priv(dev);
871 void __iomem *ioaddr = lp->base; 871 void __iomem *ioaddr = lp->base;
872 872
873 SMC_SELECT_BANK(3); 873 SMC_SELECT_BANK(lp, 3);
874 874
875 /* Idle - 32 ones */ 875 /* Idle - 32 ones */
876 smc_mii_out(dev, 0xffffffff, 32); 876 smc_mii_out(dev, 0xffffffff, 32);
@@ -879,12 +879,12 @@ static void smc_phy_write(struct net_device *dev, int phyaddr, int phyreg,
879 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32); 879 smc_mii_out(dev, 5 << 28 | phyaddr << 23 | phyreg << 18 | 2 << 16 | phydata, 32);
880 880
881 /* Return to idle state */ 881 /* Return to idle state */
882 SMC_SET_MII(SMC_GET_MII() & ~(MII_MCLK|MII_MDOE|MII_MDO)); 882 SMC_SET_MII(lp, SMC_GET_MII(lp) & ~(MII_MCLK|MII_MDOE|MII_MDO));
883 883
884 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n", 884 DBG(3, "%s: phyaddr=0x%x, phyreg=0x%x, phydata=0x%x\n",
885 __FUNCTION__, phyaddr, phyreg, phydata); 885 __FUNCTION__, phyaddr, phyreg, phydata);
886 886
887 SMC_SELECT_BANK(2); 887 SMC_SELECT_BANK(lp, 2);
888} 888}
889 889
890/* 890/*
@@ -957,9 +957,9 @@ static int smc_phy_fixed(struct net_device *dev)
957 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr); 957 smc_phy_write(dev, phyaddr, MII_BMCR, bmcr);
958 958
959 /* Re-Configure the Receive/Phy Control register */ 959 /* Re-Configure the Receive/Phy Control register */
960 SMC_SELECT_BANK(0); 960 SMC_SELECT_BANK(lp, 0);
961 SMC_SET_RPC(lp->rpc_cur_mode); 961 SMC_SET_RPC(lp, lp->rpc_cur_mode);
962 SMC_SELECT_BANK(2); 962 SMC_SELECT_BANK(lp, 2);
963 963
964 return 1; 964 return 1;
965} 965}
@@ -1050,8 +1050,8 @@ static void smc_phy_check_media(struct net_device *dev, int init)
1050 lp->tcr_cur_mode &= ~TCR_SWFDUP; 1050 lp->tcr_cur_mode &= ~TCR_SWFDUP;
1051 } 1051 }
1052 1052
1053 SMC_SELECT_BANK(0); 1053 SMC_SELECT_BANK(lp, 0);
1054 SMC_SET_TCR(lp->tcr_cur_mode); 1054 SMC_SET_TCR(lp, lp->tcr_cur_mode);
1055 } 1055 }
1056} 1056}
1057 1057
@@ -1100,8 +1100,8 @@ static void smc_phy_configure(struct work_struct *work)
1100 PHY_INT_SPDDET | PHY_INT_DPLXDET); 1100 PHY_INT_SPDDET | PHY_INT_DPLXDET);
1101 1101
1102 /* Configure the Receive/Phy Control register */ 1102 /* Configure the Receive/Phy Control register */
1103 SMC_SELECT_BANK(0); 1103 SMC_SELECT_BANK(lp, 0);
1104 SMC_SET_RPC(lp->rpc_cur_mode); 1104 SMC_SET_RPC(lp, lp->rpc_cur_mode);
1105 1105
1106 /* If the user requested no auto neg, then go set his request */ 1106 /* If the user requested no auto neg, then go set his request */
1107 if (lp->mii.force_media) { 1107 if (lp->mii.force_media) {
@@ -1158,7 +1158,7 @@ static void smc_phy_configure(struct work_struct *work)
1158 smc_phy_check_media(dev, 1); 1158 smc_phy_check_media(dev, 1);
1159 1159
1160smc_phy_configure_exit: 1160smc_phy_configure_exit:
1161 SMC_SELECT_BANK(2); 1161 SMC_SELECT_BANK(lp, 2);
1162 spin_unlock_irq(&lp->lock); 1162 spin_unlock_irq(&lp->lock);
1163 lp->work_pending = 0; 1163 lp->work_pending = 0;
1164} 1164}
@@ -1200,9 +1200,9 @@ static void smc_10bt_check_media(struct net_device *dev, int init)
1200 1200
1201 old_carrier = netif_carrier_ok(dev) ? 1 : 0; 1201 old_carrier = netif_carrier_ok(dev) ? 1 : 0;
1202 1202
1203 SMC_SELECT_BANK(0); 1203 SMC_SELECT_BANK(lp, 0);
1204 new_carrier = (SMC_GET_EPH_STATUS() & ES_LINK_OK) ? 1 : 0; 1204 new_carrier = (SMC_GET_EPH_STATUS(lp) & ES_LINK_OK) ? 1 : 0;
1205 SMC_SELECT_BANK(2); 1205 SMC_SELECT_BANK(lp, 2);
1206 1206
1207 if (init || (old_carrier != new_carrier)) { 1207 if (init || (old_carrier != new_carrier)) {
1208 if (!new_carrier) { 1208 if (!new_carrier) {
@@ -1224,11 +1224,11 @@ static void smc_eph_interrupt(struct net_device *dev)
1224 1224
1225 smc_10bt_check_media(dev, 0); 1225 smc_10bt_check_media(dev, 0);
1226 1226
1227 SMC_SELECT_BANK(1); 1227 SMC_SELECT_BANK(lp, 1);
1228 ctl = SMC_GET_CTL(); 1228 ctl = SMC_GET_CTL(lp);
1229 SMC_SET_CTL(ctl & ~CTL_LE_ENABLE); 1229 SMC_SET_CTL(lp, ctl & ~CTL_LE_ENABLE);
1230 SMC_SET_CTL(ctl); 1230 SMC_SET_CTL(lp, ctl);
1231 SMC_SELECT_BANK(2); 1231 SMC_SELECT_BANK(lp, 2);
1232} 1232}
1233 1233
1234/* 1234/*
@@ -1252,22 +1252,22 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
1252 * ISR. */ 1252 * ISR. */
1253 SMC_INTERRUPT_PREAMBLE; 1253 SMC_INTERRUPT_PREAMBLE;
1254 1254
1255 saved_pointer = SMC_GET_PTR(); 1255 saved_pointer = SMC_GET_PTR(lp);
1256 mask = SMC_GET_INT_MASK(); 1256 mask = SMC_GET_INT_MASK(lp);
1257 SMC_SET_INT_MASK(0); 1257 SMC_SET_INT_MASK(lp, 0);
1258 1258
1259 /* set a timeout value, so I don't stay here forever */ 1259 /* set a timeout value, so I don't stay here forever */
1260 timeout = MAX_IRQ_LOOPS; 1260 timeout = MAX_IRQ_LOOPS;
1261 1261
1262 do { 1262 do {
1263 status = SMC_GET_INT(); 1263 status = SMC_GET_INT(lp);
1264 1264
1265 DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n", 1265 DBG(2, "%s: INT 0x%02x MASK 0x%02x MEM 0x%04x FIFO 0x%04x\n",
1266 dev->name, status, mask, 1266 dev->name, status, mask,
1267 ({ int meminfo; SMC_SELECT_BANK(0); 1267 ({ int meminfo; SMC_SELECT_BANK(lp, 0);
1268 meminfo = SMC_GET_MIR(); 1268 meminfo = SMC_GET_MIR(lp);
1269 SMC_SELECT_BANK(2); meminfo; }), 1269 SMC_SELECT_BANK(lp, 2); meminfo; }),
1270 SMC_GET_FIFO()); 1270 SMC_GET_FIFO(lp));
1271 1271
1272 status &= mask; 1272 status &= mask;
1273 if (!status) 1273 if (!status)
@@ -1277,7 +1277,7 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
1277 /* do this before RX as it will free memory quickly */ 1277 /* do this before RX as it will free memory quickly */
1278 DBG(3, "%s: TX int\n", dev->name); 1278 DBG(3, "%s: TX int\n", dev->name);
1279 smc_tx(dev); 1279 smc_tx(dev);
1280 SMC_ACK_INT(IM_TX_INT); 1280 SMC_ACK_INT(lp, IM_TX_INT);
1281 if (THROTTLE_TX_PKTS) 1281 if (THROTTLE_TX_PKTS)
1282 netif_wake_queue(dev); 1282 netif_wake_queue(dev);
1283 } else if (status & IM_RCV_INT) { 1283 } else if (status & IM_RCV_INT) {
@@ -1292,9 +1292,9 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
1292 mask &= ~IM_TX_EMPTY_INT; 1292 mask &= ~IM_TX_EMPTY_INT;
1293 1293
1294 /* update stats */ 1294 /* update stats */
1295 SMC_SELECT_BANK(0); 1295 SMC_SELECT_BANK(lp, 0);
1296 card_stats = SMC_GET_COUNTER(); 1296 card_stats = SMC_GET_COUNTER(lp);
1297 SMC_SELECT_BANK(2); 1297 SMC_SELECT_BANK(lp, 2);
1298 1298
1299 /* single collisions */ 1299 /* single collisions */
1300 dev->stats.collisions += card_stats & 0xF; 1300 dev->stats.collisions += card_stats & 0xF;
@@ -1304,26 +1304,26 @@ static irqreturn_t smc_interrupt(int irq, void *dev_id)
1304 dev->stats.collisions += card_stats & 0xF; 1304 dev->stats.collisions += card_stats & 0xF;
1305 } else if (status & IM_RX_OVRN_INT) { 1305 } else if (status & IM_RX_OVRN_INT) {
1306 DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name, 1306 DBG(1, "%s: RX overrun (EPH_ST 0x%04x)\n", dev->name,
1307 ({ int eph_st; SMC_SELECT_BANK(0); 1307 ({ int eph_st; SMC_SELECT_BANK(lp, 0);
1308 eph_st = SMC_GET_EPH_STATUS(); 1308 eph_st = SMC_GET_EPH_STATUS(lp);
1309 SMC_SELECT_BANK(2); eph_st; }) ); 1309 SMC_SELECT_BANK(lp, 2); eph_st; }));
1310 SMC_ACK_INT(IM_RX_OVRN_INT); 1310 SMC_ACK_INT(lp, IM_RX_OVRN_INT);
1311 dev->stats.rx_errors++; 1311 dev->stats.rx_errors++;
1312 dev->stats.rx_fifo_errors++; 1312 dev->stats.rx_fifo_errors++;
1313 } else if (status & IM_EPH_INT) { 1313 } else if (status & IM_EPH_INT) {
1314 smc_eph_interrupt(dev); 1314 smc_eph_interrupt(dev);
1315 } else if (status & IM_MDINT) { 1315 } else if (status & IM_MDINT) {
1316 SMC_ACK_INT(IM_MDINT); 1316 SMC_ACK_INT(lp, IM_MDINT);
1317 smc_phy_interrupt(dev); 1317 smc_phy_interrupt(dev);
1318 } else if (status & IM_ERCV_INT) { 1318 } else if (status & IM_ERCV_INT) {
1319 SMC_ACK_INT(IM_ERCV_INT); 1319 SMC_ACK_INT(lp, IM_ERCV_INT);
1320 PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name); 1320 PRINTK("%s: UNSUPPORTED: ERCV INTERRUPT \n", dev->name);
1321 } 1321 }
1322 } while (--timeout); 1322 } while (--timeout);
1323 1323
1324 /* restore register states */ 1324 /* restore register states */
1325 SMC_SET_PTR(saved_pointer); 1325 SMC_SET_PTR(lp, saved_pointer);
1326 SMC_SET_INT_MASK(mask); 1326 SMC_SET_INT_MASK(lp, mask);
1327 spin_unlock(&lp->lock); 1327 spin_unlock(&lp->lock);
1328 1328
1329 if (timeout == MAX_IRQ_LOOPS) 1329 if (timeout == MAX_IRQ_LOOPS)
@@ -1366,13 +1366,13 @@ static void smc_timeout(struct net_device *dev)
1366 DBG(2, "%s: %s\n", dev->name, __FUNCTION__); 1366 DBG(2, "%s: %s\n", dev->name, __FUNCTION__);
1367 1367
1368 spin_lock_irq(&lp->lock); 1368 spin_lock_irq(&lp->lock);
1369 status = SMC_GET_INT(); 1369 status = SMC_GET_INT(lp);
1370 mask = SMC_GET_INT_MASK(); 1370 mask = SMC_GET_INT_MASK(lp);
1371 fifo = SMC_GET_FIFO(); 1371 fifo = SMC_GET_FIFO(lp);
1372 SMC_SELECT_BANK(0); 1372 SMC_SELECT_BANK(lp, 0);
1373 eph_st = SMC_GET_EPH_STATUS(); 1373 eph_st = SMC_GET_EPH_STATUS(lp);
1374 meminfo = SMC_GET_MIR(); 1374 meminfo = SMC_GET_MIR(lp);
1375 SMC_SELECT_BANK(2); 1375 SMC_SELECT_BANK(lp, 2);
1376 spin_unlock_irq(&lp->lock); 1376 spin_unlock_irq(&lp->lock);
1377 PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x " 1377 PRINTK( "%s: TX timeout (INT 0x%02x INTMASK 0x%02x "
1378 "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n", 1378 "MEM 0x%04x FIFO 0x%04x EPH_ST 0x%04x)\n",
@@ -1492,13 +1492,13 @@ static void smc_set_multicast_list(struct net_device *dev)
1492 } 1492 }
1493 1493
1494 spin_lock_irq(&lp->lock); 1494 spin_lock_irq(&lp->lock);
1495 SMC_SELECT_BANK(0); 1495 SMC_SELECT_BANK(lp, 0);
1496 SMC_SET_RCR(lp->rcr_cur_mode); 1496 SMC_SET_RCR(lp, lp->rcr_cur_mode);
1497 if (update_multicast) { 1497 if (update_multicast) {
1498 SMC_SELECT_BANK(3); 1498 SMC_SELECT_BANK(lp, 3);
1499 SMC_SET_MCAST(multicast_table); 1499 SMC_SET_MCAST(lp, multicast_table);
1500 } 1500 }
1501 SMC_SELECT_BANK(2); 1501 SMC_SELECT_BANK(lp, 2);
1502 spin_unlock_irq(&lp->lock); 1502 spin_unlock_irq(&lp->lock);
1503} 1503}
1504 1504
@@ -1702,8 +1702,9 @@ static const struct ethtool_ops smc_ethtool_ops = {
1702 * I just deleted auto_irq.c, since it was never built... 1702 * I just deleted auto_irq.c, since it was never built...
1703 * --jgarzik 1703 * --jgarzik
1704 */ 1704 */
1705static int __init smc_findirq(void __iomem *ioaddr) 1705static int __init smc_findirq(struct smc_local *lp)
1706{ 1706{
1707 void __iomem *ioaddr = lp->base;
1707 int timeout = 20; 1708 int timeout = 20;
1708 unsigned long cookie; 1709 unsigned long cookie;
1709 1710
@@ -1717,14 +1718,14 @@ static int __init smc_findirq(void __iomem *ioaddr)
1717 * when done. 1718 * when done.
1718 */ 1719 */
1719 /* enable ALLOCation interrupts ONLY */ 1720 /* enable ALLOCation interrupts ONLY */
1720 SMC_SELECT_BANK(2); 1721 SMC_SELECT_BANK(lp, 2);
1721 SMC_SET_INT_MASK(IM_ALLOC_INT); 1722 SMC_SET_INT_MASK(lp, IM_ALLOC_INT);
1722 1723
1723 /* 1724 /*
1724 * Allocate 512 bytes of memory. Note that the chip was just 1725 * Allocate 512 bytes of memory. Note that the chip was just
1725 * reset so all the memory is available 1726 * reset so all the memory is available
1726 */ 1727 */
1727 SMC_SET_MMU_CMD(MC_ALLOC | 1); 1728 SMC_SET_MMU_CMD(lp, MC_ALLOC | 1);
1728 1729
1729 /* 1730 /*
1730 * Wait until positive that the interrupt has been generated 1731 * Wait until positive that the interrupt has been generated
@@ -1732,7 +1733,7 @@ static int __init smc_findirq(void __iomem *ioaddr)
1732 do { 1733 do {
1733 int int_status; 1734 int int_status;
1734 udelay(10); 1735 udelay(10);
1735 int_status = SMC_GET_INT(); 1736 int_status = SMC_GET_INT(lp);
1736 if (int_status & IM_ALLOC_INT) 1737 if (int_status & IM_ALLOC_INT)
1737 break; /* got the interrupt */ 1738 break; /* got the interrupt */
1738 } while (--timeout); 1739 } while (--timeout);
@@ -1745,7 +1746,7 @@ static int __init smc_findirq(void __iomem *ioaddr)
1745 */ 1746 */
1746 1747
1747 /* and disable all interrupts again */ 1748 /* and disable all interrupts again */
1748 SMC_SET_INT_MASK(0); 1749 SMC_SET_INT_MASK(lp, 0);
1749 1750
1750 /* and return what I found */ 1751 /* and return what I found */
1751 return probe_irq_off(cookie); 1752 return probe_irq_off(cookie);
@@ -1788,7 +1789,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
1788 DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__); 1789 DBG(2, "%s: %s\n", CARDNAME, __FUNCTION__);
1789 1790
1790 /* First, see if the high byte is 0x33 */ 1791 /* First, see if the high byte is 0x33 */
1791 val = SMC_CURRENT_BANK(); 1792 val = SMC_CURRENT_BANK(lp);
1792 DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val); 1793 DBG(2, "%s: bank signature probe returned 0x%04x\n", CARDNAME, val);
1793 if ((val & 0xFF00) != 0x3300) { 1794 if ((val & 0xFF00) != 0x3300) {
1794 if ((val & 0xFF) == 0x33) { 1795 if ((val & 0xFF) == 0x33) {
@@ -1804,8 +1805,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
1804 * The above MIGHT indicate a device, but I need to write to 1805 * The above MIGHT indicate a device, but I need to write to
1805 * further test this. 1806 * further test this.
1806 */ 1807 */
1807 SMC_SELECT_BANK(0); 1808 SMC_SELECT_BANK(lp, 0);
1808 val = SMC_CURRENT_BANK(); 1809 val = SMC_CURRENT_BANK(lp);
1809 if ((val & 0xFF00) != 0x3300) { 1810 if ((val & 0xFF00) != 0x3300) {
1810 retval = -ENODEV; 1811 retval = -ENODEV;
1811 goto err_out; 1812 goto err_out;
@@ -1817,8 +1818,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
1817 * register to bank 1, so I can access the base address 1818 * register to bank 1, so I can access the base address
1818 * register 1819 * register
1819 */ 1820 */
1820 SMC_SELECT_BANK(1); 1821 SMC_SELECT_BANK(lp, 1);
1821 val = SMC_GET_BASE(); 1822 val = SMC_GET_BASE(lp);
1822 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT; 1823 val = ((val & 0x1F00) >> 3) << SMC_IO_SHIFT;
1823 if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) { 1824 if (((unsigned int)ioaddr & (0x3e0 << SMC_IO_SHIFT)) != val) {
1824 printk("%s: IOADDR %p doesn't match configuration (%x).\n", 1825 printk("%s: IOADDR %p doesn't match configuration (%x).\n",
@@ -1830,8 +1831,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
1830 * recognize. These might need to be added to later, 1831 * recognize. These might need to be added to later,
1831 * as future revisions could be added. 1832 * as future revisions could be added.
1832 */ 1833 */
1833 SMC_SELECT_BANK(3); 1834 SMC_SELECT_BANK(lp, 3);
1834 revision_register = SMC_GET_REV(); 1835 revision_register = SMC_GET_REV(lp);
1835 DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register); 1836 DBG(2, "%s: revision = 0x%04x\n", CARDNAME, revision_register);
1836 version_string = chip_ids[ (revision_register >> 4) & 0xF]; 1837 version_string = chip_ids[ (revision_register >> 4) & 0xF];
1837 if (!version_string || (revision_register & 0xff00) != 0x3300) { 1838 if (!version_string || (revision_register & 0xff00) != 0x3300) {
@@ -1855,8 +1856,8 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
1855 spin_lock_init(&lp->lock); 1856 spin_lock_init(&lp->lock);
1856 1857
1857 /* Get the MAC address */ 1858 /* Get the MAC address */
1858 SMC_SELECT_BANK(1); 1859 SMC_SELECT_BANK(lp, 1);
1859 SMC_GET_MAC_ADDR(dev->dev_addr); 1860 SMC_GET_MAC_ADDR(lp, dev->dev_addr);
1860 1861
1861 /* now, reset the chip, and put it into a known state */ 1862 /* now, reset the chip, and put it into a known state */
1862 smc_reset(dev); 1863 smc_reset(dev);
@@ -1881,7 +1882,7 @@ static int __init smc_probe(struct net_device *dev, void __iomem *ioaddr,
1881 1882
1882 trials = 3; 1883 trials = 3;
1883 while (trials--) { 1884 while (trials--) {
1884 dev->irq = smc_findirq(ioaddr); 1885 dev->irq = smc_findirq(lp);
1885 if (dev->irq) 1886 if (dev->irq)
1886 break; 1887 break;
1887 /* kick the card and try again */ 1888 /* kick the card and try again */