diff options
author | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-09-13 13:24:59 -0400 |
commit | 6aa20a2235535605db6d6d2bd850298b2fe7f31e (patch) | |
tree | df0b855043407b831d57f2f2c271f8aab48444f4 /drivers/net/smc9194.h | |
parent | 7a291083225af6e22ffaa46b3d91cfc1a1ccaab4 (diff) |
drivers/net: Trim trailing whitespace
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/smc9194.h')
-rw-r--r-- | drivers/net/smc9194.h | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/drivers/net/smc9194.h b/drivers/net/smc9194.h index 393ab909bd86..cf69d0a5a1cb 100644 --- a/drivers/net/smc9194.h +++ b/drivers/net/smc9194.h | |||
@@ -1,18 +1,18 @@ | |||
1 | /*------------------------------------------------------------------------ | 1 | /*------------------------------------------------------------------------ |
2 | . smc9194.h | 2 | . smc9194.h |
3 | . Copyright (C) 1996 by Erik Stahlman | 3 | . Copyright (C) 1996 by Erik Stahlman |
4 | . | 4 | . |
5 | . This software may be used and distributed according to the terms | 5 | . This software may be used and distributed according to the terms |
6 | . of the GNU General Public License, incorporated herein by reference. | 6 | . of the GNU General Public License, incorporated herein by reference. |
7 | . | 7 | . |
8 | . This file contains register information and access macros for | 8 | . This file contains register information and access macros for |
9 | . the SMC91xxx chipset. | 9 | . the SMC91xxx chipset. |
10 | . | 10 | . |
11 | . Information contained in this file was obtained from the SMC91C94 | 11 | . Information contained in this file was obtained from the SMC91C94 |
12 | . manual from SMC. To get a copy, if you really want one, you can find | 12 | . manual from SMC. To get a copy, if you really want one, you can find |
13 | . information under www.smc.com in the components division. | 13 | . information under www.smc.com in the components division. |
14 | . ( this thanks to advice from Donald Becker ). | 14 | . ( this thanks to advice from Donald Becker ). |
15 | . | 15 | . |
16 | . Authors | 16 | . Authors |
17 | . Erik Stahlman ( erik@vt.edu ) | 17 | . Erik Stahlman ( erik@vt.edu ) |
18 | . | 18 | . |
@@ -38,22 +38,22 @@ typedef unsigned long int dword; | |||
38 | 38 | ||
39 | 39 | ||
40 | /*--------------------------------------------------------------- | 40 | /*--------------------------------------------------------------- |
41 | . | 41 | . |
42 | . A description of the SMC registers is probably in order here, | 42 | . A description of the SMC registers is probably in order here, |
43 | . although for details, the SMC datasheet is invaluable. | 43 | . although for details, the SMC datasheet is invaluable. |
44 | . | 44 | . |
45 | . Basically, the chip has 4 banks of registers ( 0 to 3 ), which | 45 | . Basically, the chip has 4 banks of registers ( 0 to 3 ), which |
46 | . are accessed by writing a number into the BANK_SELECT register | 46 | . are accessed by writing a number into the BANK_SELECT register |
47 | . ( I also use a SMC_SELECT_BANK macro for this ). | 47 | . ( I also use a SMC_SELECT_BANK macro for this ). |
48 | . | 48 | . |
49 | . The banks are configured so that for most purposes, bank 2 is all | 49 | . The banks are configured so that for most purposes, bank 2 is all |
50 | . that is needed for simple run time tasks. | 50 | . that is needed for simple run time tasks. |
51 | -----------------------------------------------------------------------*/ | 51 | -----------------------------------------------------------------------*/ |
52 | 52 | ||
53 | /* | 53 | /* |
54 | . Bank Select Register: | 54 | . Bank Select Register: |
55 | . | 55 | . |
56 | . yyyy yyyy 0000 00xx | 56 | . yyyy yyyy 0000 00xx |
57 | . xx = bank number | 57 | . xx = bank number |
58 | . yyyy yyyy = 0x33, for identification purposes. | 58 | . yyyy yyyy = 0x33, for identification purposes. |
59 | */ | 59 | */ |
@@ -62,23 +62,23 @@ typedef unsigned long int dword; | |||
62 | /* BANK 0 */ | 62 | /* BANK 0 */ |
63 | 63 | ||
64 | #define TCR 0 /* transmit control register */ | 64 | #define TCR 0 /* transmit control register */ |
65 | #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ | 65 | #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ |
66 | #define TCR_FDUPLX 0x0800 /* receive packets sent out */ | 66 | #define TCR_FDUPLX 0x0800 /* receive packets sent out */ |
67 | #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ | 67 | #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ |
68 | #define TCR_MON_CNS 0x0400 /* monitors the carrier status */ | 68 | #define TCR_MON_CNS 0x0400 /* monitors the carrier status */ |
69 | #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */ | 69 | #define TCR_PAD_ENABLE 0x0080 /* pads short packets to 64 bytes */ |
70 | 70 | ||
71 | #define TCR_CLEAR 0 /* do NOTHING */ | 71 | #define TCR_CLEAR 0 /* do NOTHING */ |
72 | /* the normal settings for the TCR register : */ | 72 | /* the normal settings for the TCR register : */ |
73 | /* QUESTION: do I want to enable padding of short packets ? */ | 73 | /* QUESTION: do I want to enable padding of short packets ? */ |
74 | #define TCR_NORMAL TCR_ENABLE | 74 | #define TCR_NORMAL TCR_ENABLE |
75 | 75 | ||
76 | 76 | ||
77 | #define EPH_STATUS 2 | 77 | #define EPH_STATUS 2 |
78 | #define ES_LINK_OK 0x4000 /* is the link integrity ok ? */ | 78 | #define ES_LINK_OK 0x4000 /* is the link integrity ok ? */ |
79 | 79 | ||
80 | #define RCR 4 | 80 | #define RCR 4 |
81 | #define RCR_SOFTRESET 0x8000 /* resets the chip */ | 81 | #define RCR_SOFTRESET 0x8000 /* resets the chip */ |
82 | #define RCR_STRIP_CRC 0x200 /* strips CRC */ | 82 | #define RCR_STRIP_CRC 0x200 /* strips CRC */ |
83 | #define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ | 83 | #define RCR_ENABLE 0x100 /* IFF this is set, we can receive packets */ |
84 | #define RCR_ALMUL 0x4 /* receive all multicast packets */ | 84 | #define RCR_ALMUL 0x4 /* receive all multicast packets */ |
@@ -114,12 +114,12 @@ typedef unsigned long int dword; | |||
114 | #define MC_BUSY 1 /* only readable bit in the register */ | 114 | #define MC_BUSY 1 /* only readable bit in the register */ |
115 | #define MC_NOP 0 | 115 | #define MC_NOP 0 |
116 | #define MC_ALLOC 0x20 /* or with number of 256 byte packets */ | 116 | #define MC_ALLOC 0x20 /* or with number of 256 byte packets */ |
117 | #define MC_RESET 0x40 | 117 | #define MC_RESET 0x40 |
118 | #define MC_REMOVE 0x60 /* remove the current rx packet */ | 118 | #define MC_REMOVE 0x60 /* remove the current rx packet */ |
119 | #define MC_RELEASE 0x80 /* remove and release the current rx packet */ | 119 | #define MC_RELEASE 0x80 /* remove and release the current rx packet */ |
120 | #define MC_FREEPKT 0xA0 /* Release packet in PNR register */ | 120 | #define MC_FREEPKT 0xA0 /* Release packet in PNR register */ |
121 | #define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ | 121 | #define MC_ENQUEUE 0xC0 /* Enqueue the packet for transmit */ |
122 | 122 | ||
123 | #define PNR_ARR 2 | 123 | #define PNR_ARR 2 |
124 | #define FIFO_PORTS 4 | 124 | #define FIFO_PORTS 4 |
125 | 125 | ||
@@ -139,11 +139,11 @@ typedef unsigned long int dword; | |||
139 | #define INT_MASK 13 | 139 | #define INT_MASK 13 |
140 | #define IM_RCV_INT 0x1 | 140 | #define IM_RCV_INT 0x1 |
141 | #define IM_TX_INT 0x2 | 141 | #define IM_TX_INT 0x2 |
142 | #define IM_TX_EMPTY_INT 0x4 | 142 | #define IM_TX_EMPTY_INT 0x4 |
143 | #define IM_ALLOC_INT 0x8 | 143 | #define IM_ALLOC_INT 0x8 |
144 | #define IM_RX_OVRN_INT 0x10 | 144 | #define IM_RX_OVRN_INT 0x10 |
145 | #define IM_EPH_INT 0x20 | 145 | #define IM_EPH_INT 0x20 |
146 | #define IM_ERCV_INT 0x40 /* not on SMC9192 */ | 146 | #define IM_ERCV_INT 0x40 /* not on SMC9192 */ |
147 | 147 | ||
148 | /* BANK 3 */ | 148 | /* BANK 3 */ |
149 | #define MULTICAST1 0 | 149 | #define MULTICAST1 0 |
@@ -162,19 +162,19 @@ typedef unsigned long int dword; | |||
162 | #define CHIP_9195 5 | 162 | #define CHIP_9195 5 |
163 | #define CHIP_91100 7 | 163 | #define CHIP_91100 7 |
164 | 164 | ||
165 | static const char * chip_ids[ 15 ] = { | 165 | static const char * chip_ids[ 15 ] = { |
166 | NULL, NULL, NULL, | 166 | NULL, NULL, NULL, |
167 | /* 3 */ "SMC91C90/91C92", | 167 | /* 3 */ "SMC91C90/91C92", |
168 | /* 4 */ "SMC91C94", | 168 | /* 4 */ "SMC91C94", |
169 | /* 5 */ "SMC91C95", | 169 | /* 5 */ "SMC91C95", |
170 | NULL, | 170 | NULL, |
171 | /* 7 */ "SMC91C100", | 171 | /* 7 */ "SMC91C100", |
172 | /* 8 */ "SMC91C100FD", | 172 | /* 8 */ "SMC91C100FD", |
173 | NULL, NULL, NULL, | 173 | NULL, NULL, NULL, |
174 | NULL, NULL, NULL}; | 174 | NULL, NULL, NULL}; |
175 | 175 | ||
176 | /* | 176 | /* |
177 | . Transmit status bits | 177 | . Transmit status bits |
178 | */ | 178 | */ |
179 | #define TS_SUCCESS 0x0001 | 179 | #define TS_SUCCESS 0x0001 |
180 | #define TS_LOSTCAR 0x0400 | 180 | #define TS_LOSTCAR 0x0400 |
@@ -190,18 +190,18 @@ static const char * chip_ids[ 15 ] = { | |||
190 | #define RS_TOOLONG 0x0800 | 190 | #define RS_TOOLONG 0x0800 |
191 | #define RS_TOOSHORT 0x0400 | 191 | #define RS_TOOSHORT 0x0400 |
192 | #define RS_MULTICAST 0x0001 | 192 | #define RS_MULTICAST 0x0001 |
193 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) | 193 | #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) |
194 | 194 | ||
195 | static const char * interfaces[ 2 ] = { "TP", "AUI" }; | 195 | static const char * interfaces[ 2 ] = { "TP", "AUI" }; |
196 | 196 | ||
197 | /*------------------------------------------------------------------------- | 197 | /*------------------------------------------------------------------------- |
198 | . I define some macros to make it easier to do somewhat common | 198 | . I define some macros to make it easier to do somewhat common |
199 | . or slightly complicated, repeated tasks. | 199 | . or slightly complicated, repeated tasks. |
200 | --------------------------------------------------------------------------*/ | 200 | --------------------------------------------------------------------------*/ |
201 | 201 | ||
202 | /* select a register bank, 0 to 3 */ | 202 | /* select a register bank, 0 to 3 */ |
203 | 203 | ||
204 | #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); } | 204 | #define SMC_SELECT_BANK(x) { outw( x, ioaddr + BANK_SELECT ); } |
205 | 205 | ||
206 | /* define a small delay for the reset */ | 206 | /* define a small delay for the reset */ |
207 | #define SMC_DELAY() { inw( ioaddr + RCR );\ | 207 | #define SMC_DELAY() { inw( ioaddr + RCR );\ |
@@ -229,13 +229,13 @@ static const char * interfaces[ 2 ] = { "TP", "AUI" }; | |||
229 | 229 | ||
230 | /*---------------------------------------------------------------------- | 230 | /*---------------------------------------------------------------------- |
231 | . Define the interrupts that I want to receive from the card | 231 | . Define the interrupts that I want to receive from the card |
232 | . | 232 | . |
233 | . I want: | 233 | . I want: |
234 | . IM_EPH_INT, for nasty errors | 234 | . IM_EPH_INT, for nasty errors |
235 | . IM_RCV_INT, for happy received packets | 235 | . IM_RCV_INT, for happy received packets |
236 | . IM_RX_OVRN_INT, because I have to kick the receiver | 236 | . IM_RX_OVRN_INT, because I have to kick the receiver |
237 | --------------------------------------------------------------------------*/ | 237 | --------------------------------------------------------------------------*/ |
238 | #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT) | 238 | #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT) |
239 | 239 | ||
240 | #endif /* _SMC_9194_H_ */ | 240 | #endif /* _SMC_9194_H_ */ |
241 | 241 | ||