aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/smc911x.h
diff options
context:
space:
mode:
authorMagnus Damm <magnus.damm@gmail.com>2008-06-09 19:33:54 -0400
committerJeff Garzik <jgarzik@redhat.com>2008-06-11 21:58:09 -0400
commit699559f84bee8b630c1d16fe1bc8e9667d170d65 (patch)
treec87edc5d98d39bebbba076bb799f57108dc77a6b /drivers/net/smc911x.h
parent9961530a5f017afae6a928672840617103bea118 (diff)
smc911x: pass along private data and use iomem
This patch contains changes needed for platform data support: - Move smc911x_local structure to header file - Pass along smc911x_local structure pointer to macros - Keep register base address in smc911x_local structure - Remove unused ioaddr variables [m.kozlowski@tuxland.pl: Parenthesis fix in drivers/net/smc911x.h] Signed-off-by: Magnus Damm <damm@igel.co.jp> Cc: Jeff Garzik <jeff@garzik.org> Cc: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
Diffstat (limited to 'drivers/net/smc911x.h')
-rw-r--r--drivers/net/smc911x.h351
1 files changed, 199 insertions, 152 deletions
diff --git a/drivers/net/smc911x.h b/drivers/net/smc911x.h
index 2b06e5087e36..271a3e8cf683 100644
--- a/drivers/net/smc911x.h
+++ b/drivers/net/smc911x.h
@@ -44,31 +44,78 @@
44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW 44 #define SMC_IRQ_SENSE IRQF_TRIGGER_LOW
45#endif 45#endif
46 46
47/* store this information for the driver.. */
48struct smc911x_local {
49 /*
50 * If I have to wait until the DMA is finished and ready to reload a
51 * packet, I will store the skbuff here. Then, the DMA will send it
52 * out and free it.
53 */
54 struct sk_buff *pending_tx_skb;
55
56 /* version/revision of the SMC911x chip */
57 u16 version;
58 u16 revision;
59
60 /* FIFO sizes */
61 int tx_fifo_kb;
62 int tx_fifo_size;
63 int rx_fifo_size;
64 int afc_cfg;
65
66 /* Contains the current active receive/phy mode */
67 int ctl_rfduplx;
68 int ctl_rspeed;
69
70 u32 msg_enable;
71 u32 phy_type;
72 struct mii_if_info mii;
73
74 /* work queue */
75 struct work_struct phy_configure;
76 int work_pending;
77
78 int tx_throttle;
79 spinlock_t lock;
80
81 struct net_device *netdev;
82
83#ifdef SMC_USE_DMA
84 /* DMA needs the physical address of the chip */
85 u_long physaddr;
86 int rxdma;
87 int txdma;
88 int rxdma_active;
89 int txdma_active;
90 struct sk_buff *current_rx_skb;
91 struct sk_buff *current_tx_skb;
92 struct device *dev;
93#endif
94 void __iomem *base;
95};
47 96
48/* 97/*
49 * Define the bus width specific IO macros 98 * Define the bus width specific IO macros
50 */ 99 */
51 100
52#if SMC_USE_16BIT 101#if SMC_USE_16BIT
53#define SMC_inl(a, r) (readw((a) + (r)) & 0xFFFF) + (readw((a) + (r) + 2) << 16)) 102#define SMC_inl(lp, r) ((readw((lp)->base + (r)) & 0xFFFF) + (readw((lp)->base + (r) + 2) << 16))
54#define SMC_outl(v, a, r) \ 103#define SMC_outl(v, lp, r) \
55 do{ \ 104 do{ \
56 writew(v & 0xFFFF, (a) + (r)); \ 105 writew(v & 0xFFFF, (lp)->base + (r)); \
57 writew(v >> 16, (a) + (r) + 2); \ 106 writew(v >> 16, (lp)->base + (r) + 2); \
58 } while (0) 107 } while (0)
59#define SMC_insl(a, r, p, l) readsw((short*)((a) + (r)), p, l*2) 108#define SMC_insl(lp, r, p, l) readsw((short*)((lp)->base + (r)), p, l*2)
60#define SMC_outsl(a, r, p, l) writesw((short*)((a) + (r)), p, l*2) 109#define SMC_outsl(lp, r, p, l) writesw((short*)((lp)->base + (r)), p, l*2)
61 110
62#elif SMC_USE_32BIT 111#elif SMC_USE_32BIT
63#define SMC_inl(a, r) readl((a) + (r)) 112#define SMC_inl(lp, r) readl((lp)->base + (r))
64#define SMC_outl(v, a, r) writel(v, (a) + (r)) 113#define SMC_outl(v, lp, r) writel(v, (lp)->base + (r))
65#define SMC_insl(a, r, p, l) readsl((int*)((a) + (r)), p, l) 114#define SMC_insl(lp, r, p, l) readsl((int*)((lp)->base + (r)), p, l)
66#define SMC_outsl(a, r, p, l) writesl((int*)((a) + (r)), p, l) 115#define SMC_outsl(lp, r, p, l) writesl((int*)((lp)->base + (r)), p, l)
67 116
68#endif /* SMC_USE_16BIT */ 117#endif /* SMC_USE_16BIT */
69 118
70
71
72#ifdef SMC_USE_PXA_DMA 119#ifdef SMC_USE_PXA_DMA
73#define SMC_USE_DMA 120#define SMC_USE_DMA
74 121
@@ -103,22 +150,22 @@ static int rx_dmalen, tx_dmalen;
103 150
104#ifdef SMC_insl 151#ifdef SMC_insl
105#undef SMC_insl 152#undef SMC_insl
106#define SMC_insl(a, r, p, l) \ 153#define SMC_insl(lp, r, p, l) \
107 smc_pxa_dma_insl(lp->dev, a, lp->physaddr, r, lp->rxdma, p, l) 154 smc_pxa_dma_insl(lp, lp->physaddr, r, lp->rxdma, p, l)
108 155
109static inline void 156static inline void
110smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr, 157smc_pxa_dma_insl(struct smc911x_local *lp, u_long physaddr,
111 int reg, int dma, u_char *buf, int len) 158 int reg, int dma, u_char *buf, int len)
112{ 159{
113 /* 64 bit alignment is required for memory to memory DMA */ 160 /* 64 bit alignment is required for memory to memory DMA */
114 if ((long)buf & 4) { 161 if ((long)buf & 4) {
115 *((u32 *)buf) = SMC_inl(ioaddr, reg); 162 *((u32 *)buf) = SMC_inl(lp, reg);
116 buf += 4; 163 buf += 4;
117 len--; 164 len--;
118 } 165 }
119 166
120 len *= 4; 167 len *= 4;
121 rx_dmabuf = dma_map_single(dev, buf, len, DMA_FROM_DEVICE); 168 rx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_FROM_DEVICE);
122 rx_dmalen = len; 169 rx_dmalen = len;
123 DCSR(dma) = DCSR_NODESC; 170 DCSR(dma) = DCSR_NODESC;
124 DTADR(dma) = rx_dmabuf; 171 DTADR(dma) = rx_dmabuf;
@@ -131,22 +178,22 @@ smc_pxa_dma_insl(struct device *dev, u_long ioaddr, u_long physaddr,
131 178
132#ifdef SMC_outsl 179#ifdef SMC_outsl
133#undef SMC_outsl 180#undef SMC_outsl
134#define SMC_outsl(a, r, p, l) \ 181#define SMC_outsl(lp, r, p, l) \
135 smc_pxa_dma_outsl(lp->dev, a, lp->physaddr, r, lp->txdma, p, l) 182 smc_pxa_dma_outsl(lp, lp->physaddr, r, lp->txdma, p, l)
136 183
137static inline void 184static inline void
138smc_pxa_dma_outsl(struct device *dev, u_long ioaddr, u_long physaddr, 185smc_pxa_dma_outsl(struct smc911x_local *lp, u_long physaddr,
139 int reg, int dma, u_char *buf, int len) 186 int reg, int dma, u_char *buf, int len)
140{ 187{
141 /* 64 bit alignment is required for memory to memory DMA */ 188 /* 64 bit alignment is required for memory to memory DMA */
142 if ((long)buf & 4) { 189 if ((long)buf & 4) {
143 SMC_outl(*((u32 *)buf), ioaddr, reg); 190 SMC_outl(*((u32 *)buf), lp, reg);
144 buf += 4; 191 buf += 4;
145 len--; 192 len--;
146 } 193 }
147 194
148 len *= 4; 195 len *= 4;
149 tx_dmabuf = dma_map_single(dev, buf, len, DMA_TO_DEVICE); 196 tx_dmabuf = dma_map_single(lp->dev, buf, len, DMA_TO_DEVICE);
150 tx_dmalen = len; 197 tx_dmalen = len;
151 DCSR(dma) = DCSR_NODESC; 198 DCSR(dma) = DCSR_NODESC;
152 DSADR(dma) = tx_dmabuf; 199 DSADR(dma) = tx_dmabuf;
@@ -565,213 +612,213 @@ static const struct chip_id chip_ids[] = {
565 * capabilities. Please use those and not the in/out primitives. 612 * capabilities. Please use those and not the in/out primitives.
566 */ 613 */
567/* FIFO read/write macros */ 614/* FIFO read/write macros */
568#define SMC_PUSH_DATA(p, l) SMC_outsl( ioaddr, TX_DATA_FIFO, p, (l) >> 2 ) 615#define SMC_PUSH_DATA(lp, p, l) SMC_outsl( lp, TX_DATA_FIFO, p, (l) >> 2 )
569#define SMC_PULL_DATA(p, l) SMC_insl ( ioaddr, RX_DATA_FIFO, p, (l) >> 2 ) 616#define SMC_PULL_DATA(lp, p, l) SMC_insl ( lp, RX_DATA_FIFO, p, (l) >> 2 )
570#define SMC_SET_TX_FIFO(x) SMC_outl( x, ioaddr, TX_DATA_FIFO ) 617#define SMC_SET_TX_FIFO(lp, x) SMC_outl( x, lp, TX_DATA_FIFO )
571#define SMC_GET_RX_FIFO() SMC_inl( ioaddr, RX_DATA_FIFO ) 618#define SMC_GET_RX_FIFO(lp) SMC_inl( lp, RX_DATA_FIFO )
572 619
573 620
574/* I/O mapped register read/write macros */ 621/* I/O mapped register read/write macros */
575#define SMC_GET_TX_STS_FIFO() SMC_inl( ioaddr, TX_STATUS_FIFO ) 622#define SMC_GET_TX_STS_FIFO(lp) SMC_inl( lp, TX_STATUS_FIFO )
576#define SMC_GET_RX_STS_FIFO() SMC_inl( ioaddr, RX_STATUS_FIFO ) 623#define SMC_GET_RX_STS_FIFO(lp) SMC_inl( lp, RX_STATUS_FIFO )
577#define SMC_GET_RX_STS_FIFO_PEEK() SMC_inl( ioaddr, RX_STATUS_FIFO_PEEK ) 624#define SMC_GET_RX_STS_FIFO_PEEK(lp) SMC_inl( lp, RX_STATUS_FIFO_PEEK )
578#define SMC_GET_PN() (SMC_inl( ioaddr, ID_REV ) >> 16) 625#define SMC_GET_PN(lp) (SMC_inl( lp, ID_REV ) >> 16)
579#define SMC_GET_REV() (SMC_inl( ioaddr, ID_REV ) & 0xFFFF) 626#define SMC_GET_REV(lp) (SMC_inl( lp, ID_REV ) & 0xFFFF)
580#define SMC_GET_IRQ_CFG() SMC_inl( ioaddr, INT_CFG ) 627#define SMC_GET_IRQ_CFG(lp) SMC_inl( lp, INT_CFG )
581#define SMC_SET_IRQ_CFG(x) SMC_outl( x, ioaddr, INT_CFG ) 628#define SMC_SET_IRQ_CFG(lp, x) SMC_outl( x, lp, INT_CFG )
582#define SMC_GET_INT() SMC_inl( ioaddr, INT_STS ) 629#define SMC_GET_INT(lp) SMC_inl( lp, INT_STS )
583#define SMC_ACK_INT(x) SMC_outl( x, ioaddr, INT_STS ) 630#define SMC_ACK_INT(lp, x) SMC_outl( x, lp, INT_STS )
584#define SMC_GET_INT_EN() SMC_inl( ioaddr, INT_EN ) 631#define SMC_GET_INT_EN(lp) SMC_inl( lp, INT_EN )
585#define SMC_SET_INT_EN(x) SMC_outl( x, ioaddr, INT_EN ) 632#define SMC_SET_INT_EN(lp, x) SMC_outl( x, lp, INT_EN )
586#define SMC_GET_BYTE_TEST() SMC_inl( ioaddr, BYTE_TEST ) 633#define SMC_GET_BYTE_TEST(lp) SMC_inl( lp, BYTE_TEST )
587#define SMC_SET_BYTE_TEST(x) SMC_outl( x, ioaddr, BYTE_TEST ) 634#define SMC_SET_BYTE_TEST(lp, x) SMC_outl( x, lp, BYTE_TEST )
588#define SMC_GET_FIFO_INT() SMC_inl( ioaddr, FIFO_INT ) 635#define SMC_GET_FIFO_INT(lp) SMC_inl( lp, FIFO_INT )
589#define SMC_SET_FIFO_INT(x) SMC_outl( x, ioaddr, FIFO_INT ) 636#define SMC_SET_FIFO_INT(lp, x) SMC_outl( x, lp, FIFO_INT )
590#define SMC_SET_FIFO_TDA(x) \ 637#define SMC_SET_FIFO_TDA(lp, x) \
591 do { \ 638 do { \
592 unsigned long __flags; \ 639 unsigned long __flags; \
593 int __mask; \ 640 int __mask; \
594 local_irq_save(__flags); \ 641 local_irq_save(__flags); \
595 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<24); \ 642 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<24); \
596 SMC_SET_FIFO_INT( __mask | (x)<<24 ); \ 643 SMC_SET_FIFO_INT( (lp), __mask | (x)<<24 ); \
597 local_irq_restore(__flags); \ 644 local_irq_restore(__flags); \
598 } while (0) 645 } while (0)
599#define SMC_SET_FIFO_TSL(x) \ 646#define SMC_SET_FIFO_TSL(lp, x) \
600 do { \ 647 do { \
601 unsigned long __flags; \ 648 unsigned long __flags; \
602 int __mask; \ 649 int __mask; \
603 local_irq_save(__flags); \ 650 local_irq_save(__flags); \
604 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<16); \ 651 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<16); \
605 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<16)); \ 652 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<16)); \
606 local_irq_restore(__flags); \ 653 local_irq_restore(__flags); \
607 } while (0) 654 } while (0)
608#define SMC_SET_FIFO_RSA(x) \ 655#define SMC_SET_FIFO_RSA(lp, x) \
609 do { \ 656 do { \
610 unsigned long __flags; \ 657 unsigned long __flags; \
611 int __mask; \ 658 int __mask; \
612 local_irq_save(__flags); \ 659 local_irq_save(__flags); \
613 __mask = SMC_GET_FIFO_INT() & ~(0xFF<<8); \ 660 __mask = SMC_GET_FIFO_INT((lp)) & ~(0xFF<<8); \
614 SMC_SET_FIFO_INT( __mask | (((x) & 0xFF)<<8)); \ 661 SMC_SET_FIFO_INT( (lp), __mask | (((x) & 0xFF)<<8)); \
615 local_irq_restore(__flags); \ 662 local_irq_restore(__flags); \
616 } while (0) 663 } while (0)
617#define SMC_SET_FIFO_RSL(x) \ 664#define SMC_SET_FIFO_RSL(lp, x) \
618 do { \ 665 do { \
619 unsigned long __flags; \ 666 unsigned long __flags; \
620 int __mask; \ 667 int __mask; \
621 local_irq_save(__flags); \ 668 local_irq_save(__flags); \
622 __mask = SMC_GET_FIFO_INT() & ~0xFF; \ 669 __mask = SMC_GET_FIFO_INT((lp)) & ~0xFF; \
623 SMC_SET_FIFO_INT( __mask | ((x) & 0xFF)); \ 670 SMC_SET_FIFO_INT( (lp),__mask | ((x) & 0xFF)); \
624 local_irq_restore(__flags); \ 671 local_irq_restore(__flags); \
625 } while (0) 672 } while (0)
626#define SMC_GET_RX_CFG() SMC_inl( ioaddr, RX_CFG ) 673#define SMC_GET_RX_CFG(lp) SMC_inl( lp, RX_CFG )
627#define SMC_SET_RX_CFG(x) SMC_outl( x, ioaddr, RX_CFG ) 674#define SMC_SET_RX_CFG(lp, x) SMC_outl( x, lp, RX_CFG )
628#define SMC_GET_TX_CFG() SMC_inl( ioaddr, TX_CFG ) 675#define SMC_GET_TX_CFG(lp) SMC_inl( lp, TX_CFG )
629#define SMC_SET_TX_CFG(x) SMC_outl( x, ioaddr, TX_CFG ) 676#define SMC_SET_TX_CFG(lp, x) SMC_outl( x, lp, TX_CFG )
630#define SMC_GET_HW_CFG() SMC_inl( ioaddr, HW_CFG ) 677#define SMC_GET_HW_CFG(lp) SMC_inl( lp, HW_CFG )
631#define SMC_SET_HW_CFG(x) SMC_outl( x, ioaddr, HW_CFG ) 678#define SMC_SET_HW_CFG(lp, x) SMC_outl( x, lp, HW_CFG )
632#define SMC_GET_RX_DP_CTRL() SMC_inl( ioaddr, RX_DP_CTRL ) 679#define SMC_GET_RX_DP_CTRL(lp) SMC_inl( lp, RX_DP_CTRL )
633#define SMC_SET_RX_DP_CTRL(x) SMC_outl( x, ioaddr, RX_DP_CTRL ) 680#define SMC_SET_RX_DP_CTRL(lp, x) SMC_outl( x, lp, RX_DP_CTRL )
634#define SMC_GET_PMT_CTRL() SMC_inl( ioaddr, PMT_CTRL ) 681#define SMC_GET_PMT_CTRL(lp) SMC_inl( lp, PMT_CTRL )
635#define SMC_SET_PMT_CTRL(x) SMC_outl( x, ioaddr, PMT_CTRL ) 682#define SMC_SET_PMT_CTRL(lp, x) SMC_outl( x, lp, PMT_CTRL )
636#define SMC_GET_GPIO_CFG() SMC_inl( ioaddr, GPIO_CFG ) 683#define SMC_GET_GPIO_CFG(lp) SMC_inl( lp, GPIO_CFG )
637#define SMC_SET_GPIO_CFG(x) SMC_outl( x, ioaddr, GPIO_CFG ) 684#define SMC_SET_GPIO_CFG(lp, x) SMC_outl( x, lp, GPIO_CFG )
638#define SMC_GET_RX_FIFO_INF() SMC_inl( ioaddr, RX_FIFO_INF ) 685#define SMC_GET_RX_FIFO_INF(lp) SMC_inl( lp, RX_FIFO_INF )
639#define SMC_SET_RX_FIFO_INF(x) SMC_outl( x, ioaddr, RX_FIFO_INF ) 686#define SMC_SET_RX_FIFO_INF(lp, x) SMC_outl( x, lp, RX_FIFO_INF )
640#define SMC_GET_TX_FIFO_INF() SMC_inl( ioaddr, TX_FIFO_INF ) 687#define SMC_GET_TX_FIFO_INF(lp) SMC_inl( lp, TX_FIFO_INF )
641#define SMC_SET_TX_FIFO_INF(x) SMC_outl( x, ioaddr, TX_FIFO_INF ) 688#define SMC_SET_TX_FIFO_INF(lp, x) SMC_outl( x, lp, TX_FIFO_INF )
642#define SMC_GET_GPT_CFG() SMC_inl( ioaddr, GPT_CFG ) 689#define SMC_GET_GPT_CFG(lp) SMC_inl( lp, GPT_CFG )
643#define SMC_SET_GPT_CFG(x) SMC_outl( x, ioaddr, GPT_CFG ) 690#define SMC_SET_GPT_CFG(lp, x) SMC_outl( x, lp, GPT_CFG )
644#define SMC_GET_RX_DROP() SMC_inl( ioaddr, RX_DROP ) 691#define SMC_GET_RX_DROP(lp) SMC_inl( lp, RX_DROP )
645#define SMC_SET_RX_DROP(x) SMC_outl( x, ioaddr, RX_DROP ) 692#define SMC_SET_RX_DROP(lp, x) SMC_outl( x, lp, RX_DROP )
646#define SMC_GET_MAC_CMD() SMC_inl( ioaddr, MAC_CSR_CMD ) 693#define SMC_GET_MAC_CMD(lp) SMC_inl( lp, MAC_CSR_CMD )
647#define SMC_SET_MAC_CMD(x) SMC_outl( x, ioaddr, MAC_CSR_CMD ) 694#define SMC_SET_MAC_CMD(lp, x) SMC_outl( x, lp, MAC_CSR_CMD )
648#define SMC_GET_MAC_DATA() SMC_inl( ioaddr, MAC_CSR_DATA ) 695#define SMC_GET_MAC_DATA(lp) SMC_inl( lp, MAC_CSR_DATA )
649#define SMC_SET_MAC_DATA(x) SMC_outl( x, ioaddr, MAC_CSR_DATA ) 696#define SMC_SET_MAC_DATA(lp, x) SMC_outl( x, lp, MAC_CSR_DATA )
650#define SMC_GET_AFC_CFG() SMC_inl( ioaddr, AFC_CFG ) 697#define SMC_GET_AFC_CFG(lp) SMC_inl( lp, AFC_CFG )
651#define SMC_SET_AFC_CFG(x) SMC_outl( x, ioaddr, AFC_CFG ) 698#define SMC_SET_AFC_CFG(lp, x) SMC_outl( x, lp, AFC_CFG )
652#define SMC_GET_E2P_CMD() SMC_inl( ioaddr, E2P_CMD ) 699#define SMC_GET_E2P_CMD(lp) SMC_inl( lp, E2P_CMD )
653#define SMC_SET_E2P_CMD(x) SMC_outl( x, ioaddr, E2P_CMD ) 700#define SMC_SET_E2P_CMD(lp, x) SMC_outl( x, lp, E2P_CMD )
654#define SMC_GET_E2P_DATA() SMC_inl( ioaddr, E2P_DATA ) 701#define SMC_GET_E2P_DATA(lp) SMC_inl( lp, E2P_DATA )
655#define SMC_SET_E2P_DATA(x) SMC_outl( x, ioaddr, E2P_DATA ) 702#define SMC_SET_E2P_DATA(lp, x) SMC_outl( x, lp, E2P_DATA )
656 703
657/* MAC register read/write macros */ 704/* MAC register read/write macros */
658#define SMC_GET_MAC_CSR(a,v) \ 705#define SMC_GET_MAC_CSR(lp,a,v) \
659 do { \ 706 do { \
660 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 707 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
661 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | \ 708 SMC_SET_MAC_CMD((lp),MAC_CSR_CMD_CSR_BUSY_ | \
662 MAC_CSR_CMD_R_NOT_W_ | (a) ); \ 709 MAC_CSR_CMD_R_NOT_W_ | (a) ); \
663 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 710 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
664 v = SMC_GET_MAC_DATA(); \ 711 v = SMC_GET_MAC_DATA((lp)); \
665 } while (0) 712 } while (0)
666#define SMC_SET_MAC_CSR(a,v) \ 713#define SMC_SET_MAC_CSR(lp,a,v) \
667 do { \ 714 do { \
668 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 715 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
669 SMC_SET_MAC_DATA(v); \ 716 SMC_SET_MAC_DATA((lp), v); \
670 SMC_SET_MAC_CMD(MAC_CSR_CMD_CSR_BUSY_ | (a) ); \ 717 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_CSR_BUSY_ | (a) ); \
671 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 718 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
672 } while (0) 719 } while (0)
673#define SMC_GET_MAC_CR(x) SMC_GET_MAC_CSR( MAC_CR, x ) 720#define SMC_GET_MAC_CR(lp, x) SMC_GET_MAC_CSR( (lp), MAC_CR, x )
674#define SMC_SET_MAC_CR(x) SMC_SET_MAC_CSR( MAC_CR, x ) 721#define SMC_SET_MAC_CR(lp, x) SMC_SET_MAC_CSR( (lp), MAC_CR, x )
675#define SMC_GET_ADDRH(x) SMC_GET_MAC_CSR( ADDRH, x ) 722#define SMC_GET_ADDRH(lp, x) SMC_GET_MAC_CSR( (lp), ADDRH, x )
676#define SMC_SET_ADDRH(x) SMC_SET_MAC_CSR( ADDRH, x ) 723#define SMC_SET_ADDRH(lp, x) SMC_SET_MAC_CSR( (lp), ADDRH, x )
677#define SMC_GET_ADDRL(x) SMC_GET_MAC_CSR( ADDRL, x ) 724#define SMC_GET_ADDRL(lp, x) SMC_GET_MAC_CSR( (lp), ADDRL, x )
678#define SMC_SET_ADDRL(x) SMC_SET_MAC_CSR( ADDRL, x ) 725#define SMC_SET_ADDRL(lp, x) SMC_SET_MAC_CSR( (lp), ADDRL, x )
679#define SMC_GET_HASHH(x) SMC_GET_MAC_CSR( HASHH, x ) 726#define SMC_GET_HASHH(lp, x) SMC_GET_MAC_CSR( (lp), HASHH, x )
680#define SMC_SET_HASHH(x) SMC_SET_MAC_CSR( HASHH, x ) 727#define SMC_SET_HASHH(lp, x) SMC_SET_MAC_CSR( (lp), HASHH, x )
681#define SMC_GET_HASHL(x) SMC_GET_MAC_CSR( HASHL, x ) 728#define SMC_GET_HASHL(lp, x) SMC_GET_MAC_CSR( (lp), HASHL, x )
682#define SMC_SET_HASHL(x) SMC_SET_MAC_CSR( HASHL, x ) 729#define SMC_SET_HASHL(lp, x) SMC_SET_MAC_CSR( (lp), HASHL, x )
683#define SMC_GET_MII_ACC(x) SMC_GET_MAC_CSR( MII_ACC, x ) 730#define SMC_GET_MII_ACC(lp, x) SMC_GET_MAC_CSR( (lp), MII_ACC, x )
684#define SMC_SET_MII_ACC(x) SMC_SET_MAC_CSR( MII_ACC, x ) 731#define SMC_SET_MII_ACC(lp, x) SMC_SET_MAC_CSR( (lp), MII_ACC, x )
685#define SMC_GET_MII_DATA(x) SMC_GET_MAC_CSR( MII_DATA, x ) 732#define SMC_GET_MII_DATA(lp, x) SMC_GET_MAC_CSR( (lp), MII_DATA, x )
686#define SMC_SET_MII_DATA(x) SMC_SET_MAC_CSR( MII_DATA, x ) 733#define SMC_SET_MII_DATA(lp, x) SMC_SET_MAC_CSR( (lp), MII_DATA, x )
687#define SMC_GET_FLOW(x) SMC_GET_MAC_CSR( FLOW, x ) 734#define SMC_GET_FLOW(lp, x) SMC_GET_MAC_CSR( (lp), FLOW, x )
688#define SMC_SET_FLOW(x) SMC_SET_MAC_CSR( FLOW, x ) 735#define SMC_SET_FLOW(lp, x) SMC_SET_MAC_CSR( (lp), FLOW, x )
689#define SMC_GET_VLAN1(x) SMC_GET_MAC_CSR( VLAN1, x ) 736#define SMC_GET_VLAN1(lp, x) SMC_GET_MAC_CSR( (lp), VLAN1, x )
690#define SMC_SET_VLAN1(x) SMC_SET_MAC_CSR( VLAN1, x ) 737#define SMC_SET_VLAN1(lp, x) SMC_SET_MAC_CSR( (lp), VLAN1, x )
691#define SMC_GET_VLAN2(x) SMC_GET_MAC_CSR( VLAN2, x ) 738#define SMC_GET_VLAN2(lp, x) SMC_GET_MAC_CSR( (lp), VLAN2, x )
692#define SMC_SET_VLAN2(x) SMC_SET_MAC_CSR( VLAN2, x ) 739#define SMC_SET_VLAN2(lp, x) SMC_SET_MAC_CSR( (lp), VLAN2, x )
693#define SMC_SET_WUFF(x) SMC_SET_MAC_CSR( WUFF, x ) 740#define SMC_SET_WUFF(lp, x) SMC_SET_MAC_CSR( (lp), WUFF, x )
694#define SMC_GET_WUCSR(x) SMC_GET_MAC_CSR( WUCSR, x ) 741#define SMC_GET_WUCSR(lp, x) SMC_GET_MAC_CSR( (lp), WUCSR, x )
695#define SMC_SET_WUCSR(x) SMC_SET_MAC_CSR( WUCSR, x ) 742#define SMC_SET_WUCSR(lp, x) SMC_SET_MAC_CSR( (lp), WUCSR, x )
696 743
697/* PHY register read/write macros */ 744/* PHY register read/write macros */
698#define SMC_GET_MII(a,phy,v) \ 745#define SMC_GET_MII(lp,a,phy,v) \
699 do { \ 746 do { \
700 u32 __v; \ 747 u32 __v; \
701 do { \ 748 do { \
702 SMC_GET_MII_ACC(__v); \ 749 SMC_GET_MII_ACC((lp), __v); \
703 } while ( __v & MII_ACC_MII_BUSY_ ); \ 750 } while ( __v & MII_ACC_MII_BUSY_ ); \
704 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 751 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
705 MII_ACC_MII_BUSY_); \ 752 MII_ACC_MII_BUSY_); \
706 do { \ 753 do { \
707 SMC_GET_MII_ACC(__v); \ 754 SMC_GET_MII_ACC( (lp), __v); \
708 } while ( __v & MII_ACC_MII_BUSY_ ); \ 755 } while ( __v & MII_ACC_MII_BUSY_ ); \
709 SMC_GET_MII_DATA(v); \ 756 SMC_GET_MII_DATA((lp), v); \
710 } while (0) 757 } while (0)
711#define SMC_SET_MII(a,phy,v) \ 758#define SMC_SET_MII(lp,a,phy,v) \
712 do { \ 759 do { \
713 u32 __v; \ 760 u32 __v; \
714 do { \ 761 do { \
715 SMC_GET_MII_ACC(__v); \ 762 SMC_GET_MII_ACC((lp), __v); \
716 } while ( __v & MII_ACC_MII_BUSY_ ); \ 763 } while ( __v & MII_ACC_MII_BUSY_ ); \
717 SMC_SET_MII_DATA(v); \ 764 SMC_SET_MII_DATA((lp), v); \
718 SMC_SET_MII_ACC( ((phy)<<11) | ((a)<<6) | \ 765 SMC_SET_MII_ACC( (lp), ((phy)<<11) | ((a)<<6) | \
719 MII_ACC_MII_BUSY_ | \ 766 MII_ACC_MII_BUSY_ | \
720 MII_ACC_MII_WRITE_ ); \ 767 MII_ACC_MII_WRITE_ ); \
721 do { \ 768 do { \
722 SMC_GET_MII_ACC(__v); \ 769 SMC_GET_MII_ACC((lp), __v); \
723 } while ( __v & MII_ACC_MII_BUSY_ ); \ 770 } while ( __v & MII_ACC_MII_BUSY_ ); \
724 } while (0) 771 } while (0)
725#define SMC_GET_PHY_BMCR(phy,x) SMC_GET_MII( MII_BMCR, phy, x ) 772#define SMC_GET_PHY_BMCR(lp,phy,x) SMC_GET_MII( (lp), MII_BMCR, phy, x )
726#define SMC_SET_PHY_BMCR(phy,x) SMC_SET_MII( MII_BMCR, phy, x ) 773#define SMC_SET_PHY_BMCR(lp,phy,x) SMC_SET_MII( (lp), MII_BMCR, phy, x )
727#define SMC_GET_PHY_BMSR(phy,x) SMC_GET_MII( MII_BMSR, phy, x ) 774#define SMC_GET_PHY_BMSR(lp,phy,x) SMC_GET_MII( (lp), MII_BMSR, phy, x )
728#define SMC_GET_PHY_ID1(phy,x) SMC_GET_MII( MII_PHYSID1, phy, x ) 775#define SMC_GET_PHY_ID1(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID1, phy, x )
729#define SMC_GET_PHY_ID2(phy,x) SMC_GET_MII( MII_PHYSID2, phy, x ) 776#define SMC_GET_PHY_ID2(lp,phy,x) SMC_GET_MII( (lp), MII_PHYSID2, phy, x )
730#define SMC_GET_PHY_MII_ADV(phy,x) SMC_GET_MII( MII_ADVERTISE, phy, x ) 777#define SMC_GET_PHY_MII_ADV(lp,phy,x) SMC_GET_MII( (lp), MII_ADVERTISE, phy, x )
731#define SMC_SET_PHY_MII_ADV(phy,x) SMC_SET_MII( MII_ADVERTISE, phy, x ) 778#define SMC_SET_PHY_MII_ADV(lp,phy,x) SMC_SET_MII( (lp), MII_ADVERTISE, phy, x )
732#define SMC_GET_PHY_MII_LPA(phy,x) SMC_GET_MII( MII_LPA, phy, x ) 779#define SMC_GET_PHY_MII_LPA(lp,phy,x) SMC_GET_MII( (lp), MII_LPA, phy, x )
733#define SMC_SET_PHY_MII_LPA(phy,x) SMC_SET_MII( MII_LPA, phy, x ) 780#define SMC_SET_PHY_MII_LPA(lp,phy,x) SMC_SET_MII( (lp), MII_LPA, phy, x )
734#define SMC_GET_PHY_CTRL_STS(phy,x) SMC_GET_MII( PHY_MODE_CTRL_STS, phy, x ) 781#define SMC_GET_PHY_CTRL_STS(lp,phy,x) SMC_GET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
735#define SMC_SET_PHY_CTRL_STS(phy,x) SMC_SET_MII( PHY_MODE_CTRL_STS, phy, x ) 782#define SMC_SET_PHY_CTRL_STS(lp,phy,x) SMC_SET_MII( (lp), PHY_MODE_CTRL_STS, phy, x )
736#define SMC_GET_PHY_INT_SRC(phy,x) SMC_GET_MII( PHY_INT_SRC, phy, x ) 783#define SMC_GET_PHY_INT_SRC(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_SRC, phy, x )
737#define SMC_SET_PHY_INT_SRC(phy,x) SMC_SET_MII( PHY_INT_SRC, phy, x ) 784#define SMC_SET_PHY_INT_SRC(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_SRC, phy, x )
738#define SMC_GET_PHY_INT_MASK(phy,x) SMC_GET_MII( PHY_INT_MASK, phy, x ) 785#define SMC_GET_PHY_INT_MASK(lp,phy,x) SMC_GET_MII( (lp), PHY_INT_MASK, phy, x )
739#define SMC_SET_PHY_INT_MASK(phy,x) SMC_SET_MII( PHY_INT_MASK, phy, x ) 786#define SMC_SET_PHY_INT_MASK(lp,phy,x) SMC_SET_MII( (lp), PHY_INT_MASK, phy, x )
740#define SMC_GET_PHY_SPECIAL(phy,x) SMC_GET_MII( PHY_SPECIAL, phy, x ) 787#define SMC_GET_PHY_SPECIAL(lp,phy,x) SMC_GET_MII( (lp), PHY_SPECIAL, phy, x )
741 788
742 789
743 790
744/* Misc read/write macros */ 791/* Misc read/write macros */
745 792
746#ifndef SMC_GET_MAC_ADDR 793#ifndef SMC_GET_MAC_ADDR
747#define SMC_GET_MAC_ADDR(addr) \ 794#define SMC_GET_MAC_ADDR(lp, addr) \
748 do { \ 795 do { \
749 unsigned int __v; \ 796 unsigned int __v; \
750 \ 797 \
751 SMC_GET_MAC_CSR(ADDRL, __v); \ 798 SMC_GET_MAC_CSR((lp), ADDRL, __v); \
752 addr[0] = __v; addr[1] = __v >> 8; \ 799 addr[0] = __v; addr[1] = __v >> 8; \
753 addr[2] = __v >> 16; addr[3] = __v >> 24; \ 800 addr[2] = __v >> 16; addr[3] = __v >> 24; \
754 SMC_GET_MAC_CSR(ADDRH, __v); \ 801 SMC_GET_MAC_CSR((lp), ADDRH, __v); \
755 addr[4] = __v; addr[5] = __v >> 8; \ 802 addr[4] = __v; addr[5] = __v >> 8; \
756 } while (0) 803 } while (0)
757#endif 804#endif
758 805
759#define SMC_SET_MAC_ADDR(addr) \ 806#define SMC_SET_MAC_ADDR(lp, addr) \
760 do { \ 807 do { \
761 SMC_SET_MAC_CSR(ADDRL, \ 808 SMC_SET_MAC_CSR((lp), ADDRL, \
762 addr[0] | \ 809 addr[0] | \
763 (addr[1] << 8) | \ 810 (addr[1] << 8) | \
764 (addr[2] << 16) | \ 811 (addr[2] << 16) | \
765 (addr[3] << 24)); \ 812 (addr[3] << 24)); \
766 SMC_SET_MAC_CSR(ADDRH, addr[4]|(addr[5] << 8));\ 813 SMC_SET_MAC_CSR((lp), ADDRH, addr[4]|(addr[5] << 8));\
767 } while (0) 814 } while (0)
768 815
769 816
770#define SMC_WRITE_EEPROM_CMD(cmd, addr) \ 817#define SMC_WRITE_EEPROM_CMD(lp, cmd, addr) \
771 do { \ 818 do { \
772 while (SMC_GET_E2P_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 819 while (SMC_GET_E2P_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
773 SMC_SET_MAC_CMD(MAC_CSR_CMD_R_NOT_W_ | a ); \ 820 SMC_SET_MAC_CMD((lp), MAC_CSR_CMD_R_NOT_W_ | a ); \
774 while (SMC_GET_MAC_CMD() & MAC_CSR_CMD_CSR_BUSY_); \ 821 while (SMC_GET_MAC_CMD((lp)) & MAC_CSR_CMD_CSR_BUSY_); \
775 } while (0) 822 } while (0)
776 823
777#endif /* _SMC911X_H_ */ 824#endif /* _SMC911X_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-07 02:38:10 -0500