diff options
author | Stephen Hemminger <shemminger@osdl.org> | 2006-03-22 13:38:45 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2006-03-22 20:30:45 -0500 |
commit | eadfa7ddca98b0430b8b666e0344ab1d559389c8 (patch) | |
tree | c3949c277f2a0e99a6b6cceff6deab16b75a7dba /drivers/net/sky2.h | |
parent | def720e6166f49027c45286088d1e22743666ca3 (diff) |
[PATCH] sky2: more ethtool stats
Expose all the available hardware statistics via ethtool.
And cleanup some of the statistics definitions.
Signed-off-by: Stephen Hemminger <shemminger@osdl.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/sky2.h')
-rw-r--r-- | drivers/net/sky2.h | 71 |
1 files changed, 35 insertions, 36 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h index d63cd5a1b71c..2838f661b393 100644 --- a/drivers/net/sky2.h +++ b/drivers/net/sky2.h | |||
@@ -1373,23 +1373,23 @@ enum { | |||
1373 | GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ | 1373 | GM_SMI_CTRL = 0x0080, /* 16 bit r/w SMI Control Register */ |
1374 | GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ | 1374 | GM_SMI_DATA = 0x0084, /* 16 bit r/w SMI Data Register */ |
1375 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ | 1375 | GM_PHY_ADDR = 0x0088, /* 16 bit r/w GPHY Address Register */ |
1376 | /* MIB Counters */ | ||
1377 | GM_MIB_CNT_BASE = 0x0100, /* Base Address of MIB Counters */ | ||
1378 | GM_MIB_CNT_SIZE = 256, | ||
1376 | }; | 1379 | }; |
1377 | 1380 | ||
1378 | /* MIB Counters */ | ||
1379 | #define GM_MIB_CNT_BASE 0x0100 /* Base Address of MIB Counters */ | ||
1380 | #define GM_MIB_CNT_SIZE 44 /* Number of MIB Counters */ | ||
1381 | 1381 | ||
1382 | /* | 1382 | /* |
1383 | * MIB Counters base address definitions (low word) - | 1383 | * MIB Counters base address definitions (low word) - |
1384 | * use offset 4 for access to high word (32 bit r/o) | 1384 | * use offset 4 for access to high word (32 bit r/o) |
1385 | */ | 1385 | */ |
1386 | enum { | 1386 | enum { |
1387 | GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ | 1387 | GM_RXF_UC_OK = GM_MIB_CNT_BASE + 0, /* Unicast Frames Received OK */ |
1388 | GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ | 1388 | GM_RXF_BC_OK = GM_MIB_CNT_BASE + 8, /* Broadcast Frames Received OK */ |
1389 | GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ | 1389 | GM_RXF_MPAUSE = GM_MIB_CNT_BASE + 16, /* Pause MAC Ctrl Frames Received */ |
1390 | GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ | 1390 | GM_RXF_MC_OK = GM_MIB_CNT_BASE + 24, /* Multicast Frames Received OK */ |
1391 | GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ | 1391 | GM_RXF_FCS_ERR = GM_MIB_CNT_BASE + 32, /* Rx Frame Check Seq. Error */ |
1392 | /* GM_MIB_CNT_BASE + 40: reserved */ | 1392 | |
1393 | GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ | 1393 | GM_RXO_OK_LO = GM_MIB_CNT_BASE + 48, /* Octets Received OK Low */ |
1394 | GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ | 1394 | GM_RXO_OK_HI = GM_MIB_CNT_BASE + 56, /* Octets Received OK High */ |
1395 | GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ | 1395 | GM_RXO_ERR_LO = GM_MIB_CNT_BASE + 64, /* Octets Received Invalid Low */ |
@@ -1397,37 +1397,36 @@ enum { | |||
1397 | GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ | 1397 | GM_RXF_SHT = GM_MIB_CNT_BASE + 80, /* Frames <64 Byte Received OK */ |
1398 | GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ | 1398 | GM_RXE_FRAG = GM_MIB_CNT_BASE + 88, /* Frames <64 Byte Received with FCS Err */ |
1399 | GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ | 1399 | GM_RXF_64B = GM_MIB_CNT_BASE + 96, /* 64 Byte Rx Frame */ |
1400 | GM_RXF_127B = GM_MIB_CNT_BASE + 104, /* 65-127 Byte Rx Frame */ | 1400 | GM_RXF_127B = GM_MIB_CNT_BASE + 104,/* 65-127 Byte Rx Frame */ |
1401 | GM_RXF_255B = GM_MIB_CNT_BASE + 112, /* 128-255 Byte Rx Frame */ | 1401 | GM_RXF_255B = GM_MIB_CNT_BASE + 112,/* 128-255 Byte Rx Frame */ |
1402 | GM_RXF_511B = GM_MIB_CNT_BASE + 120, /* 256-511 Byte Rx Frame */ | 1402 | GM_RXF_511B = GM_MIB_CNT_BASE + 120,/* 256-511 Byte Rx Frame */ |
1403 | GM_RXF_1023B = GM_MIB_CNT_BASE + 128, /* 512-1023 Byte Rx Frame */ | 1403 | GM_RXF_1023B = GM_MIB_CNT_BASE + 128,/* 512-1023 Byte Rx Frame */ |
1404 | GM_RXF_1518B = GM_MIB_CNT_BASE + 136, /* 1024-1518 Byte Rx Frame */ | 1404 | GM_RXF_1518B = GM_MIB_CNT_BASE + 136,/* 1024-1518 Byte Rx Frame */ |
1405 | GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144, /* 1519-MaxSize Byte Rx Frame */ | 1405 | GM_RXF_MAX_SZ = GM_MIB_CNT_BASE + 144,/* 1519-MaxSize Byte Rx Frame */ |
1406 | GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152, /* Rx Frame too Long Error */ | 1406 | GM_RXF_LNG_ERR = GM_MIB_CNT_BASE + 152,/* Rx Frame too Long Error */ |
1407 | GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160, /* Rx Jabber Packet Frame */ | 1407 | GM_RXF_JAB_PKT = GM_MIB_CNT_BASE + 160,/* Rx Jabber Packet Frame */ |
1408 | /* GM_MIB_CNT_BASE + 168: reserved */ | 1408 | |
1409 | GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176, /* Rx FIFO overflow Event */ | 1409 | GM_RXE_FIFO_OV = GM_MIB_CNT_BASE + 176,/* Rx FIFO overflow Event */ |
1410 | /* GM_MIB_CNT_BASE + 184: reserved */ | 1410 | GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192,/* Unicast Frames Xmitted OK */ |
1411 | GM_TXF_UC_OK = GM_MIB_CNT_BASE + 192, /* Unicast Frames Xmitted OK */ | 1411 | GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200,/* Broadcast Frames Xmitted OK */ |
1412 | GM_TXF_BC_OK = GM_MIB_CNT_BASE + 200, /* Broadcast Frames Xmitted OK */ | 1412 | GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208,/* Pause MAC Ctrl Frames Xmitted */ |
1413 | GM_TXF_MPAUSE = GM_MIB_CNT_BASE + 208, /* Pause MAC Ctrl Frames Xmitted */ | 1413 | GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216,/* Multicast Frames Xmitted OK */ |
1414 | GM_TXF_MC_OK = GM_MIB_CNT_BASE + 216, /* Multicast Frames Xmitted OK */ | 1414 | GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224,/* Octets Transmitted OK Low */ |
1415 | GM_TXO_OK_LO = GM_MIB_CNT_BASE + 224, /* Octets Transmitted OK Low */ | 1415 | GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232,/* Octets Transmitted OK High */ |
1416 | GM_TXO_OK_HI = GM_MIB_CNT_BASE + 232, /* Octets Transmitted OK High */ | 1416 | GM_TXF_64B = GM_MIB_CNT_BASE + 240,/* 64 Byte Tx Frame */ |
1417 | GM_TXF_64B = GM_MIB_CNT_BASE + 240, /* 64 Byte Tx Frame */ | 1417 | GM_TXF_127B = GM_MIB_CNT_BASE + 248,/* 65-127 Byte Tx Frame */ |
1418 | GM_TXF_127B = GM_MIB_CNT_BASE + 248, /* 65-127 Byte Tx Frame */ | 1418 | GM_TXF_255B = GM_MIB_CNT_BASE + 256,/* 128-255 Byte Tx Frame */ |
1419 | GM_TXF_255B = GM_MIB_CNT_BASE + 256, /* 128-255 Byte Tx Frame */ | 1419 | GM_TXF_511B = GM_MIB_CNT_BASE + 264,/* 256-511 Byte Tx Frame */ |
1420 | GM_TXF_511B = GM_MIB_CNT_BASE + 264, /* 256-511 Byte Tx Frame */ | 1420 | GM_TXF_1023B = GM_MIB_CNT_BASE + 272,/* 512-1023 Byte Tx Frame */ |
1421 | GM_TXF_1023B = GM_MIB_CNT_BASE + 272, /* 512-1023 Byte Tx Frame */ | 1421 | GM_TXF_1518B = GM_MIB_CNT_BASE + 280,/* 1024-1518 Byte Tx Frame */ |
1422 | GM_TXF_1518B = GM_MIB_CNT_BASE + 280, /* 1024-1518 Byte Tx Frame */ | 1422 | GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288,/* 1519-MaxSize Byte Tx Frame */ |
1423 | GM_TXF_MAX_SZ = GM_MIB_CNT_BASE + 288, /* 1519-MaxSize Byte Tx Frame */ | 1423 | |
1424 | 1424 | GM_TXF_COL = GM_MIB_CNT_BASE + 304,/* Tx Collision */ | |
1425 | GM_TXF_COL = GM_MIB_CNT_BASE + 304, /* Tx Collision */ | 1425 | GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312,/* Tx Late Collision */ |
1426 | GM_TXF_LAT_COL = GM_MIB_CNT_BASE + 312, /* Tx Late Collision */ | 1426 | GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320,/* Tx aborted due to Exces. Col. */ |
1427 | GM_TXF_ABO_COL = GM_MIB_CNT_BASE + 320, /* Tx aborted due to Exces. Col. */ | 1427 | GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328,/* Tx Multiple Collision */ |
1428 | GM_TXF_MUL_COL = GM_MIB_CNT_BASE + 328, /* Tx Multiple Collision */ | 1428 | GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336,/* Tx Single Collision */ |
1429 | GM_TXF_SNG_COL = GM_MIB_CNT_BASE + 336, /* Tx Single Collision */ | 1429 | GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344,/* Tx FIFO Underrun Event */ |
1430 | GM_TXE_FIFO_UR = GM_MIB_CNT_BASE + 344, /* Tx FIFO Underrun Event */ | ||
1431 | }; | 1430 | }; |
1432 | 1431 | ||
1433 | /* GMAC Bit Definitions */ | 1432 | /* GMAC Bit Definitions */ |