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authorStephen Hemminger <shemminger@linux-foundation.org>2007-02-06 13:45:43 -0500
committerJeff Garzik <jeff@garzik.org>2007-02-07 18:50:46 -0500
commit9374549428820be10f01e217cec1b34cb3e3de6d (patch)
treed35c1f19c1d2ee0780106aa91105746dfe46ae19 /drivers/net/sky2.h
parent62335ab013d9eaef502bd402eb2eb72e8cff58f1 (diff)
sky2: Yukon Extreme support
This is basic support for the new Yukon Extreme chip, extracted from the new vendor driver 10.0.4.3. Since this is untested hardware, it has a big fat warning for now. Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/sky2.h')
-rw-r--r--drivers/net/sky2.h56
1 files changed, 52 insertions, 4 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index a84584835ee1..3b0189569d52 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -371,12 +371,9 @@ enum {
371 371
372/* B2_CHIP_ID 8 bit Chip Identification Number */ 372/* B2_CHIP_ID 8 bit Chip Identification Number */
373enum { 373enum {
374 CHIP_ID_GENESIS = 0x0a, /* Chip ID for GENESIS */
375 CHIP_ID_YUKON = 0xb0, /* Chip ID for YUKON */
376 CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
377 CHIP_ID_YUKON_LP = 0xb2, /* Chip ID for YUKON-LP */
378 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */ 374 CHIP_ID_YUKON_XL = 0xb3, /* Chip ID for YUKON-2 XL */
379 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */ 375 CHIP_ID_YUKON_EC_U = 0xb4, /* Chip ID for YUKON-2 EC Ultra */
376 CHIP_ID_YUKON_EX = 0xb5, /* Chip ID for YUKON-2 Extreme */
380 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */ 377 CHIP_ID_YUKON_EC = 0xb6, /* Chip ID for YUKON-2 EC */
381 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */ 378 CHIP_ID_YUKON_FE = 0xb7, /* Chip ID for YUKON-2 FE */
382 379
@@ -768,6 +765,24 @@ enum {
768 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */ 765 POLL_LIST_ADDR_HI= 0x0e2c,/* 32 bit Poll. List Start Addr (high) */
769}; 766};
770 767
768enum {
769 SMB_CFG = 0x0e40, /* 32 bit SMBus Config Register */
770 SMB_CSR = 0x0e44, /* 32 bit SMBus Control/Status Register */
771};
772
773enum {
774 CPU_WDOG = 0x0e48, /* 32 bit Watchdog Register */
775 CPU_CNTR = 0x0e4C, /* 32 bit Counter Register */
776 CPU_TIM = 0x0e50,/* 32 bit Timer Compare Register */
777 CPU_AHB_ADDR = 0x0e54, /* 32 bit CPU AHB Debug Register */
778 CPU_AHB_WDATA = 0x0e58, /* 32 bit CPU AHB Debug Register */
779 CPU_AHB_RDATA = 0x0e5C, /* 32 bit CPU AHB Debug Register */
780 HCU_MAP_BASE = 0x0e60, /* 32 bit Reset Mapping Base */
781 CPU_AHB_CTRL = 0x0e64, /* 32 bit CPU AHB Debug Register */
782 HCU_CCSR = 0x0e68, /* 32 bit CPU Control and Status Register */
783 HCU_HCSR = 0x0e6C, /* 32 bit Host Control and Status Register */
784};
785
771/* ASF Subsystem Registers (Yukon-2 only) */ 786/* ASF Subsystem Registers (Yukon-2 only) */
772enum { 787enum {
773 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */ 788 B28_Y2_SMB_CONFIG = 0x0e40,/* 32 bit ASF SMBus Config Register */
@@ -1649,6 +1664,39 @@ enum {
1649 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */ 1664 Y2_ASF_CLR_ASFI = 1<<1, /* Clear host IRQ */
1650 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */ 1665 Y2_ASF_HOST_IRQ = 1<<0, /* Issue an IRQ to HOST system */
1651}; 1666};
1667/* HCU_CCSR CPU Control and Status Register */
1668enum {
1669 HCU_CCSR_SMBALERT_MONITOR= 1<<27, /* SMBALERT pin monitor */
1670 HCU_CCSR_CPU_SLEEP = 1<<26, /* CPU sleep status */
1671 /* Clock Stretching Timeout */
1672 HCU_CCSR_CS_TO = 1<<25,
1673 HCU_CCSR_WDOG = 1<<24, /* Watchdog Reset */
1674
1675 HCU_CCSR_CLR_IRQ_HOST = 1<<17, /* Clear IRQ_HOST */
1676 HCU_CCSR_SET_IRQ_HCU = 1<<16, /* Set IRQ_HCU */
1677
1678 HCU_CCSR_AHB_RST = 1<<9, /* Reset AHB bridge */
1679 HCU_CCSR_CPU_RST_MODE = 1<<8, /* CPU Reset Mode */
1680
1681 HCU_CCSR_SET_SYNC_CPU = 1<<5,
1682 HCU_CCSR_CPU_CLK_DIVIDE_MSK = 3<<3,/* CPU Clock Divide */
1683 HCU_CCSR_CPU_CLK_DIVIDE_BASE= 1<<3,
1684 HCU_CCSR_OS_PRSNT = 1<<2, /* ASF OS Present */
1685/* Microcontroller State */
1686 HCU_CCSR_UC_STATE_MSK = 3,
1687 HCU_CCSR_UC_STATE_BASE = 1<<0,
1688 HCU_CCSR_ASF_RESET = 0,
1689 HCU_CCSR_ASF_HALTED = 1<<1,
1690 HCU_CCSR_ASF_RUNNING = 1<<0,
1691};
1692
1693/* HCU_HCSR Host Control and Status Register */
1694enum {
1695 HCU_HCSR_SET_IRQ_CPU = 1<<16, /* Set IRQ_CPU */
1696
1697 HCU_HCSR_CLR_IRQ_HCU = 1<<1, /* Clear IRQ_HCU */
1698 HCU_HCSR_SET_IRQ_HOST = 1<<0, /* Set IRQ_HOST */
1699};
1652 1700
1653/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */ 1701/* STAT_CTRL 32 bit Status BMU control register (Yukon-2 only) */
1654enum { 1702enum {