aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/net/sky2.h
diff options
context:
space:
mode:
authorStephen Hemminger <shemminger@linux-foundation.org>2007-08-29 15:58:12 -0400
committerDavid S. Miller <davem@sunset.davemloft.net>2007-10-10 19:50:52 -0400
commitefcf6e2febbfe5b2ab497421e2f7f188e1741cf9 (patch)
tree150fe73fa32b833131c68749f59710d79a283436 /drivers/net/sky2.h
parent5b296bc9e1e5570ce60262e62af066f70180cb99 (diff)
sky2: document GPHY_CTRL bits
Add documentation of GPHY_CTRL register bits even if driver is not using them (yet). Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/sky2.h')
-rw-r--r--drivers/net/sky2.h22
1 files changed, 22 insertions, 0 deletions
diff --git a/drivers/net/sky2.h b/drivers/net/sky2.h
index f18f8752118e..3d4f1903d62c 100644
--- a/drivers/net/sky2.h
+++ b/drivers/net/sky2.h
@@ -1850,6 +1850,28 @@ enum {
1850 1850
1851/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */ 1851/* GPHY_CTRL 32 bit GPHY Control Reg (YUKON only) */
1852enum { 1852enum {
1853 GPC_TX_PAUSE = 1<<30, /* Tx pause enabled (ro) */
1854 GPC_RX_PAUSE = 1<<29, /* Rx pause enabled (ro) */
1855 GPC_SPEED = 3<<27, /* PHY speed (ro) */
1856 GPC_LINK = 1<<26, /* Link up (ro) */
1857 GPC_DUPLEX = 1<<25, /* Duplex (ro) */
1858 GPC_CLOCK = 1<<24, /* 125Mhz clock stable (ro) */
1859
1860 GPC_PDOWN = 1<<23, /* Internal regulator 2.5 power down */
1861 GPC_TSTMODE = 1<<22, /* Test mode */
1862 GPC_REG18 = 1<<21, /* Reg18 Power down */
1863 GPC_REG12SEL = 3<<19, /* Reg12 power setting */
1864 GPC_REG18SEL = 3<<17, /* Reg18 power setting */
1865 GPC_SPILOCK = 1<<16, /* SPI lock (ASF) */
1866
1867 GPC_LEDMUX = 3<<14, /* LED Mux */
1868 GPC_INTPOL = 1<<13, /* Interrupt polarity */
1869 GPC_DETECT = 1<<12, /* Energy detect */
1870 GPC_1000HD = 1<<11, /* Enable 1000Mbit HD */
1871 GPC_SLAVE = 1<<10, /* Slave mode */
1872 GPC_PAUSE = 1<<9, /* Pause enable */
1873 GPC_LEDCTL = 3<<6, /* GPHY Leds */
1874
1853 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */ 1875 GPC_RST_CLR = 1<<1, /* Clear GPHY Reset */
1854 GPC_RST_SET = 1<<0, /* Set GPHY Reset */ 1876 GPC_RST_SET = 1<<0, /* Set GPHY Reset */
1855}; 1877};