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authorStephen Hemminger <shemminger@linux-foundation.org>2007-05-24 18:22:43 -0400
committerJeff Garzik <jeff@garzik.org>2007-05-30 09:52:47 -0400
commitb4ed372b29e458021293e1c791d92d90f1bf5fe3 (patch)
tree717bacf9e4679908db59f41d7f88147f28070b6f /drivers/net/sky2.c
parent8903bab009d3e9b34050042f8c0faf741eb027be (diff)
sky2: dont set bogus bit in PHY register
This code inherited from the sk98lin driver is incorrect on the Yukon2. The GPHY_CTRL register values are specific to the internal PHY of the chip and the values used were leftovers. Driver was setting bit 13 which is now the INT polarity for the PHY! Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/sky2.c')
-rw-r--r--drivers/net/sky2.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
index 832fd69a0e59..d9bc98bd8af7 100644
--- a/drivers/net/sky2.c
+++ b/drivers/net/sky2.c
@@ -658,7 +658,7 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
658 const u8 *addr = hw->dev[port]->dev_addr; 658 const u8 *addr = hw->dev[port]->dev_addr;
659 659
660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET); 660 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE); 661 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
662 662
663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR); 663 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
664 664