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authorJeff Garzik <jgarzik@pobox.com>2005-11-11 22:48:14 -0500
committerJeff Garzik <jgarzik@pobox.com>2005-11-11 22:48:14 -0500
commit06d61cbf7c2522f43c09d5bb050acd0bd31812c0 (patch)
tree2ce1fb910566961de2d2ff1f2f01a9c0546d8092 /drivers/net/sky2.c
parent34afd638d0b0698e66b6aa4f749face019a3e90f (diff)
parentd0bbccfa3297d3ef6ae4691585abde9a6c26b186 (diff)
Merge branch 'sky2'
Diffstat (limited to 'drivers/net/sky2.c')
-rw-r--r--drivers/net/sky2.c3039
1 files changed, 3039 insertions, 0 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c
new file mode 100644
index 000000000000..9f89000e5ad5
--- /dev/null
+++ b/drivers/net/sky2.c
@@ -0,0 +1,3039 @@
1/*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26/*
27 * TODO
28 * - coalescing setting?
29 *
30 * TOTEST
31 * - speed setting
32 * - suspend/resume
33 */
34
35#include <linux/config.h>
36#include <linux/crc32.h>
37#include <linux/kernel.h>
38#include <linux/version.h>
39#include <linux/module.h>
40#include <linux/netdevice.h>
41#include <linux/dma-mapping.h>
42#include <linux/etherdevice.h>
43#include <linux/ethtool.h>
44#include <linux/pci.h>
45#include <linux/ip.h>
46#include <linux/tcp.h>
47#include <linux/in.h>
48#include <linux/delay.h>
49#include <linux/if_vlan.h>
50
51#include <asm/irq.h>
52
53#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
54#define SKY2_VLAN_TAG_USED 1
55#endif
56
57#include "sky2.h"
58
59#define DRV_NAME "sky2"
60#define DRV_VERSION "0.7"
61#define PFX DRV_NAME " "
62
63/*
64 * The Yukon II chipset takes 64 bit command blocks (called list elements)
65 * that are organized into three (receive, transmit, status) different rings
66 * similar to Tigon3. A transmit can require several elements;
67 * a receive requires one (or two if using 64 bit dma).
68 */
69
70#ifdef CONFIG_SKY2_EC_A1
71#define is_ec_a1(hw) \
72 ((hw)->chip_id == CHIP_ID_YUKON_EC && \
73 (hw)->chip_rev == CHIP_REV_YU_EC_A1)
74#else
75#define is_ec_a1(hw) 0
76#endif
77
78#define RX_LE_SIZE 256
79#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
80#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
81#define RX_DEF_PENDING 128
82#define RX_COPY_THRESHOLD 256
83
84#define TX_RING_SIZE 512
85#define TX_DEF_PENDING (TX_RING_SIZE - 1)
86#define TX_MIN_PENDING 64
87#define MAX_SKB_TX_LE (4 + 2*MAX_SKB_FRAGS)
88
89#define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
90#define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
91#define ETH_JUMBO_MTU 9000
92#define TX_WATCHDOG (5 * HZ)
93#define NAPI_WEIGHT 64
94#define PHY_RETRIES 1000
95
96static const u32 default_msg =
97 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
98 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
99 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_INTR;
100
101static int debug = -1; /* defaults above */
102module_param(debug, int, 0);
103MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
104
105static const struct pci_device_id sky2_id_table[] = {
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) },
107 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) },
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) },
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
123 { 0 }
124};
125
126MODULE_DEVICE_TABLE(pci, sky2_id_table);
127
128/* Avoid conditionals by using array */
129static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
130static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
131
132static const char *yukon_name[] = {
133 [CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
134 [CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
135 [CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
136
137 [CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
138 [CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
139};
140
141
142/* Access to external PHY */
143static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
144{
145 int i;
146
147 gma_write16(hw, port, GM_SMI_DATA, val);
148 gma_write16(hw, port, GM_SMI_CTRL,
149 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
150
151 for (i = 0; i < PHY_RETRIES; i++) {
152 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
153 return;
154 udelay(1);
155 }
156 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
157}
158
159static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
160{
161 int i;
162
163 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
164 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
165
166 for (i = 0; i < PHY_RETRIES; i++) {
167 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
168 goto ready;
169 udelay(1);
170 }
171
172 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
173ready:
174 return gma_read16(hw, port, GM_SMI_DATA);
175}
176
177static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
178{
179 u16 power_control;
180 u32 reg1;
181 int vaux;
182 int ret = 0;
183
184 pr_debug("sky2_set_power_state %d\n", state);
185 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
186
187 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_PMC, &power_control);
188 vaux = (sky2_read8(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
189 (power_control & PCI_PM_CAP_PME_D3cold);
190
191 pci_read_config_word(hw->pdev, hw->pm_cap + PCI_PM_CTRL, &power_control);
192
193 power_control |= PCI_PM_CTRL_PME_STATUS;
194 power_control &= ~(PCI_PM_CTRL_STATE_MASK);
195
196 switch (state) {
197 case PCI_D0:
198 /* switch power to VCC (WA for VAUX problem) */
199 sky2_write8(hw, B0_POWER_CTRL,
200 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
201
202 /* disable Core Clock Division, */
203 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
204
205 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
206 /* enable bits are inverted */
207 sky2_write8(hw, B2_Y2_CLK_GATE,
208 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
209 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
210 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
211 else
212 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
213
214 /* Turn off phy power saving */
215 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
216 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
217
218 /* looks like this XL is back asswards .. */
219 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) {
220 reg1 |= PCI_Y2_PHY1_COMA;
221 if (hw->ports > 1)
222 reg1 |= PCI_Y2_PHY2_COMA;
223 }
224 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
225 break;
226
227 case PCI_D3hot:
228 case PCI_D3cold:
229 /* Turn on phy power saving */
230 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg1);
231 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
232 reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
233 else
234 reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
235 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1);
236
237 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
238 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
239 else
240 /* enable bits are inverted */
241 sky2_write8(hw, B2_Y2_CLK_GATE,
242 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
243 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
244 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
245
246 /* switch power to VAUX */
247 if (vaux && state != PCI_D3cold)
248 sky2_write8(hw, B0_POWER_CTRL,
249 (PC_VAUX_ENA | PC_VCC_ENA |
250 PC_VAUX_ON | PC_VCC_OFF));
251 break;
252 default:
253 printk(KERN_ERR PFX "Unknown power state %d\n", state);
254 ret = -1;
255 }
256
257 pci_write_config_byte(hw->pdev, hw->pm_cap + PCI_PM_CTRL, power_control);
258 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
259 return ret;
260}
261
262static void sky2_phy_reset(struct sky2_hw *hw, unsigned port)
263{
264 u16 reg;
265
266 /* disable all GMAC IRQ's */
267 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
268 /* disable PHY IRQs */
269 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
270
271 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
272 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
273 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
274 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
275
276 reg = gma_read16(hw, port, GM_RX_CTRL);
277 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
278 gma_write16(hw, port, GM_RX_CTRL, reg);
279}
280
281static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
282{
283 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
284 u16 ctrl, ct1000, adv, pg, ledctrl, ledover;
285
286 if (sky2->autoneg == AUTONEG_ENABLE && hw->chip_id != CHIP_ID_YUKON_XL) {
287 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
288
289 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
290 PHY_M_EC_MAC_S_MSK);
291 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
292
293 if (hw->chip_id == CHIP_ID_YUKON_EC)
294 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
295 else
296 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
297
298 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
299 }
300
301 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
302 if (hw->copper) {
303 if (hw->chip_id == CHIP_ID_YUKON_FE) {
304 /* enable automatic crossover */
305 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
306 } else {
307 /* disable energy detect */
308 ctrl &= ~PHY_M_PC_EN_DET_MSK;
309
310 /* enable automatic crossover */
311 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
312
313 if (sky2->autoneg == AUTONEG_ENABLE &&
314 hw->chip_id == CHIP_ID_YUKON_XL) {
315 ctrl &= ~PHY_M_PC_DSC_MSK;
316 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
317 }
318 }
319 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
320 } else {
321 /* workaround for deviation #4.88 (CRC errors) */
322 /* disable Automatic Crossover */
323
324 ctrl &= ~PHY_M_PC_MDIX_MSK;
325 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
326
327 if (hw->chip_id == CHIP_ID_YUKON_XL) {
328 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
329 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
330 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
331 ctrl &= ~PHY_M_MAC_MD_MSK;
332 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
333 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
334
335 /* select page 1 to access Fiber registers */
336 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
337 }
338 }
339
340 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
341 if (sky2->autoneg == AUTONEG_DISABLE)
342 ctrl &= ~PHY_CT_ANE;
343 else
344 ctrl |= PHY_CT_ANE;
345
346 ctrl |= PHY_CT_RESET;
347 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
348
349 ctrl = 0;
350 ct1000 = 0;
351 adv = PHY_AN_CSMA;
352
353 if (sky2->autoneg == AUTONEG_ENABLE) {
354 if (hw->copper) {
355 if (sky2->advertising & ADVERTISED_1000baseT_Full)
356 ct1000 |= PHY_M_1000C_AFD;
357 if (sky2->advertising & ADVERTISED_1000baseT_Half)
358 ct1000 |= PHY_M_1000C_AHD;
359 if (sky2->advertising & ADVERTISED_100baseT_Full)
360 adv |= PHY_M_AN_100_FD;
361 if (sky2->advertising & ADVERTISED_100baseT_Half)
362 adv |= PHY_M_AN_100_HD;
363 if (sky2->advertising & ADVERTISED_10baseT_Full)
364 adv |= PHY_M_AN_10_FD;
365 if (sky2->advertising & ADVERTISED_10baseT_Half)
366 adv |= PHY_M_AN_10_HD;
367 } else /* special defines for FIBER (88E1011S only) */
368 adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD;
369
370 /* Set Flow-control capabilities */
371 if (sky2->tx_pause && sky2->rx_pause)
372 adv |= PHY_AN_PAUSE_CAP; /* symmetric */
373 else if (sky2->rx_pause && !sky2->tx_pause)
374 adv |= PHY_AN_PAUSE_ASYM | PHY_AN_PAUSE_CAP;
375 else if (!sky2->rx_pause && sky2->tx_pause)
376 adv |= PHY_AN_PAUSE_ASYM; /* local */
377
378 /* Restart Auto-negotiation */
379 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
380 } else {
381 /* forced speed/duplex settings */
382 ct1000 = PHY_M_1000C_MSE;
383
384 if (sky2->duplex == DUPLEX_FULL)
385 ctrl |= PHY_CT_DUP_MD;
386
387 switch (sky2->speed) {
388 case SPEED_1000:
389 ctrl |= PHY_CT_SP1000;
390 break;
391 case SPEED_100:
392 ctrl |= PHY_CT_SP100;
393 break;
394 }
395
396 ctrl |= PHY_CT_RESET;
397 }
398
399 if (hw->chip_id != CHIP_ID_YUKON_FE)
400 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
401
402 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
403 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
404
405 /* Setup Phy LED's */
406 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
407 ledover = 0;
408
409 switch (hw->chip_id) {
410 case CHIP_ID_YUKON_FE:
411 /* on 88E3082 these bits are at 11..9 (shifted left) */
412 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
413
414 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
415
416 /* delete ACT LED control bits */
417 ctrl &= ~PHY_M_FELP_LED1_MSK;
418 /* change ACT LED control to blink mode */
419 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
420 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
421 break;
422
423 case CHIP_ID_YUKON_XL:
424 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
425
426 /* select page 3 to access LED control register */
427 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
428
429 /* set LED Function Control register */
430 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
431 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
432 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
433 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
434
435 /* set Polarity Control register */
436 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
437 (PHY_M_POLC_LS1_P_MIX(4) |
438 PHY_M_POLC_IS0_P_MIX(4) |
439 PHY_M_POLC_LOS_CTRL(2) |
440 PHY_M_POLC_INIT_CTRL(2) |
441 PHY_M_POLC_STA1_CTRL(2) |
442 PHY_M_POLC_STA0_CTRL(2)));
443
444 /* restore page register */
445 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
446 break;
447
448 default:
449 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
450 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
451 /* turn off the Rx LED (LED_RX) */
452 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
453 }
454
455 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
456
457 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
458 /* turn on 100 Mbps LED (LED_LINK100) */
459 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
460 }
461
462 if (ledover)
463 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
464
465 /* Enable phy interrupt on auto-negotiation complete (or link up) */
466 if (sky2->autoneg == AUTONEG_ENABLE)
467 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
468 else
469 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
470}
471
472static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
473{
474 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
475 u16 reg;
476 int i;
477 const u8 *addr = hw->dev[port]->dev_addr;
478
479 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
480 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
481
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
483
484 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
485 /* WA DEV_472 -- looks like crossed wires on port 2 */
486 /* clear GMAC 1 Control reset */
487 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
488 do {
489 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
490 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
491 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
492 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
493 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
494 }
495
496 if (sky2->autoneg == AUTONEG_DISABLE) {
497 reg = gma_read16(hw, port, GM_GP_CTRL);
498 reg |= GM_GPCR_AU_ALL_DIS;
499 gma_write16(hw, port, GM_GP_CTRL, reg);
500 gma_read16(hw, port, GM_GP_CTRL);
501
502 switch (sky2->speed) {
503 case SPEED_1000:
504 reg |= GM_GPCR_SPEED_1000;
505 /* fallthru */
506 case SPEED_100:
507 reg |= GM_GPCR_SPEED_100;
508 }
509
510 if (sky2->duplex == DUPLEX_FULL)
511 reg |= GM_GPCR_DUP_FULL;
512 } else
513 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
514
515 if (!sky2->tx_pause && !sky2->rx_pause) {
516 sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
517 reg |=
518 GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
519 } else if (sky2->tx_pause && !sky2->rx_pause) {
520 /* disable Rx flow-control */
521 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
522 }
523
524 gma_write16(hw, port, GM_GP_CTRL, reg);
525
526 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
527
528 spin_lock_bh(&hw->phy_lock);
529 sky2_phy_init(hw, port);
530 spin_unlock_bh(&hw->phy_lock);
531
532 /* MIB clear */
533 reg = gma_read16(hw, port, GM_PHY_ADDR);
534 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
535
536 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
537 gma_read16(hw, port, GM_MIB_CNT_BASE + 8 * i);
538 gma_write16(hw, port, GM_PHY_ADDR, reg);
539
540 /* transmit control */
541 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
542
543 /* receive control reg: unicast + multicast + no FCS */
544 gma_write16(hw, port, GM_RX_CTRL,
545 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
546
547 /* transmit flow control */
548 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
549
550 /* transmit parameter */
551 gma_write16(hw, port, GM_TX_PARAM,
552 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
553 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
554 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
555 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
556
557 /* serial mode register */
558 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
559 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
560
561 if (hw->dev[port]->mtu > ETH_DATA_LEN)
562 reg |= GM_SMOD_JUMBO_ENA;
563
564 gma_write16(hw, port, GM_SERIAL_MODE, reg);
565
566 /* virtual address for data */
567 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
568
569 /* physical address: used for pause frames */
570 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
571
572 /* ignore counter overflows */
573 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
574 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
575 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
576
577 /* Configure Rx MAC FIFO */
578 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
579 sky2_write16(hw, SK_REG(port, RX_GMF_CTRL_T),
580 GMF_RX_CTRL_DEF);
581
582 /* Flush Rx MAC FIFO on any flow control or error */
583 reg = GMR_FS_ANY_ERR;
584 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
585 reg = 0; /* WA dev #4.115 */
586
587 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
588 /* Set threshold to 0xa (64 bytes)
589 * ASF disabled so no need to do WA dev #4.30
590 */
591 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF);
592
593 /* Configure Tx MAC FIFO */
594 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
595 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
596}
597
598static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
599{
600 u32 end;
601
602 start /= 8;
603 len /= 8;
604 end = start + len - 1;
605
606 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
607 sky2_write32(hw, RB_ADDR(q, RB_START), start);
608 sky2_write32(hw, RB_ADDR(q, RB_END), end);
609 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
610 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
611
612 if (q == Q_R1 || q == Q_R2) {
613 u32 rxup, rxlo;
614
615 rxlo = len/2;
616 rxup = rxlo + len/4;
617
618 /* Set thresholds on receive queue's */
619 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), rxup);
620 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), rxlo);
621 } else {
622 /* Enable store & forward on Tx queue's because
623 * Tx FIFO is only 1K on Yukon
624 */
625 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
626 }
627
628 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
629 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
630}
631
632/* Setup Bus Memory Interface */
633static void sky2_qset(struct sky2_hw *hw, u16 q, u32 wm)
634{
635 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
636 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
637 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
638 sky2_write32(hw, Q_ADDR(q, Q_WM), wm);
639}
640
641/* Setup prefetch unit registers. This is the interface between
642 * hardware and driver list elements
643 */
644static inline void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
645 u64 addr, u32 last)
646{
647 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
648 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
649 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
650 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
651 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
652 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
653
654 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
655}
656
657static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
658{
659 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
660
661 sky2->tx_prod = (sky2->tx_prod + 1) % TX_RING_SIZE;
662 return le;
663}
664
665/*
666 * This is a workaround code taken from SysKonnect sk98lin driver
667 * to deal with chip bug on Yukon EC rev 0 in the wraparound case.
668 */
669static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q,
670 u16 idx, u16 *last, u16 size)
671{
672 if (is_ec_a1(hw) && idx < *last) {
673 u16 hwget = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
674
675 if (hwget == 0) {
676 /* Start prefetching again */
677 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 0xe0);
678 goto setnew;
679 }
680
681 if (hwget == size - 1) {
682 /* set watermark to one list element */
683 sky2_write8(hw, Y2_QADDR(q, PREF_UNIT_FIFO_WM), 8);
684
685 /* set put index to first list element */
686 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), 0);
687 } else /* have hardware go to end of list */
688 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX),
689 size - 1);
690 } else {
691setnew:
692 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
693 }
694 *last = idx;
695}
696
697
698static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
699{
700 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
701 sky2->rx_put = (sky2->rx_put + 1) % RX_LE_SIZE;
702 return le;
703}
704
705/* Build description to hardware about buffer */
706static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
707{
708 struct sky2_rx_le *le;
709 u32 hi = (re->mapaddr >> 16) >> 16;
710
711 re->idx = sky2->rx_put;
712 if (sky2->rx_addr64 != hi) {
713 le = sky2_next_rx(sky2);
714 le->addr = cpu_to_le32(hi);
715 le->ctrl = 0;
716 le->opcode = OP_ADDR64 | HW_OWNER;
717 sky2->rx_addr64 = hi;
718 }
719
720 le = sky2_next_rx(sky2);
721 le->addr = cpu_to_le32((u32) re->mapaddr);
722 le->length = cpu_to_le16(re->maplen);
723 le->ctrl = 0;
724 le->opcode = OP_PACKET | HW_OWNER;
725}
726
727
728/* Tell chip where to start receive checksum.
729 * Actually has two checksums, but set both same to avoid possible byte
730 * order problems.
731 */
732static void rx_set_checksum(struct sky2_port *sky2)
733{
734 struct sky2_rx_le *le;
735
736 le = sky2_next_rx(sky2);
737 le->addr = (ETH_HLEN << 16) | ETH_HLEN;
738 le->ctrl = 0;
739 le->opcode = OP_TCPSTART | HW_OWNER;
740
741 sky2_write32(sky2->hw,
742 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
743 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
744
745}
746
747/*
748 * The RX Stop command will not work for Yukon-2 if the BMU does not
749 * reach the end of packet and since we can't make sure that we have
750 * incoming data, we must reset the BMU while it is not doing a DMA
751 * transfer. Since it is possible that the RX path is still active,
752 * the RX RAM buffer will be stopped first, so any possible incoming
753 * data will not trigger a DMA. After the RAM buffer is stopped, the
754 * BMU is polled until any DMA in progress is ended and only then it
755 * will be reset.
756 */
757static void sky2_rx_stop(struct sky2_port *sky2)
758{
759 struct sky2_hw *hw = sky2->hw;
760 unsigned rxq = rxqaddr[sky2->port];
761 int i;
762
763 /* disable the RAM Buffer receive queue */
764 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
765
766 for (i = 0; i < 0xffff; i++)
767 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
768 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
769 goto stopped;
770
771 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
772 sky2->netdev->name);
773stopped:
774 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
775
776 /* reset the Rx prefetch unit */
777 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
778}
779
780/* Clean out receive buffer area, assumes receiver hardware stopped */
781static void sky2_rx_clean(struct sky2_port *sky2)
782{
783 unsigned i;
784
785 memset(sky2->rx_le, 0, RX_LE_BYTES);
786 for (i = 0; i < sky2->rx_pending; i++) {
787 struct ring_info *re = sky2->rx_ring + i;
788
789 if (re->skb) {
790 pci_unmap_single(sky2->hw->pdev,
791 re->mapaddr, re->maplen,
792 PCI_DMA_FROMDEVICE);
793 kfree_skb(re->skb);
794 re->skb = NULL;
795 }
796 }
797}
798
799#ifdef SKY2_VLAN_TAG_USED
800static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
801{
802 struct sky2_port *sky2 = netdev_priv(dev);
803 struct sky2_hw *hw = sky2->hw;
804 u16 port = sky2->port;
805 unsigned long flags;
806
807 spin_lock_irqsave(&sky2->tx_lock, flags);
808
809 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
811 sky2->vlgrp = grp;
812
813 spin_unlock_irqrestore(&sky2->tx_lock, flags);
814}
815
816static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
817{
818 struct sky2_port *sky2 = netdev_priv(dev);
819 struct sky2_hw *hw = sky2->hw;
820 u16 port = sky2->port;
821 unsigned long flags;
822
823 spin_lock_irqsave(&sky2->tx_lock, flags);
824
825 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
826 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
827 if (sky2->vlgrp)
828 sky2->vlgrp->vlan_devices[vid] = NULL;
829
830 spin_unlock_irqrestore(&sky2->tx_lock, flags);
831}
832#endif
833
834#define roundup(x, y) ((((x)+((y)-1))/(y))*(y))
835static inline unsigned rx_size(const struct sky2_port *sky2)
836{
837 return roundup(sky2->netdev->mtu + ETH_HLEN + 4, 8);
838}
839
840/*
841 * Allocate and setup receiver buffer pool.
842 * In case of 64 bit dma, there are 2X as many list elements
843 * available as ring entries
844 * and need to reserve one list element so we don't wrap around.
845 *
846 * It appears the hardware has a bug in the FIFO logic that
847 * cause it to hang if the FIFO gets overrun and the receive buffer
848 * is not aligned. This means we can't use skb_reserve to align
849 * the IP header.
850 */
851static int sky2_rx_start(struct sky2_port *sky2)
852{
853 struct sky2_hw *hw = sky2->hw;
854 unsigned size = rx_size(sky2);
855 unsigned rxq = rxqaddr[sky2->port];
856 int i;
857
858 sky2->rx_put = sky2->rx_next = 0;
859 sky2_qset(hw, rxq, is_pciex(hw) ? 0x80 : 0x600);
860 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
861
862 rx_set_checksum(sky2);
863 for (i = 0; i < sky2->rx_pending; i++) {
864 struct ring_info *re = sky2->rx_ring + i;
865
866 re->skb = dev_alloc_skb(size);
867 if (!re->skb)
868 goto nomem;
869
870 re->mapaddr = pci_map_single(hw->pdev, re->skb->data,
871 size, PCI_DMA_FROMDEVICE);
872 re->maplen = size;
873 sky2_rx_add(sky2, re);
874 }
875
876 /* Tell chip about available buffers */
877 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
878 sky2->rx_last_put = sky2_read16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX));
879 return 0;
880nomem:
881 sky2_rx_clean(sky2);
882 return -ENOMEM;
883}
884
885/* Bring up network interface. */
886static int sky2_up(struct net_device *dev)
887{
888 struct sky2_port *sky2 = netdev_priv(dev);
889 struct sky2_hw *hw = sky2->hw;
890 unsigned port = sky2->port;
891 u32 ramsize, rxspace;
892 int err = -ENOMEM;
893
894 if (netif_msg_ifup(sky2))
895 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
896
897 /* must be power of 2 */
898 sky2->tx_le = pci_alloc_consistent(hw->pdev,
899 TX_RING_SIZE *
900 sizeof(struct sky2_tx_le),
901 &sky2->tx_le_map);
902 if (!sky2->tx_le)
903 goto err_out;
904
905 sky2->tx_ring = kzalloc(TX_RING_SIZE * sizeof(struct ring_info),
906 GFP_KERNEL);
907 if (!sky2->tx_ring)
908 goto err_out;
909 sky2->tx_prod = sky2->tx_cons = 0;
910
911 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
912 &sky2->rx_le_map);
913 if (!sky2->rx_le)
914 goto err_out;
915 memset(sky2->rx_le, 0, RX_LE_BYTES);
916
917 sky2->rx_ring = kzalloc(sky2->rx_pending * sizeof(struct ring_info),
918 GFP_KERNEL);
919 if (!sky2->rx_ring)
920 goto err_out;
921
922 sky2_mac_init(hw, port);
923
924 /* Configure RAM buffers */
925 if (hw->chip_id == CHIP_ID_YUKON_FE ||
926 (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == 2))
927 ramsize = 4096;
928 else {
929 u8 e0 = sky2_read8(hw, B2_E_0);
930 ramsize = (e0 == 0) ? (128 * 1024) : (e0 * 4096);
931 }
932
933 /* 2/3 for Rx */
934 rxspace = (2 * ramsize) / 3;
935 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
936 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
937
938 /* Make sure SyncQ is disabled */
939 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
940 RB_RST_SET);
941
942 sky2_qset(hw, txqaddr[port], 0x600);
943 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
944 TX_RING_SIZE - 1);
945
946 err = sky2_rx_start(sky2);
947 if (err)
948 goto err_out;
949
950 /* Enable interrupts from phy/mac for port */
951 hw->intr_mask |= (port == 0) ? Y2_IS_PORT_1 : Y2_IS_PORT_2;
952 sky2_write32(hw, B0_IMSK, hw->intr_mask);
953 return 0;
954
955err_out:
956 if (sky2->rx_le)
957 pci_free_consistent(hw->pdev, RX_LE_BYTES,
958 sky2->rx_le, sky2->rx_le_map);
959 if (sky2->tx_le)
960 pci_free_consistent(hw->pdev,
961 TX_RING_SIZE * sizeof(struct sky2_tx_le),
962 sky2->tx_le, sky2->tx_le_map);
963 if (sky2->tx_ring)
964 kfree(sky2->tx_ring);
965 if (sky2->rx_ring)
966 kfree(sky2->rx_ring);
967
968 return err;
969}
970
971/* Modular subtraction in ring */
972static inline int tx_dist(unsigned tail, unsigned head)
973{
974 return (head >= tail ? head : head + TX_RING_SIZE) - tail;
975}
976
977/* Number of list elements available for next tx */
978static inline int tx_avail(const struct sky2_port *sky2)
979{
980 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
981}
982
983/* Estimate of number of transmit list elements required */
984static inline unsigned tx_le_req(const struct sk_buff *skb)
985{
986 unsigned count;
987
988 count = sizeof(dma_addr_t) / sizeof(u32);
989 count += skb_shinfo(skb)->nr_frags * count;
990
991 if (skb_shinfo(skb)->tso_size)
992 ++count;
993
994 if (skb->ip_summed)
995 ++count;
996
997 return count;
998}
999
1000/*
1001 * Put one packet in ring for transmit.
1002 * A single packet can generate multiple list elements, and
1003 * the number of ring elements will probably be less than the number
1004 * of list elements used.
1005 */
1006static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1007{
1008 struct sky2_port *sky2 = netdev_priv(dev);
1009 struct sky2_hw *hw = sky2->hw;
1010 struct sky2_tx_le *le = NULL;
1011 struct ring_info *re;
1012 unsigned long flags;
1013 unsigned i, len;
1014 dma_addr_t mapping;
1015 u32 addr64;
1016 u16 mss;
1017 u8 ctrl;
1018
1019 local_irq_save(flags);
1020 if (!spin_trylock(&sky2->tx_lock)) {
1021 local_irq_restore(flags);
1022 return NETDEV_TX_LOCKED;
1023 }
1024
1025 if (unlikely(tx_avail(sky2) < tx_le_req(skb))) {
1026 netif_stop_queue(dev);
1027 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1028
1029 printk(KERN_WARNING PFX "%s: ring full when queue awake!\n",
1030 dev->name);
1031 return NETDEV_TX_BUSY;
1032 }
1033
1034 if (unlikely(netif_msg_tx_queued(sky2)))
1035 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1036 dev->name, sky2->tx_prod, skb->len);
1037
1038 len = skb_headlen(skb);
1039 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1040 addr64 = (mapping >> 16) >> 16;
1041
1042 re = sky2->tx_ring + sky2->tx_prod;
1043
1044 /* Send high bits if changed */
1045 if (addr64 != sky2->tx_addr64) {
1046 le = get_tx_le(sky2);
1047 le->tx.addr = cpu_to_le32(addr64);
1048 le->ctrl = 0;
1049 le->opcode = OP_ADDR64 | HW_OWNER;
1050 sky2->tx_addr64 = addr64;
1051 }
1052
1053 /* Check for TCP Segmentation Offload */
1054 mss = skb_shinfo(skb)->tso_size;
1055 if (mss != 0) {
1056 /* just drop the packet if non-linear expansion fails */
1057 if (skb_header_cloned(skb) &&
1058 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
1059 dev_kfree_skb_any(skb);
1060 goto out_unlock;
1061 }
1062
1063 mss += ((skb->h.th->doff - 5) * 4); /* TCP options */
1064 mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
1065 mss += ETH_HLEN;
1066 }
1067
1068 if (mss != sky2->tx_last_mss) {
1069 le = get_tx_le(sky2);
1070 le->tx.tso.size = cpu_to_le16(mss);
1071 le->tx.tso.rsvd = 0;
1072 le->opcode = OP_LRGLEN | HW_OWNER;
1073 le->ctrl = 0;
1074 sky2->tx_last_mss = mss;
1075 }
1076
1077 ctrl = 0;
1078#ifdef SKY2_VLAN_TAG_USED
1079 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1080 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1081 if (!le) {
1082 le = get_tx_le(sky2);
1083 le->tx.addr = 0;
1084 le->opcode = OP_VLAN|HW_OWNER;
1085 le->ctrl = 0;
1086 } else
1087 le->opcode |= OP_VLAN;
1088 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1089 ctrl |= INS_VLAN;
1090 }
1091#endif
1092
1093 /* Handle TCP checksum offload */
1094 if (skb->ip_summed == CHECKSUM_HW) {
1095 u16 hdr = skb->h.raw - skb->data;
1096 u16 offset = hdr + skb->csum;
1097
1098 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1099 if (skb->nh.iph->protocol == IPPROTO_UDP)
1100 ctrl |= UDPTCP;
1101
1102 le = get_tx_le(sky2);
1103 le->tx.csum.start = cpu_to_le16(hdr);
1104 le->tx.csum.offset = cpu_to_le16(offset);
1105 le->length = 0; /* initial checksum value */
1106 le->ctrl = 1; /* one packet */
1107 le->opcode = OP_TCPLISW | HW_OWNER;
1108 }
1109
1110 le = get_tx_le(sky2);
1111 le->tx.addr = cpu_to_le32((u32) mapping);
1112 le->length = cpu_to_le16(len);
1113 le->ctrl = ctrl;
1114 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1115
1116 /* Record the transmit mapping info */
1117 re->skb = skb;
1118 re->mapaddr = mapping;
1119 re->maplen = len;
1120
1121 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1122 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1123 struct ring_info *fre;
1124
1125 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1126 frag->size, PCI_DMA_TODEVICE);
1127 addr64 = (mapping >> 16) >> 16;
1128 if (addr64 != sky2->tx_addr64) {
1129 le = get_tx_le(sky2);
1130 le->tx.addr = cpu_to_le32(addr64);
1131 le->ctrl = 0;
1132 le->opcode = OP_ADDR64 | HW_OWNER;
1133 sky2->tx_addr64 = addr64;
1134 }
1135
1136 le = get_tx_le(sky2);
1137 le->tx.addr = cpu_to_le32((u32) mapping);
1138 le->length = cpu_to_le16(frag->size);
1139 le->ctrl = ctrl;
1140 le->opcode = OP_BUFFER | HW_OWNER;
1141
1142 fre = sky2->tx_ring
1143 + ((re - sky2->tx_ring) + i + 1) % TX_RING_SIZE;
1144 fre->skb = NULL;
1145 fre->mapaddr = mapping;
1146 fre->maplen = frag->size;
1147 }
1148 re->idx = sky2->tx_prod;
1149 le->ctrl |= EOP;
1150
1151 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod,
1152 &sky2->tx_last_put, TX_RING_SIZE);
1153
1154 if (tx_avail(sky2) < MAX_SKB_TX_LE + 1)
1155 netif_stop_queue(dev);
1156
1157out_unlock:
1158 mmiowb();
1159 spin_unlock_irqrestore(&sky2->tx_lock, flags);
1160
1161 dev->trans_start = jiffies;
1162 return NETDEV_TX_OK;
1163}
1164
1165/*
1166 * Free ring elements from starting at tx_cons until "done"
1167 *
1168 * NB: the hardware will tell us about partial completion of multi-part
1169 * buffers; these are deferred until completion.
1170 */
1171static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1172{
1173 struct net_device *dev = sky2->netdev;
1174 unsigned i;
1175
1176 if (unlikely(netif_msg_tx_done(sky2)))
1177 printk(KERN_DEBUG "%s: tx done, up to %u\n",
1178 dev->name, done);
1179
1180 spin_lock(&sky2->tx_lock);
1181
1182 while (sky2->tx_cons != done) {
1183 struct ring_info *re = sky2->tx_ring + sky2->tx_cons;
1184 struct sk_buff *skb;
1185
1186 /* Check for partial status */
1187 if (tx_dist(sky2->tx_cons, done)
1188 < tx_dist(sky2->tx_cons, re->idx))
1189 goto out;
1190
1191 skb = re->skb;
1192 pci_unmap_single(sky2->hw->pdev,
1193 re->mapaddr, re->maplen, PCI_DMA_TODEVICE);
1194
1195 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1196 struct ring_info *fre;
1197 fre =
1198 sky2->tx_ring + (sky2->tx_cons + i +
1199 1) % TX_RING_SIZE;
1200 pci_unmap_page(sky2->hw->pdev, fre->mapaddr,
1201 fre->maplen, PCI_DMA_TODEVICE);
1202 }
1203
1204 dev_kfree_skb_any(skb);
1205
1206 sky2->tx_cons = re->idx;
1207 }
1208out:
1209
1210 if (netif_queue_stopped(dev) && tx_avail(sky2) > MAX_SKB_TX_LE)
1211 netif_wake_queue(dev);
1212 spin_unlock(&sky2->tx_lock);
1213}
1214
1215/* Cleanup all untransmitted buffers, assume transmitter not running */
1216static inline void sky2_tx_clean(struct sky2_port *sky2)
1217{
1218 sky2_tx_complete(sky2, sky2->tx_prod);
1219}
1220
1221/* Network shutdown */
1222static int sky2_down(struct net_device *dev)
1223{
1224 struct sky2_port *sky2 = netdev_priv(dev);
1225 struct sky2_hw *hw = sky2->hw;
1226 unsigned port = sky2->port;
1227 u16 ctrl;
1228
1229 if (netif_msg_ifdown(sky2))
1230 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1231
1232 netif_stop_queue(dev);
1233
1234 sky2_phy_reset(hw, port);
1235
1236 /* Stop transmitter */
1237 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1238 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1239
1240 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1241 RB_RST_SET | RB_DIS_OP_MD);
1242
1243 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1244 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1245 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1246
1247 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1248
1249 /* Workaround shared GMAC reset */
1250 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1251 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1252 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1253
1254 /* Disable Force Sync bit and Enable Alloc bit */
1255 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1256 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1257
1258 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1259 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1260 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1261
1262 /* Reset the PCI FIFO of the async Tx queue */
1263 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1264 BMU_RST_SET | BMU_FIFO_RST);
1265
1266 /* Reset the Tx prefetch units */
1267 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1268 PREF_UNIT_RST_SET);
1269
1270 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1271
1272 sky2_rx_stop(sky2);
1273
1274 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1275 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1276
1277 /* turn off LED's */
1278 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1279
1280 sky2_tx_clean(sky2);
1281 sky2_rx_clean(sky2);
1282
1283 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1284 sky2->rx_le, sky2->rx_le_map);
1285 kfree(sky2->rx_ring);
1286
1287 pci_free_consistent(hw->pdev,
1288 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1289 sky2->tx_le, sky2->tx_le_map);
1290 kfree(sky2->tx_ring);
1291
1292 return 0;
1293}
1294
1295static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1296{
1297 if (!hw->copper)
1298 return SPEED_1000;
1299
1300 if (hw->chip_id == CHIP_ID_YUKON_FE)
1301 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1302
1303 switch (aux & PHY_M_PS_SPEED_MSK) {
1304 case PHY_M_PS_SPEED_1000:
1305 return SPEED_1000;
1306 case PHY_M_PS_SPEED_100:
1307 return SPEED_100;
1308 default:
1309 return SPEED_10;
1310 }
1311}
1312
1313static void sky2_link_up(struct sky2_port *sky2)
1314{
1315 struct sky2_hw *hw = sky2->hw;
1316 unsigned port = sky2->port;
1317 u16 reg;
1318
1319 /* disable Rx GMAC FIFO flush mode */
1320 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
1321
1322 /* Enable Transmit FIFO Underrun */
1323 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
1324
1325 reg = gma_read16(hw, port, GM_GP_CTRL);
1326 if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE)
1327 reg |= GM_GPCR_DUP_FULL;
1328
1329 /* enable Rx/Tx */
1330 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1331 gma_write16(hw, port, GM_GP_CTRL, reg);
1332 gma_read16(hw, port, GM_GP_CTRL);
1333
1334 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1335
1336 netif_carrier_on(sky2->netdev);
1337 netif_wake_queue(sky2->netdev);
1338
1339 /* Turn on link LED */
1340 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1341 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1342
1343 if (hw->chip_id == CHIP_ID_YUKON_XL) {
1344 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1345
1346 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1347 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
1348 PHY_M_LEDC_INIT_CTRL(sky2->speed ==
1349 SPEED_10 ? 7 : 0) |
1350 PHY_M_LEDC_STA1_CTRL(sky2->speed ==
1351 SPEED_100 ? 7 : 0) |
1352 PHY_M_LEDC_STA0_CTRL(sky2->speed ==
1353 SPEED_1000 ? 7 : 0));
1354 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1355 }
1356
1357 if (netif_msg_link(sky2))
1358 printk(KERN_INFO PFX
1359 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1360 sky2->netdev->name, sky2->speed,
1361 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1362 (sky2->tx_pause && sky2->rx_pause) ? "both" :
1363 sky2->tx_pause ? "tx" : sky2->rx_pause ? "rx" : "none");
1364}
1365
1366static void sky2_link_down(struct sky2_port *sky2)
1367{
1368 struct sky2_hw *hw = sky2->hw;
1369 unsigned port = sky2->port;
1370 u16 reg;
1371
1372 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1373
1374 reg = gma_read16(hw, port, GM_GP_CTRL);
1375 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1376 gma_write16(hw, port, GM_GP_CTRL, reg);
1377 gma_read16(hw, port, GM_GP_CTRL); /* PCI post */
1378
1379 if (sky2->rx_pause && !sky2->tx_pause) {
1380 /* restore Asymmetric Pause bit */
1381 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
1382 gm_phy_read(hw, port, PHY_MARV_AUNE_ADV)
1383 | PHY_M_AN_ASP);
1384 }
1385
1386 sky2_phy_reset(hw, port);
1387
1388 netif_carrier_off(sky2->netdev);
1389 netif_stop_queue(sky2->netdev);
1390
1391 /* Turn on link LED */
1392 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1393
1394 if (netif_msg_link(sky2))
1395 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1396 sky2_phy_init(hw, port);
1397}
1398
1399static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1400{
1401 struct sky2_hw *hw = sky2->hw;
1402 unsigned port = sky2->port;
1403 u16 lpa;
1404
1405 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1406
1407 if (lpa & PHY_M_AN_RF) {
1408 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1409 return -1;
1410 }
1411
1412 if (hw->chip_id != CHIP_ID_YUKON_FE &&
1413 gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
1414 printk(KERN_ERR PFX "%s: master/slave fault",
1415 sky2->netdev->name);
1416 return -1;
1417 }
1418
1419 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1420 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1421 sky2->netdev->name);
1422 return -1;
1423 }
1424
1425 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1426
1427 sky2->speed = sky2_phy_speed(hw, aux);
1428
1429 /* Pause bits are offset (9..8) */
1430 if (hw->chip_id == CHIP_ID_YUKON_XL)
1431 aux >>= 6;
1432
1433 sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0;
1434 sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0;
1435
1436 if ((sky2->tx_pause || sky2->rx_pause)
1437 && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF))
1438 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1439 else
1440 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1441
1442 return 0;
1443}
1444
1445/*
1446 * Interrupt from PHY are handled in tasklet (soft irq)
1447 * because accessing phy registers requires spin wait which might
1448 * cause excess interrupt latency.
1449 */
1450static void sky2_phy_task(unsigned long data)
1451{
1452 struct sky2_port *sky2 = (struct sky2_port *)data;
1453 struct sky2_hw *hw = sky2->hw;
1454 u16 istatus, phystat;
1455
1456 spin_lock(&hw->phy_lock);
1457 istatus = gm_phy_read(hw, sky2->port, PHY_MARV_INT_STAT);
1458 phystat = gm_phy_read(hw, sky2->port, PHY_MARV_PHY_STAT);
1459
1460 if (netif_msg_intr(sky2))
1461 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1462 sky2->netdev->name, istatus, phystat);
1463
1464 if (istatus & PHY_M_IS_AN_COMPL) {
1465 if (sky2_autoneg_done(sky2, phystat) == 0)
1466 sky2_link_up(sky2);
1467 goto out;
1468 }
1469
1470 if (istatus & PHY_M_IS_LSP_CHANGE)
1471 sky2->speed = sky2_phy_speed(hw, phystat);
1472
1473 if (istatus & PHY_M_IS_DUP_CHANGE)
1474 sky2->duplex =
1475 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1476
1477 if (istatus & PHY_M_IS_LST_CHANGE) {
1478 if (phystat & PHY_M_PS_LINK_UP)
1479 sky2_link_up(sky2);
1480 else
1481 sky2_link_down(sky2);
1482 }
1483out:
1484 spin_unlock(&hw->phy_lock);
1485
1486 local_irq_disable();
1487 hw->intr_mask |= (sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2;
1488 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1489 local_irq_enable();
1490}
1491
1492static void sky2_tx_timeout(struct net_device *dev)
1493{
1494 struct sky2_port *sky2 = netdev_priv(dev);
1495
1496 if (netif_msg_timer(sky2))
1497 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1498
1499 sky2_write32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR), BMU_STOP);
1500 sky2_read32(sky2->hw, Q_ADDR(txqaddr[sky2->port], Q_CSR));
1501
1502 sky2_tx_clean(sky2);
1503}
1504
1505static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1506{
1507 struct sky2_port *sky2 = netdev_priv(dev);
1508 struct sky2_hw *hw = sky2->hw;
1509 int err;
1510 u16 ctl, mode;
1511
1512 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1513 return -EINVAL;
1514
1515 if (!netif_running(dev)) {
1516 dev->mtu = new_mtu;
1517 return 0;
1518 }
1519
1520 local_irq_disable();
1521 sky2_write32(hw, B0_IMSK, 0);
1522
1523 ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
1524 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1525 sky2_rx_stop(sky2);
1526 sky2_rx_clean(sky2);
1527
1528 dev->mtu = new_mtu;
1529 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1530 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1531
1532 if (dev->mtu > ETH_DATA_LEN)
1533 mode |= GM_SMOD_JUMBO_ENA;
1534
1535 gma_write16(hw, sky2->port, GM_SERIAL_MODE, mode);
1536
1537 sky2_write8(hw, RB_ADDR(rxqaddr[sky2->port], RB_CTRL), RB_ENA_OP_MD);
1538
1539 err = sky2_rx_start(sky2);
1540 gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
1541
1542 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1543 sky2_read32(hw, B0_IMSK);
1544 local_irq_enable();
1545 return err;
1546}
1547
1548/*
1549 * Receive one packet.
1550 * For small packets or errors, just reuse existing skb.
1551 * For larger packets, get new buffer.
1552 */
1553static struct sk_buff *sky2_receive(struct sky2_port *sky2,
1554 u16 length, u32 status)
1555{
1556 struct ring_info *re = sky2->rx_ring + sky2->rx_next;
1557 struct sk_buff *skb = NULL;
1558 struct net_device *dev;
1559 const unsigned int bufsize = rx_size(sky2);
1560
1561 if (unlikely(netif_msg_rx_status(sky2)))
1562 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
1563 sky2->netdev->name, sky2->rx_next, status, length);
1564
1565 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
1566
1567 if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
1568 goto error;
1569
1570 if (length < RX_COPY_THRESHOLD) {
1571 skb = alloc_skb(length + 2, GFP_ATOMIC);
1572 if (!skb)
1573 goto resubmit;
1574
1575 skb_reserve(skb, 2);
1576 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->mapaddr,
1577 length, PCI_DMA_FROMDEVICE);
1578 memcpy(skb->data, re->skb->data, length);
1579 skb->ip_summed = re->skb->ip_summed;
1580 skb->csum = re->skb->csum;
1581 pci_dma_sync_single_for_device(sky2->hw->pdev, re->mapaddr,
1582 length, PCI_DMA_FROMDEVICE);
1583 } else {
1584 struct sk_buff *nskb;
1585
1586 nskb = dev_alloc_skb(bufsize);
1587 if (!nskb)
1588 goto resubmit;
1589
1590 skb = re->skb;
1591 re->skb = nskb;
1592 pci_unmap_single(sky2->hw->pdev, re->mapaddr,
1593 re->maplen, PCI_DMA_FROMDEVICE);
1594 prefetch(skb->data);
1595
1596 re->mapaddr = pci_map_single(sky2->hw->pdev, nskb->data,
1597 bufsize, PCI_DMA_FROMDEVICE);
1598 re->maplen = bufsize;
1599 }
1600
1601 skb_put(skb, length);
1602 dev = sky2->netdev;
1603 skb->dev = dev;
1604 skb->protocol = eth_type_trans(skb, dev);
1605 dev->last_rx = jiffies;
1606
1607resubmit:
1608 re->skb->ip_summed = CHECKSUM_NONE;
1609 sky2_rx_add(sky2, re);
1610
1611 /* Tell receiver about new buffers. */
1612 sky2_put_idx(sky2->hw, rxqaddr[sky2->port], sky2->rx_put,
1613 &sky2->rx_last_put, RX_LE_SIZE);
1614
1615 return skb;
1616
1617error:
1618 if (status & GMR_FS_GOOD_FC)
1619 goto resubmit;
1620
1621 if (netif_msg_rx_err(sky2))
1622 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
1623 sky2->netdev->name, status, length);
1624
1625 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
1626 sky2->net_stats.rx_length_errors++;
1627 if (status & GMR_FS_FRAGMENT)
1628 sky2->net_stats.rx_frame_errors++;
1629 if (status & GMR_FS_CRC_ERR)
1630 sky2->net_stats.rx_crc_errors++;
1631 if (status & GMR_FS_RX_FF_OV)
1632 sky2->net_stats.rx_fifo_errors++;
1633
1634 goto resubmit;
1635}
1636
1637/* Transmit ring index in reported status block is encoded as:
1638 *
1639 * | TXS2 | TXA2 | TXS1 | TXA1
1640 */
1641static inline u16 tx_index(u8 port, u32 status, u16 len)
1642{
1643 if (port == 0)
1644 return status & 0xfff;
1645 else
1646 return ((status >> 24) & 0xff) | (len & 0xf) << 8;
1647}
1648
1649/*
1650 * Both ports share the same status interrupt, therefore there is only
1651 * one poll routine.
1652 */
1653static int sky2_poll(struct net_device *dev0, int *budget)
1654{
1655 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
1656 unsigned int to_do = min(dev0->quota, *budget);
1657 unsigned int work_done = 0;
1658 u16 hwidx;
1659
1660 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1661 BUG_ON(hwidx >= STATUS_RING_SIZE);
1662 rmb();
1663
1664 do {
1665 struct sky2_status_le *le = hw->st_le + hw->st_idx;
1666 struct sky2_port *sky2;
1667 struct sk_buff *skb;
1668 u32 status;
1669 u16 length;
1670
1671 /* Are we done yet? */
1672 if (hw->st_idx == hwidx) {
1673 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
1674 hwidx = sky2_read16(hw, STAT_PUT_IDX);
1675 if (hwidx == hw->st_idx)
1676 break;
1677 }
1678
1679 hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
1680 prefetch(&hw->st_le[hw->st_idx]);
1681
1682 BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
1683
1684 sky2 = netdev_priv(hw->dev[le->link]);
1685 status = le32_to_cpu(le->status);
1686 length = le16_to_cpu(le->length);
1687
1688 switch (le->opcode & ~HW_OWNER) {
1689 case OP_RXSTAT:
1690 skb = sky2_receive(sky2, length, status);
1691 if (!skb)
1692 break;
1693#ifdef SKY2_VLAN_TAG_USED
1694 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
1695 vlan_hwaccel_receive_skb(skb,
1696 sky2->vlgrp,
1697 be16_to_cpu(sky2->rx_tag));
1698 } else
1699#endif
1700 netif_receive_skb(skb);
1701 ++work_done;
1702 break;
1703
1704#ifdef SKY2_VLAN_TAG_USED
1705 case OP_RXVLAN:
1706 sky2->rx_tag = length;
1707 break;
1708
1709 case OP_RXCHKSVLAN:
1710 sky2->rx_tag = length;
1711 /* fall through */
1712#endif
1713 case OP_RXCHKS:
1714 skb = sky2->rx_ring[sky2->rx_next].skb;
1715 skb->ip_summed = CHECKSUM_HW;
1716 skb->csum = le16_to_cpu(status);
1717 break;
1718
1719 case OP_TXINDEXLE:
1720 sky2_tx_complete(sky2,
1721 tx_index(sky2->port, status, length));
1722 break;
1723
1724 default:
1725 if (net_ratelimit())
1726 printk(KERN_WARNING PFX
1727 "unknown status opcode 0x%x\n",
1728 le->opcode);
1729 break;
1730 }
1731
1732 le->opcode = 0; /* paranoia */
1733 } while (work_done < to_do);
1734
1735 mmiowb();
1736
1737 *budget -= work_done;
1738 dev0->quota -= work_done;
1739 if (work_done < to_do) {
1740 /*
1741 * Another chip workaround, need to restart TX timer if status
1742 * LE was handled. WA_DEV_43_418
1743 */
1744 if (is_ec_a1(hw)) {
1745 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
1746 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
1747 }
1748
1749 netif_rx_complete(dev0);
1750 hw->intr_mask |= Y2_IS_STAT_BMU;
1751 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1752 sky2_read32(hw, B0_IMSK);
1753 }
1754
1755 return work_done >= to_do;
1756
1757}
1758
1759static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
1760{
1761 struct net_device *dev = hw->dev[port];
1762
1763 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
1764 dev->name, status);
1765
1766 if (status & Y2_IS_PAR_RD1) {
1767 printk(KERN_ERR PFX "%s: ram data read parity error\n",
1768 dev->name);
1769 /* Clear IRQ */
1770 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
1771 }
1772
1773 if (status & Y2_IS_PAR_WR1) {
1774 printk(KERN_ERR PFX "%s: ram data write parity error\n",
1775 dev->name);
1776
1777 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
1778 }
1779
1780 if (status & Y2_IS_PAR_MAC1) {
1781 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
1782 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
1783 }
1784
1785 if (status & Y2_IS_PAR_RX1) {
1786 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
1787 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
1788 }
1789
1790 if (status & Y2_IS_TCP_TXA1) {
1791 printk(KERN_ERR PFX "%s: TCP segmentation error\n", dev->name);
1792 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
1793 }
1794}
1795
1796static void sky2_hw_intr(struct sky2_hw *hw)
1797{
1798 u32 status = sky2_read32(hw, B0_HWE_ISRC);
1799
1800 if (status & Y2_IS_TIST_OV)
1801 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
1802
1803 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
1804 u16 pci_err;
1805
1806 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_err);
1807 printk(KERN_ERR PFX "%s: pci hw error (0x%x)\n",
1808 pci_name(hw->pdev), pci_err);
1809
1810 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1811 pci_write_config_word(hw->pdev, PCI_STATUS,
1812 pci_err | PCI_STATUS_ERROR_BITS);
1813 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1814 }
1815
1816 if (status & Y2_IS_PCI_EXP) {
1817 /* PCI-Express uncorrectable Error occurred */
1818 u32 pex_err;
1819
1820 pci_read_config_dword(hw->pdev, PEX_UNC_ERR_STAT, &pex_err);
1821
1822 printk(KERN_ERR PFX "%s: pci express error (0x%x)\n",
1823 pci_name(hw->pdev), pex_err);
1824
1825 /* clear the interrupt */
1826 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1827 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1828 0xffffffffUL);
1829 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
1830
1831 if (pex_err & PEX_FATAL_ERRORS) {
1832 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
1833 hwmsk &= ~Y2_IS_PCI_EXP;
1834 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
1835 }
1836 }
1837
1838 if (status & Y2_HWE_L1_MASK)
1839 sky2_hw_error(hw, 0, status);
1840 status >>= 8;
1841 if (status & Y2_HWE_L1_MASK)
1842 sky2_hw_error(hw, 1, status);
1843}
1844
1845static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
1846{
1847 struct net_device *dev = hw->dev[port];
1848 struct sky2_port *sky2 = netdev_priv(dev);
1849 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
1850
1851 if (netif_msg_intr(sky2))
1852 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
1853 dev->name, status);
1854
1855 if (status & GM_IS_RX_FF_OR) {
1856 ++sky2->net_stats.rx_fifo_errors;
1857 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
1858 }
1859
1860 if (status & GM_IS_TX_FF_UR) {
1861 ++sky2->net_stats.tx_fifo_errors;
1862 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
1863 }
1864}
1865
1866static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1867{
1868 struct net_device *dev = hw->dev[port];
1869 struct sky2_port *sky2 = netdev_priv(dev);
1870
1871 hw->intr_mask &= ~(port == 0 ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
1872 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1873 tasklet_schedule(&sky2->phy_task);
1874}
1875
1876static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs)
1877{
1878 struct sky2_hw *hw = dev_id;
1879 struct net_device *dev0 = hw->dev[0];
1880 u32 status;
1881
1882 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
1883 if (status == 0 || status == ~0)
1884 return IRQ_NONE;
1885
1886 if (status & Y2_IS_HW_ERR)
1887 sky2_hw_intr(hw);
1888
1889 /* Do NAPI for Rx and Tx status */
1890 if (status & Y2_IS_STAT_BMU) {
1891 hw->intr_mask &= ~Y2_IS_STAT_BMU;
1892 sky2_write32(hw, B0_IMSK, hw->intr_mask);
1893 prefetch(&hw->st_le[hw->st_idx]);
1894
1895 if (netif_rx_schedule_test(dev0))
1896 __netif_rx_schedule(dev0);
1897 }
1898
1899 if (status & Y2_IS_IRQ_PHY1)
1900 sky2_phy_intr(hw, 0);
1901
1902 if (status & Y2_IS_IRQ_PHY2)
1903 sky2_phy_intr(hw, 1);
1904
1905 if (status & Y2_IS_IRQ_MAC1)
1906 sky2_mac_intr(hw, 0);
1907
1908 if (status & Y2_IS_IRQ_MAC2)
1909 sky2_mac_intr(hw, 1);
1910
1911 sky2_write32(hw, B0_Y2_SP_ICR, 2);
1912
1913 sky2_read32(hw, B0_IMSK);
1914
1915 return IRQ_HANDLED;
1916}
1917
1918#ifdef CONFIG_NET_POLL_CONTROLLER
1919static void sky2_netpoll(struct net_device *dev)
1920{
1921 struct sky2_port *sky2 = netdev_priv(dev);
1922
1923 sky2_intr(sky2->hw->pdev->irq, sky2->hw, NULL);
1924}
1925#endif
1926
1927/* Chip internal frequency for clock calculations */
1928static inline u32 sky2_khz(const struct sky2_hw *hw)
1929{
1930 switch (hw->chip_id) {
1931 case CHIP_ID_YUKON_EC:
1932 return 125000; /* 125 Mhz */
1933 case CHIP_ID_YUKON_FE:
1934 return 100000; /* 100 Mhz */
1935 default: /* YUKON_XL */
1936 return 156000; /* 156 Mhz */
1937 }
1938}
1939
1940static inline u32 sky2_ms2clk(const struct sky2_hw *hw, u32 ms)
1941{
1942 return sky2_khz(hw) * ms;
1943}
1944
1945static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
1946{
1947 return (sky2_khz(hw) * us) / 1000;
1948}
1949
1950static int sky2_reset(struct sky2_hw *hw)
1951{
1952 u32 ctst;
1953 u16 status;
1954 u8 t8, pmd_type;
1955 int i;
1956
1957 ctst = sky2_read32(hw, B0_CTST);
1958
1959 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1960 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
1961 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
1962 printk(KERN_ERR PFX "%s: unsupported chip type 0x%x\n",
1963 pci_name(hw->pdev), hw->chip_id);
1964 return -EOPNOTSUPP;
1965 }
1966
1967 /* ring for status responses */
1968 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
1969 &hw->st_dma);
1970 if (!hw->st_le)
1971 return -ENOMEM;
1972
1973 /* disable ASF */
1974 if (hw->chip_id <= CHIP_ID_YUKON_EC) {
1975 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
1976 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
1977 }
1978
1979 /* do a SW reset */
1980 sky2_write8(hw, B0_CTST, CS_RST_SET);
1981 sky2_write8(hw, B0_CTST, CS_RST_CLR);
1982
1983 /* clear PCI errors, if any */
1984 pci_read_config_word(hw->pdev, PCI_STATUS, &status);
1985 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
1986 pci_write_config_word(hw->pdev, PCI_STATUS,
1987 status | PCI_STATUS_ERROR_BITS);
1988
1989 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
1990
1991 /* clear any PEX errors */
1992 if (is_pciex(hw)) {
1993 u16 lstat;
1994 pci_write_config_dword(hw->pdev, PEX_UNC_ERR_STAT,
1995 0xffffffffUL);
1996 pci_read_config_word(hw->pdev, PEX_LNK_STAT, &lstat);
1997 }
1998
1999 pmd_type = sky2_read8(hw, B2_PMD_TYP);
2000 hw->copper = !(pmd_type == 'L' || pmd_type == 'S');
2001
2002 hw->ports = 1;
2003 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2004 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2005 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2006 ++hw->ports;
2007 }
2008 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2009
2010 sky2_set_power_state(hw, PCI_D0);
2011
2012 for (i = 0; i < hw->ports; i++) {
2013 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2014 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2015 }
2016
2017 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2018
2019 /* Clear I2C IRQ noise */
2020 sky2_write32(hw, B2_I2C_IRQ, 1);
2021
2022 /* turn off hardware timer (unused) */
2023 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2024 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2025
2026 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2027
2028 /* Turn on descriptor polling (every 75us) */
2029 sky2_write32(hw, B28_DPT_INI, sky2_us2clk(hw, 75));
2030 sky2_write8(hw, B28_DPT_CTRL, DPT_START);
2031
2032 /* Turn off receive timestamp */
2033 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2034 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2035
2036 /* enable the Tx Arbiters */
2037 for (i = 0; i < hw->ports; i++)
2038 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2039
2040 /* Initialize ram interface */
2041 for (i = 0; i < hw->ports; i++) {
2042 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2043
2044 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2045 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2046 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2047 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2048 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2049 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2050 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2051 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2052 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2053 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2054 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2055 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2056 }
2057
2058 if (is_pciex(hw)) {
2059 u16 pctrl;
2060
2061 /* change Max. Read Request Size to 2048 bytes */
2062 pci_read_config_word(hw->pdev, PEX_DEV_CTRL, &pctrl);
2063 pctrl &= ~PEX_DC_MAX_RRS_MSK;
2064 pctrl |= PEX_DC_MAX_RD_RQ_SIZE(4);
2065
2066
2067 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2068 pci_write_config_word(hw->pdev, PEX_DEV_CTRL, pctrl);
2069 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2070 }
2071
2072 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2073
2074 spin_lock_bh(&hw->phy_lock);
2075 for (i = 0; i < hw->ports; i++)
2076 sky2_phy_reset(hw, i);
2077 spin_unlock_bh(&hw->phy_lock);
2078
2079 memset(hw->st_le, 0, STATUS_LE_BYTES);
2080 hw->st_idx = 0;
2081
2082 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2083 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2084
2085 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2086 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2087
2088 /* Set the list last index */
2089 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2090
2091 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_ms2clk(hw, 10));
2092
2093 /* These status setup values are copied from SysKonnect's driver */
2094 if (is_ec_a1(hw)) {
2095 /* WA for dev. #4.3 */
2096 sky2_write16(hw, STAT_TX_IDX_TH, 0xfff); /* Tx Threshold */
2097
2098 /* set Status-FIFO watermark */
2099 sky2_write8(hw, STAT_FIFO_WM, 0x21); /* WA for dev. #4.18 */
2100
2101 /* set Status-FIFO ISR watermark */
2102 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x07); /* WA for dev. #4.18 */
2103
2104 } else {
2105 sky2_write16(hw, STAT_TX_IDX_TH, 0x000a);
2106
2107 /* set Status-FIFO watermark */
2108 sky2_write8(hw, STAT_FIFO_WM, 0x10);
2109
2110 /* set Status-FIFO ISR watermark */
2111 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2112 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x10);
2113
2114 else /* WA dev 4.109 */
2115 sky2_write8(hw, STAT_FIFO_ISR_WM, 0x04);
2116
2117 sky2_write32(hw, STAT_ISR_TIMER_INI, 0x0190);
2118 }
2119
2120 /* enable status unit */
2121 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2122
2123 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2124 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2125 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2126
2127 return 0;
2128}
2129
2130static inline u32 sky2_supported_modes(const struct sky2_hw *hw)
2131{
2132 u32 modes;
2133 if (hw->copper) {
2134 modes = SUPPORTED_10baseT_Half
2135 | SUPPORTED_10baseT_Full
2136 | SUPPORTED_100baseT_Half
2137 | SUPPORTED_100baseT_Full
2138 | SUPPORTED_Autoneg | SUPPORTED_TP;
2139
2140 if (hw->chip_id != CHIP_ID_YUKON_FE)
2141 modes |= SUPPORTED_1000baseT_Half
2142 | SUPPORTED_1000baseT_Full;
2143 } else
2144 modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE
2145 | SUPPORTED_Autoneg;
2146 return modes;
2147}
2148
2149static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2150{
2151 struct sky2_port *sky2 = netdev_priv(dev);
2152 struct sky2_hw *hw = sky2->hw;
2153
2154 ecmd->transceiver = XCVR_INTERNAL;
2155 ecmd->supported = sky2_supported_modes(hw);
2156 ecmd->phy_address = PHY_ADDR_MARV;
2157 if (hw->copper) {
2158 ecmd->supported = SUPPORTED_10baseT_Half
2159 | SUPPORTED_10baseT_Full
2160 | SUPPORTED_100baseT_Half
2161 | SUPPORTED_100baseT_Full
2162 | SUPPORTED_1000baseT_Half
2163 | SUPPORTED_1000baseT_Full
2164 | SUPPORTED_Autoneg | SUPPORTED_TP;
2165 ecmd->port = PORT_TP;
2166 } else
2167 ecmd->port = PORT_FIBRE;
2168
2169 ecmd->advertising = sky2->advertising;
2170 ecmd->autoneg = sky2->autoneg;
2171 ecmd->speed = sky2->speed;
2172 ecmd->duplex = sky2->duplex;
2173 return 0;
2174}
2175
2176static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2177{
2178 struct sky2_port *sky2 = netdev_priv(dev);
2179 const struct sky2_hw *hw = sky2->hw;
2180 u32 supported = sky2_supported_modes(hw);
2181
2182 if (ecmd->autoneg == AUTONEG_ENABLE) {
2183 ecmd->advertising = supported;
2184 sky2->duplex = -1;
2185 sky2->speed = -1;
2186 } else {
2187 u32 setting;
2188
2189 switch (ecmd->speed) {
2190 case SPEED_1000:
2191 if (ecmd->duplex == DUPLEX_FULL)
2192 setting = SUPPORTED_1000baseT_Full;
2193 else if (ecmd->duplex == DUPLEX_HALF)
2194 setting = SUPPORTED_1000baseT_Half;
2195 else
2196 return -EINVAL;
2197 break;
2198 case SPEED_100:
2199 if (ecmd->duplex == DUPLEX_FULL)
2200 setting = SUPPORTED_100baseT_Full;
2201 else if (ecmd->duplex == DUPLEX_HALF)
2202 setting = SUPPORTED_100baseT_Half;
2203 else
2204 return -EINVAL;
2205 break;
2206
2207 case SPEED_10:
2208 if (ecmd->duplex == DUPLEX_FULL)
2209 setting = SUPPORTED_10baseT_Full;
2210 else if (ecmd->duplex == DUPLEX_HALF)
2211 setting = SUPPORTED_10baseT_Half;
2212 else
2213 return -EINVAL;
2214 break;
2215 default:
2216 return -EINVAL;
2217 }
2218
2219 if ((setting & supported) == 0)
2220 return -EINVAL;
2221
2222 sky2->speed = ecmd->speed;
2223 sky2->duplex = ecmd->duplex;
2224 }
2225
2226 sky2->autoneg = ecmd->autoneg;
2227 sky2->advertising = ecmd->advertising;
2228
2229 if (netif_running(dev)) {
2230 sky2_down(dev);
2231 sky2_up(dev);
2232 }
2233
2234 return 0;
2235}
2236
2237static void sky2_get_drvinfo(struct net_device *dev,
2238 struct ethtool_drvinfo *info)
2239{
2240 struct sky2_port *sky2 = netdev_priv(dev);
2241
2242 strcpy(info->driver, DRV_NAME);
2243 strcpy(info->version, DRV_VERSION);
2244 strcpy(info->fw_version, "N/A");
2245 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2246}
2247
2248static const struct sky2_stat {
2249 char name[ETH_GSTRING_LEN];
2250 u16 offset;
2251} sky2_stats[] = {
2252 { "tx_bytes", GM_TXO_OK_HI },
2253 { "rx_bytes", GM_RXO_OK_HI },
2254 { "tx_broadcast", GM_TXF_BC_OK },
2255 { "rx_broadcast", GM_RXF_BC_OK },
2256 { "tx_multicast", GM_TXF_MC_OK },
2257 { "rx_multicast", GM_RXF_MC_OK },
2258 { "tx_unicast", GM_TXF_UC_OK },
2259 { "rx_unicast", GM_RXF_UC_OK },
2260 { "tx_mac_pause", GM_TXF_MPAUSE },
2261 { "rx_mac_pause", GM_RXF_MPAUSE },
2262 { "collisions", GM_TXF_SNG_COL },
2263 { "late_collision",GM_TXF_LAT_COL },
2264 { "aborted", GM_TXF_ABO_COL },
2265 { "multi_collisions", GM_TXF_MUL_COL },
2266 { "fifo_underrun", GM_TXE_FIFO_UR },
2267 { "fifo_overflow", GM_RXE_FIFO_OV },
2268 { "rx_toolong", GM_RXF_LNG_ERR },
2269 { "rx_jabber", GM_RXF_JAB_PKT },
2270 { "rx_runt", GM_RXE_FRAG },
2271 { "rx_too_long", GM_RXF_LNG_ERR },
2272 { "rx_fcs_error", GM_RXF_FCS_ERR },
2273};
2274
2275static u32 sky2_get_rx_csum(struct net_device *dev)
2276{
2277 struct sky2_port *sky2 = netdev_priv(dev);
2278
2279 return sky2->rx_csum;
2280}
2281
2282static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2283{
2284 struct sky2_port *sky2 = netdev_priv(dev);
2285
2286 sky2->rx_csum = data;
2287
2288 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2289 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2290
2291 return 0;
2292}
2293
2294static u32 sky2_get_msglevel(struct net_device *netdev)
2295{
2296 struct sky2_port *sky2 = netdev_priv(netdev);
2297 return sky2->msg_enable;
2298}
2299
2300static int sky2_nway_reset(struct net_device *dev)
2301{
2302 struct sky2_port *sky2 = netdev_priv(dev);
2303 struct sky2_hw *hw = sky2->hw;
2304
2305 if (sky2->autoneg != AUTONEG_ENABLE)
2306 return -EINVAL;
2307
2308 netif_stop_queue(dev);
2309
2310 spin_lock_irq(&hw->phy_lock);
2311 sky2_phy_reset(hw, sky2->port);
2312 sky2_phy_init(hw, sky2->port);
2313 spin_unlock_irq(&hw->phy_lock);
2314
2315 return 0;
2316}
2317
2318static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2319{
2320 struct sky2_hw *hw = sky2->hw;
2321 unsigned port = sky2->port;
2322 int i;
2323
2324 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2325 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2326 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2327 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2328
2329 for (i = 2; i < count; i++)
2330 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2331}
2332
2333static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2334{
2335 struct sky2_port *sky2 = netdev_priv(netdev);
2336 sky2->msg_enable = value;
2337}
2338
2339static int sky2_get_stats_count(struct net_device *dev)
2340{
2341 return ARRAY_SIZE(sky2_stats);
2342}
2343
2344static void sky2_get_ethtool_stats(struct net_device *dev,
2345 struct ethtool_stats *stats, u64 * data)
2346{
2347 struct sky2_port *sky2 = netdev_priv(dev);
2348
2349 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2350}
2351
2352static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2353{
2354 int i;
2355
2356 switch (stringset) {
2357 case ETH_SS_STATS:
2358 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2359 memcpy(data + i * ETH_GSTRING_LEN,
2360 sky2_stats[i].name, ETH_GSTRING_LEN);
2361 break;
2362 }
2363}
2364
2365/* Use hardware MIB variables for critical path statistics and
2366 * transmit feedback not reported at interrupt.
2367 * Other errors are accounted for in interrupt handler.
2368 */
2369static struct net_device_stats *sky2_get_stats(struct net_device *dev)
2370{
2371 struct sky2_port *sky2 = netdev_priv(dev);
2372 u64 data[13];
2373
2374 sky2_phy_stats(sky2, data, ARRAY_SIZE(data));
2375
2376 sky2->net_stats.tx_bytes = data[0];
2377 sky2->net_stats.rx_bytes = data[1];
2378 sky2->net_stats.tx_packets = data[2] + data[4] + data[6];
2379 sky2->net_stats.rx_packets = data[3] + data[5] + data[7];
2380 sky2->net_stats.multicast = data[5] + data[7];
2381 sky2->net_stats.collisions = data[10];
2382 sky2->net_stats.tx_aborted_errors = data[12];
2383
2384 return &sky2->net_stats;
2385}
2386
2387static int sky2_set_mac_address(struct net_device *dev, void *p)
2388{
2389 struct sky2_port *sky2 = netdev_priv(dev);
2390 struct sockaddr *addr = p;
2391 int err = 0;
2392
2393 if (!is_valid_ether_addr(addr->sa_data))
2394 return -EADDRNOTAVAIL;
2395
2396 sky2_down(dev);
2397 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
2398 memcpy_toio(sky2->hw->regs + B2_MAC_1 + sky2->port * 8,
2399 dev->dev_addr, ETH_ALEN);
2400 memcpy_toio(sky2->hw->regs + B2_MAC_2 + sky2->port * 8,
2401 dev->dev_addr, ETH_ALEN);
2402 if (dev->flags & IFF_UP)
2403 err = sky2_up(dev);
2404 return err;
2405}
2406
2407static void sky2_set_multicast(struct net_device *dev)
2408{
2409 struct sky2_port *sky2 = netdev_priv(dev);
2410 struct sky2_hw *hw = sky2->hw;
2411 unsigned port = sky2->port;
2412 struct dev_mc_list *list = dev->mc_list;
2413 u16 reg;
2414 u8 filter[8];
2415
2416 memset(filter, 0, sizeof(filter));
2417
2418 reg = gma_read16(hw, port, GM_RX_CTRL);
2419 reg |= GM_RXCR_UCF_ENA;
2420
2421 if (dev->flags & IFF_PROMISC) /* promiscuous */
2422 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2423 else if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 16) /* all multicast */
2424 memset(filter, 0xff, sizeof(filter));
2425 else if (dev->mc_count == 0) /* no multicast */
2426 reg &= ~GM_RXCR_MCF_ENA;
2427 else {
2428 int i;
2429 reg |= GM_RXCR_MCF_ENA;
2430
2431 for (i = 0; list && i < dev->mc_count; i++, list = list->next) {
2432 u32 bit = ether_crc(ETH_ALEN, list->dmi_addr) & 0x3f;
2433 filter[bit / 8] |= 1 << (bit % 8);
2434 }
2435 }
2436
2437 gma_write16(hw, port, GM_MC_ADDR_H1,
2438 (u16) filter[0] | ((u16) filter[1] << 8));
2439 gma_write16(hw, port, GM_MC_ADDR_H2,
2440 (u16) filter[2] | ((u16) filter[3] << 8));
2441 gma_write16(hw, port, GM_MC_ADDR_H3,
2442 (u16) filter[4] | ((u16) filter[5] << 8));
2443 gma_write16(hw, port, GM_MC_ADDR_H4,
2444 (u16) filter[6] | ((u16) filter[7] << 8));
2445
2446 gma_write16(hw, port, GM_RX_CTRL, reg);
2447}
2448
2449/* Can have one global because blinking is controlled by
2450 * ethtool and that is always under RTNL mutex
2451 */
2452static inline void sky2_led(struct sky2_hw *hw, unsigned port, int on)
2453{
2454 u16 pg;
2455
2456 spin_lock_bh(&hw->phy_lock);
2457 switch (hw->chip_id) {
2458 case CHIP_ID_YUKON_XL:
2459 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2460 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2461 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
2462 on ? (PHY_M_LEDC_LOS_CTRL(1) |
2463 PHY_M_LEDC_INIT_CTRL(7) |
2464 PHY_M_LEDC_STA1_CTRL(7) |
2465 PHY_M_LEDC_STA0_CTRL(7))
2466 : 0);
2467
2468 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2469 break;
2470
2471 default:
2472 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
2473 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
2474 on ? PHY_M_LED_MO_DUP(MO_LED_ON) |
2475 PHY_M_LED_MO_10(MO_LED_ON) |
2476 PHY_M_LED_MO_100(MO_LED_ON) |
2477 PHY_M_LED_MO_1000(MO_LED_ON) |
2478 PHY_M_LED_MO_RX(MO_LED_ON)
2479 : PHY_M_LED_MO_DUP(MO_LED_OFF) |
2480 PHY_M_LED_MO_10(MO_LED_OFF) |
2481 PHY_M_LED_MO_100(MO_LED_OFF) |
2482 PHY_M_LED_MO_1000(MO_LED_OFF) |
2483 PHY_M_LED_MO_RX(MO_LED_OFF));
2484
2485 }
2486 spin_unlock_bh(&hw->phy_lock);
2487}
2488
2489/* blink LED's for finding board */
2490static int sky2_phys_id(struct net_device *dev, u32 data)
2491{
2492 struct sky2_port *sky2 = netdev_priv(dev);
2493 struct sky2_hw *hw = sky2->hw;
2494 unsigned port = sky2->port;
2495 u16 ledctrl, ledover = 0;
2496 long ms;
2497 int onoff = 1;
2498
2499 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
2500 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
2501 else
2502 ms = data * 1000;
2503
2504 /* save initial values */
2505 spin_lock_bh(&hw->phy_lock);
2506 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2507 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2508 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2509 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2510 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2511 } else {
2512 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
2513 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
2514 }
2515 spin_unlock_bh(&hw->phy_lock);
2516
2517 while (ms > 0) {
2518 sky2_led(hw, port, onoff);
2519 onoff = !onoff;
2520
2521 if (msleep_interruptible(250))
2522 break; /* interrupted */
2523 ms -= 250;
2524 }
2525
2526 /* resume regularly scheduled programming */
2527 spin_lock_bh(&hw->phy_lock);
2528 if (hw->chip_id == CHIP_ID_YUKON_XL) {
2529 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
2530 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
2531 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
2532 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
2533 } else {
2534 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
2535 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
2536 }
2537 spin_unlock_bh(&hw->phy_lock);
2538
2539 return 0;
2540}
2541
2542static void sky2_get_pauseparam(struct net_device *dev,
2543 struct ethtool_pauseparam *ecmd)
2544{
2545 struct sky2_port *sky2 = netdev_priv(dev);
2546
2547 ecmd->tx_pause = sky2->tx_pause;
2548 ecmd->rx_pause = sky2->rx_pause;
2549 ecmd->autoneg = sky2->autoneg;
2550}
2551
2552static int sky2_set_pauseparam(struct net_device *dev,
2553 struct ethtool_pauseparam *ecmd)
2554{
2555 struct sky2_port *sky2 = netdev_priv(dev);
2556 int err = 0;
2557
2558 sky2->autoneg = ecmd->autoneg;
2559 sky2->tx_pause = ecmd->tx_pause != 0;
2560 sky2->rx_pause = ecmd->rx_pause != 0;
2561
2562 if (netif_running(dev)) {
2563 sky2_down(dev);
2564 err = sky2_up(dev);
2565 }
2566
2567 return err;
2568}
2569
2570#ifdef CONFIG_PM
2571static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2572{
2573 struct sky2_port *sky2 = netdev_priv(dev);
2574
2575 wol->supported = WAKE_MAGIC;
2576 wol->wolopts = sky2->wol ? WAKE_MAGIC : 0;
2577}
2578
2579static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2580{
2581 struct sky2_port *sky2 = netdev_priv(dev);
2582 struct sky2_hw *hw = sky2->hw;
2583
2584 if (wol->wolopts != WAKE_MAGIC && wol->wolopts != 0)
2585 return -EOPNOTSUPP;
2586
2587 sky2->wol = wol->wolopts == WAKE_MAGIC;
2588
2589 if (sky2->wol) {
2590 memcpy_toio(hw->regs + WOL_MAC_ADDR, dev->dev_addr, ETH_ALEN);
2591
2592 sky2_write16(hw, WOL_CTRL_STAT,
2593 WOL_CTL_ENA_PME_ON_MAGIC_PKT |
2594 WOL_CTL_ENA_MAGIC_PKT_UNIT);
2595 } else
2596 sky2_write16(hw, WOL_CTRL_STAT, WOL_CTL_DEFAULT);
2597
2598 return 0;
2599}
2600#endif
2601
2602static void sky2_get_ringparam(struct net_device *dev,
2603 struct ethtool_ringparam *ering)
2604{
2605 struct sky2_port *sky2 = netdev_priv(dev);
2606
2607 ering->rx_max_pending = RX_MAX_PENDING;
2608 ering->rx_mini_max_pending = 0;
2609 ering->rx_jumbo_max_pending = 0;
2610 ering->tx_max_pending = TX_RING_SIZE - 1;
2611
2612 ering->rx_pending = sky2->rx_pending;
2613 ering->rx_mini_pending = 0;
2614 ering->rx_jumbo_pending = 0;
2615 ering->tx_pending = sky2->tx_pending;
2616}
2617
2618static int sky2_set_ringparam(struct net_device *dev,
2619 struct ethtool_ringparam *ering)
2620{
2621 struct sky2_port *sky2 = netdev_priv(dev);
2622 int err = 0;
2623
2624 if (ering->rx_pending > RX_MAX_PENDING ||
2625 ering->rx_pending < 8 ||
2626 ering->tx_pending < MAX_SKB_TX_LE ||
2627 ering->tx_pending > TX_RING_SIZE - 1)
2628 return -EINVAL;
2629
2630 if (netif_running(dev))
2631 sky2_down(dev);
2632
2633 sky2->rx_pending = ering->rx_pending;
2634 sky2->tx_pending = ering->tx_pending;
2635
2636 if (netif_running(dev))
2637 err = sky2_up(dev);
2638
2639 return err;
2640}
2641
2642static int sky2_get_regs_len(struct net_device *dev)
2643{
2644 return 0x4000;
2645}
2646
2647/*
2648 * Returns copy of control register region
2649 * Note: access to the RAM address register set will cause timeouts.
2650 */
2651static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
2652 void *p)
2653{
2654 const struct sky2_port *sky2 = netdev_priv(dev);
2655 const void __iomem *io = sky2->hw->regs;
2656
2657 BUG_ON(regs->len < B3_RI_WTO_R1);
2658 regs->version = 1;
2659 memset(p, 0, regs->len);
2660
2661 memcpy_fromio(p, io, B3_RAM_ADDR);
2662
2663 memcpy_fromio(p + B3_RI_WTO_R1,
2664 io + B3_RI_WTO_R1,
2665 regs->len - B3_RI_WTO_R1);
2666}
2667
2668static struct ethtool_ops sky2_ethtool_ops = {
2669 .get_settings = sky2_get_settings,
2670 .set_settings = sky2_set_settings,
2671 .get_drvinfo = sky2_get_drvinfo,
2672 .get_msglevel = sky2_get_msglevel,
2673 .set_msglevel = sky2_set_msglevel,
2674 .nway_reset = sky2_nway_reset,
2675 .get_regs_len = sky2_get_regs_len,
2676 .get_regs = sky2_get_regs,
2677 .get_link = ethtool_op_get_link,
2678 .get_sg = ethtool_op_get_sg,
2679 .set_sg = ethtool_op_set_sg,
2680 .get_tx_csum = ethtool_op_get_tx_csum,
2681 .set_tx_csum = ethtool_op_set_tx_csum,
2682 .get_tso = ethtool_op_get_tso,
2683 .set_tso = ethtool_op_set_tso,
2684 .get_rx_csum = sky2_get_rx_csum,
2685 .set_rx_csum = sky2_set_rx_csum,
2686 .get_strings = sky2_get_strings,
2687 .get_ringparam = sky2_get_ringparam,
2688 .set_ringparam = sky2_set_ringparam,
2689 .get_pauseparam = sky2_get_pauseparam,
2690 .set_pauseparam = sky2_set_pauseparam,
2691#ifdef CONFIG_PM
2692 .get_wol = sky2_get_wol,
2693 .set_wol = sky2_set_wol,
2694#endif
2695 .phys_id = sky2_phys_id,
2696 .get_stats_count = sky2_get_stats_count,
2697 .get_ethtool_stats = sky2_get_ethtool_stats,
2698 .get_perm_addr = ethtool_op_get_perm_addr,
2699};
2700
2701/* Initialize network device */
2702static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
2703 unsigned port, int highmem)
2704{
2705 struct sky2_port *sky2;
2706 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
2707
2708 if (!dev) {
2709 printk(KERN_ERR "sky2 etherdev alloc failed");
2710 return NULL;
2711 }
2712
2713 SET_MODULE_OWNER(dev);
2714 SET_NETDEV_DEV(dev, &hw->pdev->dev);
2715 dev->open = sky2_up;
2716 dev->stop = sky2_down;
2717 dev->hard_start_xmit = sky2_xmit_frame;
2718 dev->get_stats = sky2_get_stats;
2719 dev->set_multicast_list = sky2_set_multicast;
2720 dev->set_mac_address = sky2_set_mac_address;
2721 dev->change_mtu = sky2_change_mtu;
2722 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
2723 dev->tx_timeout = sky2_tx_timeout;
2724 dev->watchdog_timeo = TX_WATCHDOG;
2725 if (port == 0)
2726 dev->poll = sky2_poll;
2727 dev->weight = NAPI_WEIGHT;
2728#ifdef CONFIG_NET_POLL_CONTROLLER
2729 dev->poll_controller = sky2_netpoll;
2730#endif
2731
2732 sky2 = netdev_priv(dev);
2733 sky2->netdev = dev;
2734 sky2->hw = hw;
2735 sky2->msg_enable = netif_msg_init(debug, default_msg);
2736
2737 spin_lock_init(&sky2->tx_lock);
2738 /* Auto speed and flow control */
2739 sky2->autoneg = AUTONEG_ENABLE;
2740 sky2->tx_pause = 0;
2741 sky2->rx_pause = 1;
2742 sky2->duplex = -1;
2743 sky2->speed = -1;
2744 sky2->advertising = sky2_supported_modes(hw);
2745 sky2->rx_csum = 1;
2746 tasklet_init(&sky2->phy_task, sky2_phy_task, (unsigned long)sky2);
2747 sky2->tx_pending = TX_DEF_PENDING;
2748 sky2->rx_pending = is_ec_a1(hw) ? 8 : RX_DEF_PENDING;
2749
2750 hw->dev[port] = dev;
2751
2752 sky2->port = port;
2753
2754 dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
2755 if (highmem)
2756 dev->features |= NETIF_F_HIGHDMA;
2757 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
2758
2759#ifdef SKY2_VLAN_TAG_USED
2760 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2761 dev->vlan_rx_register = sky2_vlan_rx_register;
2762 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
2763#endif
2764
2765 /* read the mac address */
2766 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
2767 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2768
2769 /* device is off until link detection */
2770 netif_carrier_off(dev);
2771 netif_stop_queue(dev);
2772
2773 return dev;
2774}
2775
2776static inline void sky2_show_addr(struct net_device *dev)
2777{
2778 const struct sky2_port *sky2 = netdev_priv(dev);
2779
2780 if (netif_msg_probe(sky2))
2781 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
2782 dev->name,
2783 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
2784 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
2785}
2786
2787static int __devinit sky2_probe(struct pci_dev *pdev,
2788 const struct pci_device_id *ent)
2789{
2790 struct net_device *dev, *dev1 = NULL;
2791 struct sky2_hw *hw;
2792 int err, pm_cap, using_dac = 0;
2793
2794 err = pci_enable_device(pdev);
2795 if (err) {
2796 printk(KERN_ERR PFX "%s cannot enable PCI device\n",
2797 pci_name(pdev));
2798 goto err_out;
2799 }
2800
2801 err = pci_request_regions(pdev, DRV_NAME);
2802 if (err) {
2803 printk(KERN_ERR PFX "%s cannot obtain PCI resources\n",
2804 pci_name(pdev));
2805 goto err_out;
2806 }
2807
2808 pci_set_master(pdev);
2809
2810 /* Find power-management capability. */
2811 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
2812 if (pm_cap == 0) {
2813 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
2814 "aborting.\n");
2815 err = -EIO;
2816 goto err_out_free_regions;
2817 }
2818
2819 if (sizeof(dma_addr_t) > sizeof(u32)) {
2820 err = pci_set_dma_mask(pdev, DMA_64BIT_MASK);
2821 if (!err)
2822 using_dac = 1;
2823 }
2824
2825 if (!using_dac) {
2826 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2827 if (err) {
2828 printk(KERN_ERR PFX "%s no usable DMA configuration\n",
2829 pci_name(pdev));
2830 goto err_out_free_regions;
2831 }
2832 }
2833#ifdef __BIG_ENDIAN
2834 /* byte swap descriptors in hardware */
2835 {
2836 u32 reg;
2837
2838 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
2839 reg |= PCI_REV_DESC;
2840 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
2841 }
2842#endif
2843
2844 err = -ENOMEM;
2845 hw = kmalloc(sizeof(*hw), GFP_KERNEL);
2846 if (!hw) {
2847 printk(KERN_ERR PFX "%s: cannot allocate hardware struct\n",
2848 pci_name(pdev));
2849 goto err_out_free_regions;
2850 }
2851
2852 memset(hw, 0, sizeof(*hw));
2853 hw->pdev = pdev;
2854 spin_lock_init(&hw->phy_lock);
2855
2856 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
2857 if (!hw->regs) {
2858 printk(KERN_ERR PFX "%s: cannot map device registers\n",
2859 pci_name(pdev));
2860 goto err_out_free_hw;
2861 }
2862 hw->pm_cap = pm_cap;
2863
2864 err = sky2_reset(hw);
2865 if (err)
2866 goto err_out_iounmap;
2867
2868 printk(KERN_INFO PFX "addr 0x%lx irq %d Yukon-%s (0x%x) rev %d\n",
2869 pci_resource_start(pdev, 0), pdev->irq,
2870 yukon_name[hw->chip_id - CHIP_ID_YUKON],
2871 hw->chip_id, hw->chip_rev);
2872
2873 dev = sky2_init_netdev(hw, 0, using_dac);
2874 if (!dev)
2875 goto err_out_free_pci;
2876
2877 err = register_netdev(dev);
2878 if (err) {
2879 printk(KERN_ERR PFX "%s: cannot register net device\n",
2880 pci_name(pdev));
2881 goto err_out_free_netdev;
2882 }
2883
2884 sky2_show_addr(dev);
2885
2886 if (hw->ports > 1 && (dev1 = sky2_init_netdev(hw, 1, using_dac))) {
2887 if (register_netdev(dev1) == 0)
2888 sky2_show_addr(dev1);
2889 else {
2890 /* Failure to register second port need not be fatal */
2891 printk(KERN_WARNING PFX
2892 "register of second port failed\n");
2893 hw->dev[1] = NULL;
2894 free_netdev(dev1);
2895 }
2896 }
2897
2898 err = request_irq(pdev->irq, sky2_intr, SA_SHIRQ, DRV_NAME, hw);
2899 if (err) {
2900 printk(KERN_ERR PFX "%s: cannot assign irq %d\n",
2901 pci_name(pdev), pdev->irq);
2902 goto err_out_unregister;
2903 }
2904
2905 hw->intr_mask = Y2_IS_BASE;
2906 sky2_write32(hw, B0_IMSK, hw->intr_mask);
2907
2908 pci_set_drvdata(pdev, hw);
2909
2910 return 0;
2911
2912err_out_unregister:
2913 if (dev1) {
2914 unregister_netdev(dev1);
2915 free_netdev(dev1);
2916 }
2917 unregister_netdev(dev);
2918err_out_free_netdev:
2919 free_netdev(dev);
2920err_out_free_pci:
2921 sky2_write8(hw, B0_CTST, CS_RST_SET);
2922 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2923err_out_iounmap:
2924 iounmap(hw->regs);
2925err_out_free_hw:
2926 kfree(hw);
2927err_out_free_regions:
2928 pci_release_regions(pdev);
2929 pci_disable_device(pdev);
2930err_out:
2931 return err;
2932}
2933
2934static void __devexit sky2_remove(struct pci_dev *pdev)
2935{
2936 struct sky2_hw *hw = pci_get_drvdata(pdev);
2937 struct net_device *dev0, *dev1;
2938
2939 if (!hw)
2940 return;
2941
2942 dev0 = hw->dev[0];
2943 dev1 = hw->dev[1];
2944 if (dev1)
2945 unregister_netdev(dev1);
2946 unregister_netdev(dev0);
2947
2948 sky2_write32(hw, B0_IMSK, 0);
2949 sky2_set_power_state(hw, PCI_D3hot);
2950 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
2951 sky2_write8(hw, B0_CTST, CS_RST_SET);
2952 sky2_read8(hw, B0_CTST);
2953
2954 free_irq(pdev->irq, hw);
2955 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
2956 pci_release_regions(pdev);
2957 pci_disable_device(pdev);
2958
2959 if (dev1)
2960 free_netdev(dev1);
2961 free_netdev(dev0);
2962 iounmap(hw->regs);
2963 kfree(hw);
2964
2965 pci_set_drvdata(pdev, NULL);
2966}
2967
2968#ifdef CONFIG_PM
2969static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
2970{
2971 struct sky2_hw *hw = pci_get_drvdata(pdev);
2972 int i;
2973
2974 for (i = 0; i < 2; i++) {
2975 struct net_device *dev = hw->dev[i];
2976
2977 if (dev) {
2978 if (!netif_running(dev))
2979 continue;
2980
2981 sky2_down(dev);
2982 netif_device_detach(dev);
2983 }
2984 }
2985
2986 return sky2_set_power_state(hw, pci_choose_state(pdev, state));
2987}
2988
2989static int sky2_resume(struct pci_dev *pdev)
2990{
2991 struct sky2_hw *hw = pci_get_drvdata(pdev);
2992 int i;
2993
2994 pci_restore_state(pdev);
2995 pci_enable_wake(pdev, PCI_D0, 0);
2996 sky2_set_power_state(hw, PCI_D0);
2997
2998 sky2_reset(hw);
2999
3000 for (i = 0; i < 2; i++) {
3001 struct net_device *dev = hw->dev[i];
3002 if (dev) {
3003 if (netif_running(dev)) {
3004 netif_device_attach(dev);
3005 sky2_up(dev);
3006 }
3007 }
3008 }
3009 return 0;
3010}
3011#endif
3012
3013static struct pci_driver sky2_driver = {
3014 .name = DRV_NAME,
3015 .id_table = sky2_id_table,
3016 .probe = sky2_probe,
3017 .remove = __devexit_p(sky2_remove),
3018#ifdef CONFIG_PM
3019 .suspend = sky2_suspend,
3020 .resume = sky2_resume,
3021#endif
3022};
3023
3024static int __init sky2_init_module(void)
3025{
3026 return pci_module_init(&sky2_driver);
3027}
3028
3029static void __exit sky2_cleanup_module(void)
3030{
3031 pci_unregister_driver(&sky2_driver);
3032}
3033
3034module_init(sky2_init_module);
3035module_exit(sky2_cleanup_module);
3036
3037MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3038MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3039MODULE_LICENSE("GPL");
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-22 23:01:59 -0400