diff options
author | Stephen Hemminger <shemminger@linux-foundation.org> | 2007-11-27 13:57:27 -0500 |
---|---|---|
committer | Jeff Garzik <jeff@garzik.org> | 2007-12-01 16:32:31 -0500 |
commit | b32f40c4853cdbe3d722a959fb0dd1ea048b50d0 (patch) | |
tree | 9c7f4ba709fe8f96ef1ff3280b91bf073f859520 /drivers/net/sky2.c | |
parent | e0348b9ae5374f9a24424ae680bcd80724415f60 (diff) |
sky2: revert to access PCI config via device space
Using the hardware window into PCI config space is more reliable
and smaller/faster than using the pci_config routines. It avoids issues
with MMCONFIG etc.
Reverts: 167f53d05fccb47b6eeadac7f6705b3f2f042d03
Please apply for 2.6.24
Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org>
Signed-off-by: Jeff Garzik <jeff@garzik.org>
Diffstat (limited to 'drivers/net/sky2.c')
-rw-r--r-- | drivers/net/sky2.c | 73 |
1 files changed, 35 insertions, 38 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 8c4c7430d906..65071e40959b 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -240,22 +240,21 @@ static void sky2_power_on(struct sky2_hw *hw) | |||
240 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | 240 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
241 | 241 | ||
242 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { | 242 | if (hw->flags & SKY2_HW_ADV_POWER_CTL) { |
243 | struct pci_dev *pdev = hw->pdev; | ||
244 | u32 reg; | 243 | u32 reg; |
245 | 244 | ||
246 | pci_write_config_dword(pdev, PCI_DEV_REG3, 0); | 245 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
247 | 246 | ||
248 | pci_read_config_dword(pdev, PCI_DEV_REG4, ®); | 247 | reg = sky2_pci_read32(hw, PCI_DEV_REG4); |
249 | /* set all bits to 0 except bits 15..12 and 8 */ | 248 | /* set all bits to 0 except bits 15..12 and 8 */ |
250 | reg &= P_ASPM_CONTROL_MSK; | 249 | reg &= P_ASPM_CONTROL_MSK; |
251 | pci_write_config_dword(pdev, PCI_DEV_REG4, reg); | 250 | sky2_pci_write32(hw, PCI_DEV_REG4, reg); |
252 | 251 | ||
253 | pci_read_config_dword(pdev, PCI_DEV_REG5, ®); | 252 | reg = sky2_pci_read32(hw, PCI_DEV_REG5); |
254 | /* set all bits to 0 except bits 28 & 27 */ | 253 | /* set all bits to 0 except bits 28 & 27 */ |
255 | reg &= P_CTL_TIM_VMAIN_AV_MSK; | 254 | reg &= P_CTL_TIM_VMAIN_AV_MSK; |
256 | pci_write_config_dword(pdev, PCI_DEV_REG5, reg); | 255 | sky2_pci_write32(hw, PCI_DEV_REG5, reg); |
257 | 256 | ||
258 | pci_write_config_dword(pdev, PCI_CFG_REG_1, 0); | 257 | sky2_pci_write32(hw, PCI_CFG_REG_1, 0); |
259 | 258 | ||
260 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ | 259 | /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */ |
261 | reg = sky2_read32(hw, B2_GP_IO); | 260 | reg = sky2_read32(hw, B2_GP_IO); |
@@ -619,12 +618,11 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
619 | 618 | ||
620 | static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) | 619 | static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) |
621 | { | 620 | { |
622 | struct pci_dev *pdev = hw->pdev; | ||
623 | u32 reg1; | 621 | u32 reg1; |
624 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; | 622 | static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; |
625 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; | 623 | static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA }; |
626 | 624 | ||
627 | pci_read_config_dword(pdev, PCI_DEV_REG1, ®1); | 625 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
628 | /* Turn on/off phy power saving */ | 626 | /* Turn on/off phy power saving */ |
629 | if (onoff) | 627 | if (onoff) |
630 | reg1 &= ~phy_power[port]; | 628 | reg1 &= ~phy_power[port]; |
@@ -634,8 +632,8 @@ static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) | |||
634 | if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | 632 | if (onoff && hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
635 | reg1 |= coma_mode[port]; | 633 | reg1 |= coma_mode[port]; |
636 | 634 | ||
637 | pci_write_config_dword(pdev, PCI_DEV_REG1, reg1); | 635 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
638 | pci_read_config_dword(pdev, PCI_DEV_REG1, ®1); | 636 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
639 | 637 | ||
640 | udelay(100); | 638 | udelay(100); |
641 | } | 639 | } |
@@ -704,9 +702,9 @@ static void sky2_wol_init(struct sky2_port *sky2) | |||
704 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); | 702 | sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl); |
705 | 703 | ||
706 | /* Turn on legacy PCI-Express PME mode */ | 704 | /* Turn on legacy PCI-Express PME mode */ |
707 | pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®1); | 705 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); |
708 | reg1 |= PCI_Y2_PME_LEGACY; | 706 | reg1 |= PCI_Y2_PME_LEGACY; |
709 | pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg1); | 707 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); |
710 | 708 | ||
711 | /* block receiver */ | 709 | /* block receiver */ |
712 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); | 710 | sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET); |
@@ -1322,9 +1320,10 @@ static int sky2_up(struct net_device *dev) | |||
1322 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { | 1320 | (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) { |
1323 | u16 cmd; | 1321 | u16 cmd; |
1324 | 1322 | ||
1325 | pci_read_config_word(hw->pdev, cap + PCI_X_CMD, &cmd); | 1323 | cmd = sky2_pci_read16(hw, cap + PCI_X_CMD); |
1326 | cmd &= ~PCI_X_CMD_MAX_SPLIT; | 1324 | cmd &= ~PCI_X_CMD_MAX_SPLIT; |
1327 | pci_write_config_word(hw->pdev, cap + PCI_X_CMD, cmd); | 1325 | sky2_pci_write16(hw, cap + PCI_X_CMD, cmd); |
1326 | |||
1328 | } | 1327 | } |
1329 | 1328 | ||
1330 | if (netif_msg_ifup(sky2)) | 1329 | if (netif_msg_ifup(sky2)) |
@@ -2422,12 +2421,12 @@ static void sky2_hw_intr(struct sky2_hw *hw) | |||
2422 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { | 2421 | if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) { |
2423 | u16 pci_err; | 2422 | u16 pci_err; |
2424 | 2423 | ||
2425 | pci_read_config_word(pdev, PCI_STATUS, &pci_err); | 2424 | pci_err = sky2_pci_read16(hw, PCI_STATUS); |
2426 | if (net_ratelimit()) | 2425 | if (net_ratelimit()) |
2427 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", | 2426 | dev_err(&pdev->dev, "PCI hardware error (0x%x)\n", |
2428 | pci_err); | 2427 | pci_err); |
2429 | 2428 | ||
2430 | pci_write_config_word(pdev, PCI_STATUS, | 2429 | sky2_pci_write16(hw, PCI_STATUS, |
2431 | pci_err | PCI_STATUS_ERROR_BITS); | 2430 | pci_err | PCI_STATUS_ERROR_BITS); |
2432 | } | 2431 | } |
2433 | 2432 | ||
@@ -2699,13 +2698,10 @@ static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) | |||
2699 | 2698 | ||
2700 | static int __devinit sky2_init(struct sky2_hw *hw) | 2699 | static int __devinit sky2_init(struct sky2_hw *hw) |
2701 | { | 2700 | { |
2702 | int rc; | ||
2703 | u8 t8; | 2701 | u8 t8; |
2704 | 2702 | ||
2705 | /* Enable all clocks and check for bad PCI access */ | 2703 | /* Enable all clocks and check for bad PCI access */ |
2706 | rc = pci_write_config_dword(hw->pdev, PCI_DEV_REG3, 0); | 2704 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
2707 | if (rc) | ||
2708 | return rc; | ||
2709 | 2705 | ||
2710 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | 2706 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
2711 | 2707 | ||
@@ -2802,9 +2798,9 @@ static void sky2_reset(struct sky2_hw *hw) | |||
2802 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); | 2798 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON); |
2803 | 2799 | ||
2804 | /* clear PCI errors, if any */ | 2800 | /* clear PCI errors, if any */ |
2805 | pci_read_config_word(pdev, PCI_STATUS, &status); | 2801 | status = sky2_pci_read16(hw, PCI_STATUS); |
2806 | status |= PCI_STATUS_ERROR_BITS; | 2802 | status |= PCI_STATUS_ERROR_BITS; |
2807 | pci_write_config_word(pdev, PCI_STATUS, status); | 2803 | sky2_pci_write16(hw, PCI_STATUS, status); |
2808 | 2804 | ||
2809 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); | 2805 | sky2_write8(hw, B0_CTST, CS_MRST_CLR); |
2810 | 2806 | ||
@@ -3668,32 +3664,33 @@ static int sky2_set_tso(struct net_device *dev, u32 data) | |||
3668 | static int sky2_get_eeprom_len(struct net_device *dev) | 3664 | static int sky2_get_eeprom_len(struct net_device *dev) |
3669 | { | 3665 | { |
3670 | struct sky2_port *sky2 = netdev_priv(dev); | 3666 | struct sky2_port *sky2 = netdev_priv(dev); |
3667 | struct sky2_hw *hw = sky2->hw; | ||
3671 | u16 reg2; | 3668 | u16 reg2; |
3672 | 3669 | ||
3673 | pci_read_config_word(sky2->hw->pdev, PCI_DEV_REG2, ®2); | 3670 | reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); |
3674 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); | 3671 | return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); |
3675 | } | 3672 | } |
3676 | 3673 | ||
3677 | static u32 sky2_vpd_read(struct pci_dev *pdev, int cap, u16 offset) | 3674 | static u32 sky2_vpd_read(struct sky2_hw *hw, int cap, u16 offset) |
3678 | { | 3675 | { |
3679 | u32 val; | 3676 | u32 val; |
3680 | 3677 | ||
3681 | pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset); | 3678 | sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset); |
3682 | 3679 | ||
3683 | do { | 3680 | do { |
3684 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); | 3681 | offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR); |
3685 | } while (!(offset & PCI_VPD_ADDR_F)); | 3682 | } while (!(offset & PCI_VPD_ADDR_F)); |
3686 | 3683 | ||
3687 | pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val); | 3684 | val = sky2_pci_read32(hw, cap + PCI_VPD_DATA); |
3688 | return val; | 3685 | return val; |
3689 | } | 3686 | } |
3690 | 3687 | ||
3691 | static void sky2_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val) | 3688 | static void sky2_vpd_write(struct sky2_hw *hw, int cap, u16 offset, u32 val) |
3692 | { | 3689 | { |
3693 | pci_write_config_word(pdev, cap + PCI_VPD_DATA, val); | 3690 | sky2_pci_write16(hw, cap + PCI_VPD_DATA, val); |
3694 | pci_write_config_dword(pdev, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); | 3691 | sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F); |
3695 | do { | 3692 | do { |
3696 | pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset); | 3693 | offset = sky2_pci_read16(hw, cap + PCI_VPD_ADDR); |
3697 | } while (offset & PCI_VPD_ADDR_F); | 3694 | } while (offset & PCI_VPD_ADDR_F); |
3698 | } | 3695 | } |
3699 | 3696 | ||
@@ -3711,7 +3708,7 @@ static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom | |||
3711 | eeprom->magic = SKY2_EEPROM_MAGIC; | 3708 | eeprom->magic = SKY2_EEPROM_MAGIC; |
3712 | 3709 | ||
3713 | while (length > 0) { | 3710 | while (length > 0) { |
3714 | u32 val = sky2_vpd_read(sky2->hw->pdev, cap, offset); | 3711 | u32 val = sky2_vpd_read(sky2->hw, cap, offset); |
3715 | int n = min_t(int, length, sizeof(val)); | 3712 | int n = min_t(int, length, sizeof(val)); |
3716 | 3713 | ||
3717 | memcpy(data, &val, n); | 3714 | memcpy(data, &val, n); |
@@ -3741,10 +3738,10 @@ static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom | |||
3741 | int n = min_t(int, length, sizeof(val)); | 3738 | int n = min_t(int, length, sizeof(val)); |
3742 | 3739 | ||
3743 | if (n < sizeof(val)) | 3740 | if (n < sizeof(val)) |
3744 | val = sky2_vpd_read(sky2->hw->pdev, cap, offset); | 3741 | val = sky2_vpd_read(sky2->hw, cap, offset); |
3745 | memcpy(&val, data, n); | 3742 | memcpy(&val, data, n); |
3746 | 3743 | ||
3747 | sky2_vpd_write(sky2->hw->pdev, cap, offset, val); | 3744 | sky2_vpd_write(sky2->hw, cap, offset, val); |
3748 | 3745 | ||
3749 | length -= n; | 3746 | length -= n; |
3750 | data += n; | 3747 | data += n; |
@@ -4180,9 +4177,9 @@ static int __devinit sky2_probe(struct pci_dev *pdev, | |||
4180 | */ | 4177 | */ |
4181 | { | 4178 | { |
4182 | u32 reg; | 4179 | u32 reg; |
4183 | pci_read_config_dword(pdev,PCI_DEV_REG2, ®); | 4180 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); |
4184 | reg &= ~PCI_REV_DESC; | 4181 | reg &= ~PCI_REV_DESC; |
4185 | pci_write_config_dword(pdev, PCI_DEV_REG2, reg); | 4182 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); |
4186 | } | 4183 | } |
4187 | #endif | 4184 | #endif |
4188 | 4185 | ||
@@ -4373,7 +4370,7 @@ static int sky2_resume(struct pci_dev *pdev) | |||
4373 | if (hw->chip_id == CHIP_ID_YUKON_EX || | 4370 | if (hw->chip_id == CHIP_ID_YUKON_EX || |
4374 | hw->chip_id == CHIP_ID_YUKON_EC_U || | 4371 | hw->chip_id == CHIP_ID_YUKON_EC_U || |
4375 | hw->chip_id == CHIP_ID_YUKON_FE_P) | 4372 | hw->chip_id == CHIP_ID_YUKON_FE_P) |
4376 | pci_write_config_dword(pdev, PCI_DEV_REG3, 0); | 4373 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
4377 | 4374 | ||
4378 | sky2_reset(hw); | 4375 | sky2_reset(hw); |
4379 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); | 4376 | sky2_write32(hw, B0_IMSK, Y2_IS_BASE); |