diff options
author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-09-24 13:15:13 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-09-24 13:15:13 -0400 |
commit | a319a2773a13bab56a0d0b3744ba8703324313b5 (patch) | |
tree | f02c86acabd1031439fd422a167784007e84ebb1 /drivers/net/sky2.c | |
parent | e18fa700c9a31360bc8f193aa543b7ef7b39a06b (diff) | |
parent | 183798799216fad36c7219fe8d4d6dee6b8fa755 (diff) |
Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6
* 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik/netdev-2.6: (217 commits)
net/ieee80211: fix more crypto-related build breakage
[PATCH] Spidernet: add ethtool -S (show statistics)
[NET] GT96100: Delete bitrotting ethernet driver
[PATCH] mv643xx_eth: restrict to 32-bit PPC_MULTIPLATFORM
[PATCH] Cirrus Logic ep93xx ethernet driver
r8169: the MMIO region of the 8167 stands behin BAR#1
e1000, ixgb: Remove pointless wrappers
[PATCH] Remove powerpc specific parts of 3c509 driver
[PATCH] s2io: Switch to pci_get_device
[PATCH] gt96100: move to pci_get_device API
[PATCH] ehea: bugfix for register access functions
[PATCH] e1000 disable device on PCI error
drivers/net/phy/fixed: #if 0 some incomplete code
drivers/net: const-ify ethtool_ops declarations
[PATCH] ethtool: allow const ethtool_ops
[PATCH] sky2: big endian
[PATCH] sky2: fiber support
[PATCH] sky2: tx pause bug fix
drivers/net: Trim trailing whitespace
[PATCH] ehea: IBM eHEA Ethernet Device Driver
...
Manually resolved conflicts in drivers/net/ixgb/ixgb_main.c and
drivers/net/sky2.c related to CHECKSUM_HW/CHECKSUM_PARTIAL changes by
commit 84fa7933a33f806bbbaae6775e87459b1ec584c0 that just happened to be
next to unrelated changes in this update.
Diffstat (limited to 'drivers/net/sky2.c')
-rw-r--r-- | drivers/net/sky2.c | 423 |
1 files changed, 203 insertions, 220 deletions
diff --git a/drivers/net/sky2.c b/drivers/net/sky2.c index 8e92566b587e..7eeefa2d6c89 100644 --- a/drivers/net/sky2.c +++ b/drivers/net/sky2.c | |||
@@ -50,7 +50,7 @@ | |||
50 | #include "sky2.h" | 50 | #include "sky2.h" |
51 | 51 | ||
52 | #define DRV_NAME "sky2" | 52 | #define DRV_NAME "sky2" |
53 | #define DRV_VERSION "1.5" | 53 | #define DRV_VERSION "1.7" |
54 | #define PFX DRV_NAME " " | 54 | #define PFX DRV_NAME " " |
55 | 55 | ||
56 | /* | 56 | /* |
@@ -106,6 +106,7 @@ static const struct pci_device_id sky2_id_table[] = { | |||
106 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, | 106 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, |
107 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, | 107 | { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, |
108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ | 108 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */ |
109 | { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */ | ||
109 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, | 110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, |
110 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, | 111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, |
111 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, | 112 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, |
@@ -117,10 +118,17 @@ static const struct pci_device_id sky2_id_table[] = { | |||
117 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, | 118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, |
118 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, | 119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, |
119 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, | 120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, | ||
120 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, | 122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, |
121 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, | 123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, |
122 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, | 124 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, |
123 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, | 125 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, |
126 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, | ||
127 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, | ||
128 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, | ||
129 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, | ||
130 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, | ||
131 | { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, | ||
124 | { 0 } | 132 | { 0 } |
125 | }; | 133 | }; |
126 | 134 | ||
@@ -190,7 +198,6 @@ static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg) | |||
190 | static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | 198 | static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) |
191 | { | 199 | { |
192 | u16 power_control; | 200 | u16 power_control; |
193 | u32 reg1; | ||
194 | int vaux; | 201 | int vaux; |
195 | 202 | ||
196 | pr_debug("sky2_set_power_state %d\n", state); | 203 | pr_debug("sky2_set_power_state %d\n", state); |
@@ -223,20 +230,9 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | |||
223 | else | 230 | else |
224 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | 231 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
225 | 232 | ||
226 | /* Turn off phy power saving */ | ||
227 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); | ||
228 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | ||
229 | |||
230 | /* looks like this XL is back asswards .. */ | ||
231 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) { | ||
232 | reg1 |= PCI_Y2_PHY1_COMA; | ||
233 | if (hw->ports > 1) | ||
234 | reg1 |= PCI_Y2_PHY2_COMA; | ||
235 | } | ||
236 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | ||
237 | udelay(100); | ||
238 | |||
239 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { | 233 | if (hw->chip_id == CHIP_ID_YUKON_EC_U) { |
234 | u32 reg1; | ||
235 | |||
240 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); | 236 | sky2_pci_write32(hw, PCI_DEV_REG3, 0); |
241 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); | 237 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG4); |
242 | reg1 &= P_ASPM_CONTROL_MSK; | 238 | reg1 &= P_ASPM_CONTROL_MSK; |
@@ -248,15 +244,6 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | |||
248 | 244 | ||
249 | case PCI_D3hot: | 245 | case PCI_D3hot: |
250 | case PCI_D3cold: | 246 | case PCI_D3cold: |
251 | /* Turn on phy power saving */ | ||
252 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); | ||
253 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | ||
254 | reg1 &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | ||
255 | else | ||
256 | reg1 |= (PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); | ||
257 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | ||
258 | udelay(100); | ||
259 | |||
260 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | 247 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) |
261 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); | 248 | sky2_write8(hw, B2_Y2_CLK_GATE, 0); |
262 | else | 249 | else |
@@ -280,7 +267,7 @@ static void sky2_set_power_state(struct sky2_hw *hw, pci_power_t state) | |||
280 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); | 267 | sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF); |
281 | } | 268 | } |
282 | 269 | ||
283 | static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) | 270 | static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port) |
284 | { | 271 | { |
285 | u16 reg; | 272 | u16 reg; |
286 | 273 | ||
@@ -302,7 +289,7 @@ static void sky2_phy_reset(struct sky2_hw *hw, unsigned port) | |||
302 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | 289 | static void sky2_phy_init(struct sky2_hw *hw, unsigned port) |
303 | { | 290 | { |
304 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); | 291 | struct sky2_port *sky2 = netdev_priv(hw->dev[port]); |
305 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover; | 292 | u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg; |
306 | 293 | ||
307 | if (sky2->autoneg == AUTONEG_ENABLE && | 294 | if (sky2->autoneg == AUTONEG_ENABLE && |
308 | !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { | 295 | !(hw->chip_id == CHIP_ID_YUKON_XL || hw->chip_id == CHIP_ID_YUKON_EC_U)) { |
@@ -321,7 +308,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
321 | } | 308 | } |
322 | 309 | ||
323 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | 310 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); |
324 | if (hw->copper) { | 311 | if (sky2_is_copper(hw)) { |
325 | if (hw->chip_id == CHIP_ID_YUKON_FE) { | 312 | if (hw->chip_id == CHIP_ID_YUKON_FE) { |
326 | /* enable automatic crossover */ | 313 | /* enable automatic crossover */ |
327 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; | 314 | ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1; |
@@ -338,25 +325,37 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
338 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; | 325 | ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA; |
339 | } | 326 | } |
340 | } | 327 | } |
341 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | ||
342 | } else { | 328 | } else { |
343 | /* workaround for deviation #4.88 (CRC errors) */ | 329 | /* workaround for deviation #4.88 (CRC errors) */ |
344 | /* disable Automatic Crossover */ | 330 | /* disable Automatic Crossover */ |
345 | 331 | ||
346 | ctrl &= ~PHY_M_PC_MDIX_MSK; | 332 | ctrl &= ~PHY_M_PC_MDIX_MSK; |
347 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | 333 | } |
348 | 334 | ||
349 | if (hw->chip_id == CHIP_ID_YUKON_XL) { | 335 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); |
350 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | 336 | |
351 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | 337 | /* special setup for PHY 88E1112 Fiber */ |
352 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | 338 | if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) { |
353 | ctrl &= ~PHY_M_MAC_MD_MSK; | 339 | pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR); |
354 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | ||
355 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | ||
356 | 340 | ||
341 | /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ | ||
342 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2); | ||
343 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | ||
344 | ctrl &= ~PHY_M_MAC_MD_MSK; | ||
345 | ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX); | ||
346 | gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl); | ||
347 | |||
348 | if (hw->pmd_type == 'P') { | ||
357 | /* select page 1 to access Fiber registers */ | 349 | /* select page 1 to access Fiber registers */ |
358 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); | 350 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1); |
351 | |||
352 | /* for SFP-module set SIGDET polarity to low */ | ||
353 | ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL); | ||
354 | ctrl |= PHY_M_FIB_SIGD_POL; | ||
355 | gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl); | ||
359 | } | 356 | } |
357 | |||
358 | gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg); | ||
360 | } | 359 | } |
361 | 360 | ||
362 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); | 361 | ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL); |
@@ -371,9 +370,10 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
371 | ctrl = 0; | 370 | ctrl = 0; |
372 | ct1000 = 0; | 371 | ct1000 = 0; |
373 | adv = PHY_AN_CSMA; | 372 | adv = PHY_AN_CSMA; |
373 | reg = 0; | ||
374 | 374 | ||
375 | if (sky2->autoneg == AUTONEG_ENABLE) { | 375 | if (sky2->autoneg == AUTONEG_ENABLE) { |
376 | if (hw->copper) { | 376 | if (sky2_is_copper(hw)) { |
377 | if (sky2->advertising & ADVERTISED_1000baseT_Full) | 377 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
378 | ct1000 |= PHY_M_1000C_AFD; | 378 | ct1000 |= PHY_M_1000C_AFD; |
379 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | 379 | if (sky2->advertising & ADVERTISED_1000baseT_Half) |
@@ -386,8 +386,12 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
386 | adv |= PHY_M_AN_10_FD; | 386 | adv |= PHY_M_AN_10_FD; |
387 | if (sky2->advertising & ADVERTISED_10baseT_Half) | 387 | if (sky2->advertising & ADVERTISED_10baseT_Half) |
388 | adv |= PHY_M_AN_10_HD; | 388 | adv |= PHY_M_AN_10_HD; |
389 | } else /* special defines for FIBER (88E1011S only) */ | 389 | } else { /* special defines for FIBER (88E1040S only) */ |
390 | adv |= PHY_M_AN_1000X_AHD | PHY_M_AN_1000X_AFD; | 390 | if (sky2->advertising & ADVERTISED_1000baseT_Full) |
391 | adv |= PHY_M_AN_1000X_AFD; | ||
392 | if (sky2->advertising & ADVERTISED_1000baseT_Half) | ||
393 | adv |= PHY_M_AN_1000X_AHD; | ||
394 | } | ||
391 | 395 | ||
392 | /* Set Flow-control capabilities */ | 396 | /* Set Flow-control capabilities */ |
393 | if (sky2->tx_pause && sky2->rx_pause) | 397 | if (sky2->tx_pause && sky2->rx_pause) |
@@ -403,21 +407,46 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
403 | /* forced speed/duplex settings */ | 407 | /* forced speed/duplex settings */ |
404 | ct1000 = PHY_M_1000C_MSE; | 408 | ct1000 = PHY_M_1000C_MSE; |
405 | 409 | ||
406 | if (sky2->duplex == DUPLEX_FULL) | 410 | /* Disable auto update for duplex flow control and speed */ |
407 | ctrl |= PHY_CT_DUP_MD; | 411 | reg |= GM_GPCR_AU_ALL_DIS; |
408 | 412 | ||
409 | switch (sky2->speed) { | 413 | switch (sky2->speed) { |
410 | case SPEED_1000: | 414 | case SPEED_1000: |
411 | ctrl |= PHY_CT_SP1000; | 415 | ctrl |= PHY_CT_SP1000; |
416 | reg |= GM_GPCR_SPEED_1000; | ||
412 | break; | 417 | break; |
413 | case SPEED_100: | 418 | case SPEED_100: |
414 | ctrl |= PHY_CT_SP100; | 419 | ctrl |= PHY_CT_SP100; |
420 | reg |= GM_GPCR_SPEED_100; | ||
415 | break; | 421 | break; |
416 | } | 422 | } |
417 | 423 | ||
424 | if (sky2->duplex == DUPLEX_FULL) { | ||
425 | reg |= GM_GPCR_DUP_FULL; | ||
426 | ctrl |= PHY_CT_DUP_MD; | ||
427 | } else if (sky2->speed != SPEED_1000 && hw->chip_id != CHIP_ID_YUKON_EC_U) { | ||
428 | /* Turn off flow control for 10/100mbps */ | ||
429 | sky2->rx_pause = 0; | ||
430 | sky2->tx_pause = 0; | ||
431 | } | ||
432 | |||
433 | if (!sky2->rx_pause) | ||
434 | reg |= GM_GPCR_FC_RX_DIS; | ||
435 | |||
436 | if (!sky2->tx_pause) | ||
437 | reg |= GM_GPCR_FC_TX_DIS; | ||
438 | |||
439 | /* Forward pause packets to GMAC? */ | ||
440 | if (sky2->tx_pause || sky2->rx_pause) | ||
441 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | ||
442 | else | ||
443 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | ||
444 | |||
418 | ctrl |= PHY_CT_RESET; | 445 | ctrl |= PHY_CT_RESET; |
419 | } | 446 | } |
420 | 447 | ||
448 | gma_write16(hw, port, GM_GP_CTRL, reg); | ||
449 | |||
421 | if (hw->chip_id != CHIP_ID_YUKON_FE) | 450 | if (hw->chip_id != CHIP_ID_YUKON_FE) |
422 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); | 451 | gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000); |
423 | 452 | ||
@@ -521,6 +550,7 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
521 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); | 550 | gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover); |
522 | 551 | ||
523 | } | 552 | } |
553 | |||
524 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ | 554 | /* Enable phy interrupt on auto-negotiation complete (or link up) */ |
525 | if (sky2->autoneg == AUTONEG_ENABLE) | 555 | if (sky2->autoneg == AUTONEG_ENABLE) |
526 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); | 556 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL); |
@@ -528,6 +558,29 @@ static void sky2_phy_init(struct sky2_hw *hw, unsigned port) | |||
528 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | 558 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); |
529 | } | 559 | } |
530 | 560 | ||
561 | static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff) | ||
562 | { | ||
563 | u32 reg1; | ||
564 | static const u32 phy_power[] | ||
565 | = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD }; | ||
566 | |||
567 | /* looks like this XL is back asswards .. */ | ||
568 | if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1) | ||
569 | onoff = !onoff; | ||
570 | |||
571 | reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); | ||
572 | |||
573 | if (onoff) | ||
574 | /* Turn off phy power saving */ | ||
575 | reg1 &= ~phy_power[port]; | ||
576 | else | ||
577 | reg1 |= phy_power[port]; | ||
578 | |||
579 | sky2_pci_write32(hw, PCI_DEV_REG1, reg1); | ||
580 | sky2_pci_read32(hw, PCI_DEV_REG1); | ||
581 | udelay(100); | ||
582 | } | ||
583 | |||
531 | /* Force a renegotiation */ | 584 | /* Force a renegotiation */ |
532 | static void sky2_phy_reinit(struct sky2_port *sky2) | 585 | static void sky2_phy_reinit(struct sky2_port *sky2) |
533 | { | 586 | { |
@@ -560,49 +613,11 @@ static void sky2_mac_init(struct sky2_hw *hw, unsigned port) | |||
560 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); | 613 | gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0); |
561 | } | 614 | } |
562 | 615 | ||
563 | if (sky2->autoneg == AUTONEG_DISABLE) { | ||
564 | reg = gma_read16(hw, port, GM_GP_CTRL); | ||
565 | reg |= GM_GPCR_AU_ALL_DIS; | ||
566 | gma_write16(hw, port, GM_GP_CTRL, reg); | ||
567 | gma_read16(hw, port, GM_GP_CTRL); | ||
568 | |||
569 | switch (sky2->speed) { | ||
570 | case SPEED_1000: | ||
571 | reg &= ~GM_GPCR_SPEED_100; | ||
572 | reg |= GM_GPCR_SPEED_1000; | ||
573 | break; | ||
574 | case SPEED_100: | ||
575 | reg &= ~GM_GPCR_SPEED_1000; | ||
576 | reg |= GM_GPCR_SPEED_100; | ||
577 | break; | ||
578 | case SPEED_10: | ||
579 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | ||
580 | break; | ||
581 | } | ||
582 | |||
583 | if (sky2->duplex == DUPLEX_FULL) | ||
584 | reg |= GM_GPCR_DUP_FULL; | ||
585 | |||
586 | /* turn off pause in 10/100mbps half duplex */ | ||
587 | else if (sky2->speed != SPEED_1000 && | ||
588 | hw->chip_id != CHIP_ID_YUKON_EC_U) | ||
589 | sky2->tx_pause = sky2->rx_pause = 0; | ||
590 | } else | ||
591 | reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL; | ||
592 | |||
593 | if (!sky2->tx_pause && !sky2->rx_pause) { | ||
594 | sky2_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | ||
595 | reg |= | ||
596 | GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | ||
597 | } else if (sky2->tx_pause && !sky2->rx_pause) { | ||
598 | /* disable Rx flow-control */ | ||
599 | reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS; | ||
600 | } | ||
601 | |||
602 | gma_write16(hw, port, GM_GP_CTRL, reg); | ||
603 | |||
604 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); | 616 | sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC)); |
605 | 617 | ||
618 | /* Enable Transmit FIFO Underrun */ | ||
619 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); | ||
620 | |||
606 | spin_lock_bh(&sky2->phy_lock); | 621 | spin_lock_bh(&sky2->phy_lock); |
607 | sky2_phy_init(hw, port); | 622 | sky2_phy_init(hw, port); |
608 | spin_unlock_bh(&sky2->phy_lock); | 623 | spin_unlock_bh(&sky2->phy_lock); |
@@ -760,9 +775,10 @@ static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2) | |||
760 | /* Update chip's next pointer */ | 775 | /* Update chip's next pointer */ |
761 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) | 776 | static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx) |
762 | { | 777 | { |
778 | q = Y2_QADDR(q, PREF_UNIT_PUT_IDX); | ||
763 | wmb(); | 779 | wmb(); |
764 | sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx); | 780 | sky2_write16(hw, q, idx); |
765 | mmiowb(); | 781 | sky2_read16(hw, q); |
766 | } | 782 | } |
767 | 783 | ||
768 | 784 | ||
@@ -811,7 +827,7 @@ static void rx_set_checksum(struct sky2_port *sky2) | |||
811 | struct sky2_rx_le *le; | 827 | struct sky2_rx_le *le; |
812 | 828 | ||
813 | le = sky2_next_rx(sky2); | 829 | le = sky2_next_rx(sky2); |
814 | le->addr = (ETH_HLEN << 16) | ETH_HLEN; | 830 | le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN); |
815 | le->ctrl = 0; | 831 | le->ctrl = 0; |
816 | le->opcode = OP_TCPSTART | HW_OWNER; | 832 | le->opcode = OP_TCPSTART | HW_OWNER; |
817 | 833 | ||
@@ -949,14 +965,16 @@ static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid) | |||
949 | /* | 965 | /* |
950 | * It appears the hardware has a bug in the FIFO logic that | 966 | * It appears the hardware has a bug in the FIFO logic that |
951 | * cause it to hang if the FIFO gets overrun and the receive buffer | 967 | * cause it to hang if the FIFO gets overrun and the receive buffer |
952 | * is not aligned. ALso alloc_skb() won't align properly if slab | 968 | * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is |
953 | * debugging is enabled. | 969 | * aligned except if slab debugging is enabled. |
954 | */ | 970 | */ |
955 | static inline struct sk_buff *sky2_alloc_skb(unsigned int size, gfp_t gfp_mask) | 971 | static inline struct sk_buff *sky2_alloc_skb(struct net_device *dev, |
972 | unsigned int length, | ||
973 | gfp_t gfp_mask) | ||
956 | { | 974 | { |
957 | struct sk_buff *skb; | 975 | struct sk_buff *skb; |
958 | 976 | ||
959 | skb = alloc_skb(size + RX_SKB_ALIGN, gfp_mask); | 977 | skb = __netdev_alloc_skb(dev, length + RX_SKB_ALIGN, gfp_mask); |
960 | if (likely(skb)) { | 978 | if (likely(skb)) { |
961 | unsigned long p = (unsigned long) skb->data; | 979 | unsigned long p = (unsigned long) skb->data; |
962 | skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); | 980 | skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p); |
@@ -992,7 +1010,8 @@ static int sky2_rx_start(struct sky2_port *sky2) | |||
992 | for (i = 0; i < sky2->rx_pending; i++) { | 1010 | for (i = 0; i < sky2->rx_pending; i++) { |
993 | struct ring_info *re = sky2->rx_ring + i; | 1011 | struct ring_info *re = sky2->rx_ring + i; |
994 | 1012 | ||
995 | re->skb = sky2_alloc_skb(sky2->rx_bufsize, GFP_KERNEL); | 1013 | re->skb = sky2_alloc_skb(sky2->netdev, sky2->rx_bufsize, |
1014 | GFP_KERNEL); | ||
996 | if (!re->skb) | 1015 | if (!re->skb) |
997 | goto nomem; | 1016 | goto nomem; |
998 | 1017 | ||
@@ -1080,6 +1099,8 @@ static int sky2_up(struct net_device *dev) | |||
1080 | if (!sky2->rx_ring) | 1099 | if (!sky2->rx_ring) |
1081 | goto err_out; | 1100 | goto err_out; |
1082 | 1101 | ||
1102 | sky2_phy_power(hw, port, 1); | ||
1103 | |||
1083 | sky2_mac_init(hw, port); | 1104 | sky2_mac_init(hw, port); |
1084 | 1105 | ||
1085 | /* Determine available ram buffer space (in 4K blocks). | 1106 | /* Determine available ram buffer space (in 4K blocks). |
@@ -1184,7 +1205,6 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |||
1184 | struct sky2_tx_le *le = NULL; | 1205 | struct sky2_tx_le *le = NULL; |
1185 | struct tx_ring_info *re; | 1206 | struct tx_ring_info *re; |
1186 | unsigned i, len; | 1207 | unsigned i, len; |
1187 | int avail; | ||
1188 | dma_addr_t mapping; | 1208 | dma_addr_t mapping; |
1189 | u32 addr64; | 1209 | u32 addr64; |
1190 | u16 mss; | 1210 | u16 mss; |
@@ -1225,7 +1245,7 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |||
1225 | /* Send high bits if changed or crosses boundary */ | 1245 | /* Send high bits if changed or crosses boundary */ |
1226 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { | 1246 | if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) { |
1227 | le = get_tx_le(sky2); | 1247 | le = get_tx_le(sky2); |
1228 | le->tx.addr = cpu_to_le32(addr64); | 1248 | le->addr = cpu_to_le32(addr64); |
1229 | le->ctrl = 0; | 1249 | le->ctrl = 0; |
1230 | le->opcode = OP_ADDR64 | HW_OWNER; | 1250 | le->opcode = OP_ADDR64 | HW_OWNER; |
1231 | sky2->tx_addr64 = high32(mapping + len); | 1251 | sky2->tx_addr64 = high32(mapping + len); |
@@ -1234,25 +1254,17 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |||
1234 | /* Check for TCP Segmentation Offload */ | 1254 | /* Check for TCP Segmentation Offload */ |
1235 | mss = skb_shinfo(skb)->gso_size; | 1255 | mss = skb_shinfo(skb)->gso_size; |
1236 | if (mss != 0) { | 1256 | if (mss != 0) { |
1237 | /* just drop the packet if non-linear expansion fails */ | ||
1238 | if (skb_header_cloned(skb) && | ||
1239 | pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) { | ||
1240 | dev_kfree_skb(skb); | ||
1241 | goto out_unlock; | ||
1242 | } | ||
1243 | |||
1244 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ | 1257 | mss += ((skb->h.th->doff - 5) * 4); /* TCP options */ |
1245 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); | 1258 | mss += (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr); |
1246 | mss += ETH_HLEN; | 1259 | mss += ETH_HLEN; |
1247 | } | ||
1248 | 1260 | ||
1249 | if (mss != sky2->tx_last_mss) { | 1261 | if (mss != sky2->tx_last_mss) { |
1250 | le = get_tx_le(sky2); | 1262 | le = get_tx_le(sky2); |
1251 | le->tx.tso.size = cpu_to_le16(mss); | 1263 | le->addr = cpu_to_le32(mss); |
1252 | le->tx.tso.rsvd = 0; | 1264 | le->opcode = OP_LRGLEN | HW_OWNER; |
1253 | le->opcode = OP_LRGLEN | HW_OWNER; | 1265 | le->ctrl = 0; |
1254 | le->ctrl = 0; | 1266 | sky2->tx_last_mss = mss; |
1255 | sky2->tx_last_mss = mss; | 1267 | } |
1256 | } | 1268 | } |
1257 | 1269 | ||
1258 | ctrl = 0; | 1270 | ctrl = 0; |
@@ -1261,7 +1273,7 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |||
1261 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { | 1273 | if (sky2->vlgrp && vlan_tx_tag_present(skb)) { |
1262 | if (!le) { | 1274 | if (!le) { |
1263 | le = get_tx_le(sky2); | 1275 | le = get_tx_le(sky2); |
1264 | le->tx.addr = 0; | 1276 | le->addr = 0; |
1265 | le->opcode = OP_VLAN|HW_OWNER; | 1277 | le->opcode = OP_VLAN|HW_OWNER; |
1266 | le->ctrl = 0; | 1278 | le->ctrl = 0; |
1267 | } else | 1279 | } else |
@@ -1273,23 +1285,29 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |||
1273 | 1285 | ||
1274 | /* Handle TCP checksum offload */ | 1286 | /* Handle TCP checksum offload */ |
1275 | if (skb->ip_summed == CHECKSUM_PARTIAL) { | 1287 | if (skb->ip_summed == CHECKSUM_PARTIAL) { |
1276 | u16 hdr = skb->h.raw - skb->data; | 1288 | unsigned offset = skb->h.raw - skb->data; |
1277 | u16 offset = hdr + skb->csum; | 1289 | u32 tcpsum; |
1290 | |||
1291 | tcpsum = offset << 16; /* sum start */ | ||
1292 | tcpsum |= offset + skb->csum; /* sum write */ | ||
1278 | 1293 | ||
1279 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; | 1294 | ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; |
1280 | if (skb->nh.iph->protocol == IPPROTO_UDP) | 1295 | if (skb->nh.iph->protocol == IPPROTO_UDP) |
1281 | ctrl |= UDPTCP; | 1296 | ctrl |= UDPTCP; |
1282 | 1297 | ||
1283 | le = get_tx_le(sky2); | 1298 | if (tcpsum != sky2->tx_tcpsum) { |
1284 | le->tx.csum.start = cpu_to_le16(hdr); | 1299 | sky2->tx_tcpsum = tcpsum; |
1285 | le->tx.csum.offset = cpu_to_le16(offset); | 1300 | |
1286 | le->length = 0; /* initial checksum value */ | 1301 | le = get_tx_le(sky2); |
1287 | le->ctrl = 1; /* one packet */ | 1302 | le->addr = cpu_to_le32(tcpsum); |
1288 | le->opcode = OP_TCPLISW | HW_OWNER; | 1303 | le->length = 0; /* initial checksum value */ |
1304 | le->ctrl = 1; /* one packet */ | ||
1305 | le->opcode = OP_TCPLISW | HW_OWNER; | ||
1306 | } | ||
1289 | } | 1307 | } |
1290 | 1308 | ||
1291 | le = get_tx_le(sky2); | 1309 | le = get_tx_le(sky2); |
1292 | le->tx.addr = cpu_to_le32((u32) mapping); | 1310 | le->addr = cpu_to_le32((u32) mapping); |
1293 | le->length = cpu_to_le16(len); | 1311 | le->length = cpu_to_le16(len); |
1294 | le->ctrl = ctrl; | 1312 | le->ctrl = ctrl; |
1295 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); | 1313 | le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER); |
@@ -1307,36 +1325,31 @@ static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev) | |||
1307 | addr64 = high32(mapping); | 1325 | addr64 = high32(mapping); |
1308 | if (addr64 != sky2->tx_addr64) { | 1326 | if (addr64 != sky2->tx_addr64) { |
1309 | le = get_tx_le(sky2); | 1327 | le = get_tx_le(sky2); |
1310 | le->tx.addr = cpu_to_le32(addr64); | 1328 | le->addr = cpu_to_le32(addr64); |
1311 | le->ctrl = 0; | 1329 | le->ctrl = 0; |
1312 | le->opcode = OP_ADDR64 | HW_OWNER; | 1330 | le->opcode = OP_ADDR64 | HW_OWNER; |
1313 | sky2->tx_addr64 = addr64; | 1331 | sky2->tx_addr64 = addr64; |
1314 | } | 1332 | } |
1315 | 1333 | ||
1316 | le = get_tx_le(sky2); | 1334 | le = get_tx_le(sky2); |
1317 | le->tx.addr = cpu_to_le32((u32) mapping); | 1335 | le->addr = cpu_to_le32((u32) mapping); |
1318 | le->length = cpu_to_le16(frag->size); | 1336 | le->length = cpu_to_le16(frag->size); |
1319 | le->ctrl = ctrl; | 1337 | le->ctrl = ctrl; |
1320 | le->opcode = OP_BUFFER | HW_OWNER; | 1338 | le->opcode = OP_BUFFER | HW_OWNER; |
1321 | 1339 | ||
1322 | fre = sky2->tx_ring | 1340 | fre = sky2->tx_ring |
1323 | + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE); | 1341 | + RING_NEXT((re - sky2->tx_ring) + i, TX_RING_SIZE); |
1324 | pci_unmap_addr_set(fre, mapaddr, mapping); | 1342 | pci_unmap_addr_set(fre, mapaddr, mapping); |
1325 | } | 1343 | } |
1326 | 1344 | ||
1327 | re->idx = sky2->tx_prod; | 1345 | re->idx = sky2->tx_prod; |
1328 | le->ctrl |= EOP; | 1346 | le->ctrl |= EOP; |
1329 | 1347 | ||
1330 | avail = tx_avail(sky2); | 1348 | if (tx_avail(sky2) <= MAX_SKB_TX_LE) |
1331 | if (mss != 0 || avail < TX_MIN_PENDING) { | 1349 | netif_stop_queue(dev); |
1332 | le->ctrl |= FRC_STAT; | ||
1333 | if (avail <= MAX_SKB_TX_LE) | ||
1334 | netif_stop_queue(dev); | ||
1335 | } | ||
1336 | 1350 | ||
1337 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); | 1351 | sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod); |
1338 | 1352 | ||
1339 | out_unlock: | ||
1340 | spin_unlock(&sky2->tx_lock); | 1353 | spin_unlock(&sky2->tx_lock); |
1341 | 1354 | ||
1342 | dev->trans_start = jiffies; | 1355 | dev->trans_start = jiffies; |
@@ -1421,7 +1434,7 @@ static int sky2_down(struct net_device *dev) | |||
1421 | /* Stop more packets from being queued */ | 1434 | /* Stop more packets from being queued */ |
1422 | netif_stop_queue(dev); | 1435 | netif_stop_queue(dev); |
1423 | 1436 | ||
1424 | sky2_phy_reset(hw, port); | 1437 | sky2_gmac_reset(hw, port); |
1425 | 1438 | ||
1426 | /* Stop transmitter */ | 1439 | /* Stop transmitter */ |
1427 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); | 1440 | sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP); |
@@ -1469,6 +1482,8 @@ static int sky2_down(struct net_device *dev) | |||
1469 | imask &= ~portirq_msk[port]; | 1482 | imask &= ~portirq_msk[port]; |
1470 | sky2_write32(hw, B0_IMSK, imask); | 1483 | sky2_write32(hw, B0_IMSK, imask); |
1471 | 1484 | ||
1485 | sky2_phy_power(hw, port, 0); | ||
1486 | |||
1472 | /* turn off LED's */ | 1487 | /* turn off LED's */ |
1473 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); | 1488 | sky2_write16(hw, B0_Y2LED, LED_STAT_OFF); |
1474 | 1489 | ||
@@ -1497,7 +1512,7 @@ static int sky2_down(struct net_device *dev) | |||
1497 | 1512 | ||
1498 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) | 1513 | static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux) |
1499 | { | 1514 | { |
1500 | if (!hw->copper) | 1515 | if (!sky2_is_copper(hw)) |
1501 | return SPEED_1000; | 1516 | return SPEED_1000; |
1502 | 1517 | ||
1503 | if (hw->chip_id == CHIP_ID_YUKON_FE) | 1518 | if (hw->chip_id == CHIP_ID_YUKON_FE) |
@@ -1519,40 +1534,10 @@ static void sky2_link_up(struct sky2_port *sky2) | |||
1519 | unsigned port = sky2->port; | 1534 | unsigned port = sky2->port; |
1520 | u16 reg; | 1535 | u16 reg; |
1521 | 1536 | ||
1522 | /* Enable Transmit FIFO Underrun */ | ||
1523 | sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK); | ||
1524 | |||
1525 | reg = gma_read16(hw, port, GM_GP_CTRL); | ||
1526 | if (sky2->autoneg == AUTONEG_DISABLE) { | ||
1527 | reg |= GM_GPCR_AU_ALL_DIS; | ||
1528 | |||
1529 | /* Is write/read necessary? Copied from sky2_mac_init */ | ||
1530 | gma_write16(hw, port, GM_GP_CTRL, reg); | ||
1531 | gma_read16(hw, port, GM_GP_CTRL); | ||
1532 | |||
1533 | switch (sky2->speed) { | ||
1534 | case SPEED_1000: | ||
1535 | reg &= ~GM_GPCR_SPEED_100; | ||
1536 | reg |= GM_GPCR_SPEED_1000; | ||
1537 | break; | ||
1538 | case SPEED_100: | ||
1539 | reg &= ~GM_GPCR_SPEED_1000; | ||
1540 | reg |= GM_GPCR_SPEED_100; | ||
1541 | break; | ||
1542 | case SPEED_10: | ||
1543 | reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100); | ||
1544 | break; | ||
1545 | } | ||
1546 | } else | ||
1547 | reg &= ~GM_GPCR_AU_ALL_DIS; | ||
1548 | |||
1549 | if (sky2->duplex == DUPLEX_FULL || sky2->autoneg == AUTONEG_ENABLE) | ||
1550 | reg |= GM_GPCR_DUP_FULL; | ||
1551 | |||
1552 | /* enable Rx/Tx */ | 1537 | /* enable Rx/Tx */ |
1538 | reg = gma_read16(hw, port, GM_GP_CTRL); | ||
1553 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; | 1539 | reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; |
1554 | gma_write16(hw, port, GM_GP_CTRL, reg); | 1540 | gma_write16(hw, port, GM_GP_CTRL, reg); |
1555 | gma_read16(hw, port, GM_GP_CTRL); | ||
1556 | 1541 | ||
1557 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); | 1542 | gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK); |
1558 | 1543 | ||
@@ -1606,7 +1591,6 @@ static void sky2_link_down(struct sky2_port *sky2) | |||
1606 | reg = gma_read16(hw, port, GM_GP_CTRL); | 1591 | reg = gma_read16(hw, port, GM_GP_CTRL); |
1607 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); | 1592 | reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); |
1608 | gma_write16(hw, port, GM_GP_CTRL, reg); | 1593 | gma_write16(hw, port, GM_GP_CTRL, reg); |
1609 | gma_read16(hw, port, GM_GP_CTRL); /* PCI post */ | ||
1610 | 1594 | ||
1611 | if (sky2->rx_pause && !sky2->tx_pause) { | 1595 | if (sky2->rx_pause && !sky2->tx_pause) { |
1612 | /* restore Asymmetric Pause bit */ | 1596 | /* restore Asymmetric Pause bit */ |
@@ -1623,6 +1607,7 @@ static void sky2_link_down(struct sky2_port *sky2) | |||
1623 | 1607 | ||
1624 | if (netif_msg_link(sky2)) | 1608 | if (netif_msg_link(sky2)) |
1625 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); | 1609 | printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name); |
1610 | |||
1626 | sky2_phy_init(hw, port); | 1611 | sky2_phy_init(hw, port); |
1627 | } | 1612 | } |
1628 | 1613 | ||
@@ -1663,8 +1648,11 @@ static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux) | |||
1663 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; | 1648 | sky2->rx_pause = (aux & PHY_M_PS_RX_P_EN) != 0; |
1664 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; | 1649 | sky2->tx_pause = (aux & PHY_M_PS_TX_P_EN) != 0; |
1665 | 1650 | ||
1666 | if ((sky2->tx_pause || sky2->rx_pause) | 1651 | if (sky2->duplex == DUPLEX_HALF && sky2->speed != SPEED_1000 |
1667 | && !(sky2->speed < SPEED_1000 && sky2->duplex == DUPLEX_HALF)) | 1652 | && hw->chip_id != CHIP_ID_YUKON_EC_U) |
1653 | sky2->rx_pause = sky2->tx_pause = 0; | ||
1654 | |||
1655 | if (sky2->rx_pause || sky2->tx_pause) | ||
1668 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); | 1656 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON); |
1669 | else | 1657 | else |
1670 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); | 1658 | sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF); |
@@ -1690,7 +1678,7 @@ static void sky2_phy_intr(struct sky2_hw *hw, unsigned port) | |||
1690 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", | 1678 | printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n", |
1691 | sky2->netdev->name, istatus, phystat); | 1679 | sky2->netdev->name, istatus, phystat); |
1692 | 1680 | ||
1693 | if (istatus & PHY_M_IS_AN_COMPL) { | 1681 | if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) { |
1694 | if (sky2_autoneg_done(sky2, phystat) == 0) | 1682 | if (sky2_autoneg_done(sky2, phystat) == 0) |
1695 | sky2_link_up(sky2); | 1683 | sky2_link_up(sky2); |
1696 | goto out; | 1684 | goto out; |
@@ -1832,15 +1820,16 @@ static int sky2_change_mtu(struct net_device *dev, int new_mtu) | |||
1832 | * For small packets or errors, just reuse existing skb. | 1820 | * For small packets or errors, just reuse existing skb. |
1833 | * For larger packets, get new buffer. | 1821 | * For larger packets, get new buffer. |
1834 | */ | 1822 | */ |
1835 | static struct sk_buff *sky2_receive(struct sky2_port *sky2, | 1823 | static struct sk_buff *sky2_receive(struct net_device *dev, |
1836 | u16 length, u32 status) | 1824 | u16 length, u32 status) |
1837 | { | 1825 | { |
1826 | struct sky2_port *sky2 = netdev_priv(dev); | ||
1838 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; | 1827 | struct ring_info *re = sky2->rx_ring + sky2->rx_next; |
1839 | struct sk_buff *skb = NULL; | 1828 | struct sk_buff *skb = NULL; |
1840 | 1829 | ||
1841 | if (unlikely(netif_msg_rx_status(sky2))) | 1830 | if (unlikely(netif_msg_rx_status(sky2))) |
1842 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", | 1831 | printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n", |
1843 | sky2->netdev->name, sky2->rx_next, status, length); | 1832 | dev->name, sky2->rx_next, status, length); |
1844 | 1833 | ||
1845 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; | 1834 | sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending; |
1846 | prefetch(sky2->rx_ring + sky2->rx_next); | 1835 | prefetch(sky2->rx_ring + sky2->rx_next); |
@@ -1851,11 +1840,11 @@ static struct sk_buff *sky2_receive(struct sky2_port *sky2, | |||
1851 | if (!(status & GMR_FS_RX_OK)) | 1840 | if (!(status & GMR_FS_RX_OK)) |
1852 | goto resubmit; | 1841 | goto resubmit; |
1853 | 1842 | ||
1854 | if (length > sky2->netdev->mtu + ETH_HLEN) | 1843 | if (length > dev->mtu + ETH_HLEN) |
1855 | goto oversize; | 1844 | goto oversize; |
1856 | 1845 | ||
1857 | if (length < copybreak) { | 1846 | if (length < copybreak) { |
1858 | skb = alloc_skb(length + 2, GFP_ATOMIC); | 1847 | skb = netdev_alloc_skb(dev, length + 2); |
1859 | if (!skb) | 1848 | if (!skb) |
1860 | goto resubmit; | 1849 | goto resubmit; |
1861 | 1850 | ||
@@ -1870,7 +1859,7 @@ static struct sk_buff *sky2_receive(struct sky2_port *sky2, | |||
1870 | } else { | 1859 | } else { |
1871 | struct sk_buff *nskb; | 1860 | struct sk_buff *nskb; |
1872 | 1861 | ||
1873 | nskb = sky2_alloc_skb(sky2->rx_bufsize, GFP_ATOMIC); | 1862 | nskb = sky2_alloc_skb(dev, sky2->rx_bufsize, GFP_ATOMIC); |
1874 | if (!nskb) | 1863 | if (!nskb) |
1875 | goto resubmit; | 1864 | goto resubmit; |
1876 | 1865 | ||
@@ -1900,7 +1889,7 @@ error: | |||
1900 | 1889 | ||
1901 | if (netif_msg_rx_err(sky2) && net_ratelimit()) | 1890 | if (netif_msg_rx_err(sky2) && net_ratelimit()) |
1902 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", | 1891 | printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n", |
1903 | sky2->netdev->name, status, length); | 1892 | dev->name, status, length); |
1904 | 1893 | ||
1905 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) | 1894 | if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE)) |
1906 | sky2->net_stats.rx_length_errors++; | 1895 | sky2->net_stats.rx_length_errors++; |
@@ -1926,12 +1915,6 @@ static inline void sky2_tx_done(struct net_device *dev, u16 last) | |||
1926 | } | 1915 | } |
1927 | } | 1916 | } |
1928 | 1917 | ||
1929 | /* Is status ring empty or is there more to do? */ | ||
1930 | static inline int sky2_more_work(const struct sky2_hw *hw) | ||
1931 | { | ||
1932 | return (hw->st_idx != sky2_read16(hw, STAT_PUT_IDX)); | ||
1933 | } | ||
1934 | |||
1935 | /* Process status response ring */ | 1918 | /* Process status response ring */ |
1936 | static int sky2_status_intr(struct sky2_hw *hw, int to_do) | 1919 | static int sky2_status_intr(struct sky2_hw *hw, int to_do) |
1937 | { | 1920 | { |
@@ -1955,16 +1938,15 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do) | |||
1955 | dev = hw->dev[le->link]; | 1938 | dev = hw->dev[le->link]; |
1956 | 1939 | ||
1957 | sky2 = netdev_priv(dev); | 1940 | sky2 = netdev_priv(dev); |
1958 | length = le->length; | 1941 | length = le16_to_cpu(le->length); |
1959 | status = le->status; | 1942 | status = le32_to_cpu(le->status); |
1960 | 1943 | ||
1961 | switch (le->opcode & ~HW_OWNER) { | 1944 | switch (le->opcode & ~HW_OWNER) { |
1962 | case OP_RXSTAT: | 1945 | case OP_RXSTAT: |
1963 | skb = sky2_receive(sky2, length, status); | 1946 | skb = sky2_receive(dev, length, status); |
1964 | if (!skb) | 1947 | if (!skb) |
1965 | break; | 1948 | break; |
1966 | 1949 | ||
1967 | skb->dev = dev; | ||
1968 | skb->protocol = eth_type_trans(skb, dev); | 1950 | skb->protocol = eth_type_trans(skb, dev); |
1969 | dev->last_rx = jiffies; | 1951 | dev->last_rx = jiffies; |
1970 | 1952 | ||
@@ -2001,7 +1983,7 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do) | |||
2001 | case OP_RXCHKS: | 1983 | case OP_RXCHKS: |
2002 | skb = sky2->rx_ring[sky2->rx_next].skb; | 1984 | skb = sky2->rx_ring[sky2->rx_next].skb; |
2003 | skb->ip_summed = CHECKSUM_COMPLETE; | 1985 | skb->ip_summed = CHECKSUM_COMPLETE; |
2004 | skb->csum = le16_to_cpu(status); | 1986 | skb->csum = status & 0xffff; |
2005 | break; | 1987 | break; |
2006 | 1988 | ||
2007 | case OP_TXINDEXLE: | 1989 | case OP_TXINDEXLE: |
@@ -2022,6 +2004,9 @@ static int sky2_status_intr(struct sky2_hw *hw, int to_do) | |||
2022 | } | 2004 | } |
2023 | } | 2005 | } |
2024 | 2006 | ||
2007 | /* Fully processed status ring so clear irq */ | ||
2008 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | ||
2009 | |||
2025 | exit_loop: | 2010 | exit_loop: |
2026 | if (buf_write[0]) { | 2011 | if (buf_write[0]) { |
2027 | sky2 = netdev_priv(hw->dev[0]); | 2012 | sky2 = netdev_priv(hw->dev[0]); |
@@ -2231,19 +2216,16 @@ static int sky2_poll(struct net_device *dev0, int *budget) | |||
2231 | sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); | 2216 | sky2_descriptor_error(hw, 1, "transmit", Y2_IS_CHK_TXA2); |
2232 | 2217 | ||
2233 | work_done = sky2_status_intr(hw, work_limit); | 2218 | work_done = sky2_status_intr(hw, work_limit); |
2234 | *budget -= work_done; | 2219 | if (work_done < work_limit) { |
2235 | dev0->quota -= work_done; | 2220 | netif_rx_complete(dev0); |
2236 | 2221 | ||
2237 | if (status & Y2_IS_STAT_BMU) | 2222 | sky2_read32(hw, B0_Y2_SP_LISR); |
2238 | sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ); | 2223 | return 0; |
2239 | 2224 | } else { | |
2240 | if (sky2_more_work(hw)) | 2225 | *budget -= work_done; |
2226 | dev0->quota -= work_done; | ||
2241 | return 1; | 2227 | return 1; |
2242 | 2228 | } | |
2243 | netif_rx_complete(dev0); | ||
2244 | |||
2245 | sky2_read32(hw, B0_Y2_SP_LISR); | ||
2246 | return 0; | ||
2247 | } | 2229 | } |
2248 | 2230 | ||
2249 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) | 2231 | static irqreturn_t sky2_intr(int irq, void *dev_id, struct pt_regs *regs) |
@@ -2303,7 +2285,7 @@ static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk) | |||
2303 | static int sky2_reset(struct sky2_hw *hw) | 2285 | static int sky2_reset(struct sky2_hw *hw) |
2304 | { | 2286 | { |
2305 | u16 status; | 2287 | u16 status; |
2306 | u8 t8, pmd_type; | 2288 | u8 t8; |
2307 | int i; | 2289 | int i; |
2308 | 2290 | ||
2309 | sky2_write8(hw, B0_CTST, CS_RST_CLR); | 2291 | sky2_write8(hw, B0_CTST, CS_RST_CLR); |
@@ -2349,9 +2331,7 @@ static int sky2_reset(struct sky2_hw *hw) | |||
2349 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); | 2331 | sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL); |
2350 | 2332 | ||
2351 | 2333 | ||
2352 | pmd_type = sky2_read8(hw, B2_PMD_TYP); | 2334 | hw->pmd_type = sky2_read8(hw, B2_PMD_TYP); |
2353 | hw->copper = !(pmd_type == 'L' || pmd_type == 'S'); | ||
2354 | |||
2355 | hw->ports = 1; | 2335 | hw->ports = 1; |
2356 | t8 = sky2_read8(hw, B2_Y2_HW_RES); | 2336 | t8 = sky2_read8(hw, B2_Y2_HW_RES); |
2357 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { | 2337 | if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) { |
@@ -2409,7 +2389,7 @@ static int sky2_reset(struct sky2_hw *hw) | |||
2409 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); | 2389 | sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK); |
2410 | 2390 | ||
2411 | for (i = 0; i < hw->ports; i++) | 2391 | for (i = 0; i < hw->ports; i++) |
2412 | sky2_phy_reset(hw, i); | 2392 | sky2_gmac_reset(hw, i); |
2413 | 2393 | ||
2414 | memset(hw->st_le, 0, STATUS_LE_BYTES); | 2394 | memset(hw->st_le, 0, STATUS_LE_BYTES); |
2415 | hw->st_idx = 0; | 2395 | hw->st_idx = 0; |
@@ -2448,21 +2428,22 @@ static int sky2_reset(struct sky2_hw *hw) | |||
2448 | 2428 | ||
2449 | static u32 sky2_supported_modes(const struct sky2_hw *hw) | 2429 | static u32 sky2_supported_modes(const struct sky2_hw *hw) |
2450 | { | 2430 | { |
2451 | u32 modes; | 2431 | if (sky2_is_copper(hw)) { |
2452 | if (hw->copper) { | 2432 | u32 modes = SUPPORTED_10baseT_Half |
2453 | modes = SUPPORTED_10baseT_Half | 2433 | | SUPPORTED_10baseT_Full |
2454 | | SUPPORTED_10baseT_Full | 2434 | | SUPPORTED_100baseT_Half |
2455 | | SUPPORTED_100baseT_Half | 2435 | | SUPPORTED_100baseT_Full |
2456 | | SUPPORTED_100baseT_Full | 2436 | | SUPPORTED_Autoneg | SUPPORTED_TP; |
2457 | | SUPPORTED_Autoneg | SUPPORTED_TP; | ||
2458 | 2437 | ||
2459 | if (hw->chip_id != CHIP_ID_YUKON_FE) | 2438 | if (hw->chip_id != CHIP_ID_YUKON_FE) |
2460 | modes |= SUPPORTED_1000baseT_Half | 2439 | modes |= SUPPORTED_1000baseT_Half |
2461 | | SUPPORTED_1000baseT_Full; | 2440 | | SUPPORTED_1000baseT_Full; |
2441 | return modes; | ||
2462 | } else | 2442 | } else |
2463 | modes = SUPPORTED_1000baseT_Full | SUPPORTED_FIBRE | 2443 | return SUPPORTED_1000baseT_Half |
2464 | | SUPPORTED_Autoneg; | 2444 | | SUPPORTED_1000baseT_Full |
2465 | return modes; | 2445 | | SUPPORTED_Autoneg |
2446 | | SUPPORTED_FIBRE; | ||
2466 | } | 2447 | } |
2467 | 2448 | ||
2468 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | 2449 | static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) |
@@ -2473,7 +2454,7 @@ static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
2473 | ecmd->transceiver = XCVR_INTERNAL; | 2454 | ecmd->transceiver = XCVR_INTERNAL; |
2474 | ecmd->supported = sky2_supported_modes(hw); | 2455 | ecmd->supported = sky2_supported_modes(hw); |
2475 | ecmd->phy_address = PHY_ADDR_MARV; | 2456 | ecmd->phy_address = PHY_ADDR_MARV; |
2476 | if (hw->copper) { | 2457 | if (sky2_is_copper(hw)) { |
2477 | ecmd->supported = SUPPORTED_10baseT_Half | 2458 | ecmd->supported = SUPPORTED_10baseT_Half |
2478 | | SUPPORTED_10baseT_Full | 2459 | | SUPPORTED_10baseT_Full |
2479 | | SUPPORTED_100baseT_Half | 2460 | | SUPPORTED_100baseT_Half |
@@ -2482,12 +2463,14 @@ static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd) | |||
2482 | | SUPPORTED_1000baseT_Full | 2463 | | SUPPORTED_1000baseT_Full |
2483 | | SUPPORTED_Autoneg | SUPPORTED_TP; | 2464 | | SUPPORTED_Autoneg | SUPPORTED_TP; |
2484 | ecmd->port = PORT_TP; | 2465 | ecmd->port = PORT_TP; |
2485 | } else | 2466 | ecmd->speed = sky2->speed; |
2467 | } else { | ||
2468 | ecmd->speed = SPEED_1000; | ||
2486 | ecmd->port = PORT_FIBRE; | 2469 | ecmd->port = PORT_FIBRE; |
2470 | } | ||
2487 | 2471 | ||
2488 | ecmd->advertising = sky2->advertising; | 2472 | ecmd->advertising = sky2->advertising; |
2489 | ecmd->autoneg = sky2->autoneg; | 2473 | ecmd->autoneg = sky2->autoneg; |
2490 | ecmd->speed = sky2->speed; | ||
2491 | ecmd->duplex = sky2->duplex; | 2474 | ecmd->duplex = sky2->duplex; |
2492 | return 0; | 2475 | return 0; |
2493 | } | 2476 | } |
@@ -2886,7 +2869,6 @@ static int sky2_set_pauseparam(struct net_device *dev, | |||
2886 | struct ethtool_pauseparam *ecmd) | 2869 | struct ethtool_pauseparam *ecmd) |
2887 | { | 2870 | { |
2888 | struct sky2_port *sky2 = netdev_priv(dev); | 2871 | struct sky2_port *sky2 = netdev_priv(dev); |
2889 | int err = 0; | ||
2890 | 2872 | ||
2891 | sky2->autoneg = ecmd->autoneg; | 2873 | sky2->autoneg = ecmd->autoneg; |
2892 | sky2->tx_pause = ecmd->tx_pause != 0; | 2874 | sky2->tx_pause = ecmd->tx_pause != 0; |
@@ -2894,7 +2876,7 @@ static int sky2_set_pauseparam(struct net_device *dev, | |||
2894 | 2876 | ||
2895 | sky2_phy_reinit(sky2); | 2877 | sky2_phy_reinit(sky2); |
2896 | 2878 | ||
2897 | return err; | 2879 | return 0; |
2898 | } | 2880 | } |
2899 | 2881 | ||
2900 | static int sky2_get_coalesce(struct net_device *dev, | 2882 | static int sky2_get_coalesce(struct net_device *dev, |
@@ -3051,7 +3033,7 @@ static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs, | |||
3051 | regs->len - B3_RI_WTO_R1); | 3033 | regs->len - B3_RI_WTO_R1); |
3052 | } | 3034 | } |
3053 | 3035 | ||
3054 | static struct ethtool_ops sky2_ethtool_ops = { | 3036 | static const struct ethtool_ops sky2_ethtool_ops = { |
3055 | .get_settings = sky2_get_settings, | 3037 | .get_settings = sky2_get_settings, |
3056 | .set_settings = sky2_set_settings, | 3038 | .set_settings = sky2_set_settings, |
3057 | .get_drvinfo = sky2_get_drvinfo, | 3039 | .get_drvinfo = sky2_get_drvinfo, |
@@ -3200,6 +3182,8 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw) | |||
3200 | struct pci_dev *pdev = hw->pdev; | 3182 | struct pci_dev *pdev = hw->pdev; |
3201 | int err; | 3183 | int err; |
3202 | 3184 | ||
3185 | init_waitqueue_head (&hw->msi_wait); | ||
3186 | |||
3203 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); | 3187 | sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW); |
3204 | 3188 | ||
3205 | err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw); | 3189 | err = request_irq(pdev->irq, sky2_test_intr, IRQF_SHARED, DRV_NAME, hw); |
@@ -3209,10 +3193,8 @@ static int __devinit sky2_test_msi(struct sky2_hw *hw) | |||
3209 | return err; | 3193 | return err; |
3210 | } | 3194 | } |
3211 | 3195 | ||
3212 | init_waitqueue_head (&hw->msi_wait); | ||
3213 | |||
3214 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); | 3196 | sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ); |
3215 | wmb(); | 3197 | sky2_read8(hw, B0_CTST); |
3216 | 3198 | ||
3217 | wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); | 3199 | wait_event_timeout(hw->msi_wait, hw->msi_detected, HZ/10); |
3218 | 3200 | ||
@@ -3304,12 +3286,13 @@ static int __devinit sky2_probe(struct pci_dev *pdev, | |||
3304 | hw->pm_cap = pm_cap; | 3286 | hw->pm_cap = pm_cap; |
3305 | 3287 | ||
3306 | #ifdef __BIG_ENDIAN | 3288 | #ifdef __BIG_ENDIAN |
3307 | /* byte swap descriptors in hardware */ | 3289 | /* The sk98lin vendor driver uses hardware byte swapping but |
3290 | * this driver uses software swapping. | ||
3291 | */ | ||
3308 | { | 3292 | { |
3309 | u32 reg; | 3293 | u32 reg; |
3310 | |||
3311 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); | 3294 | reg = sky2_pci_read32(hw, PCI_DEV_REG2); |
3312 | reg |= PCI_REV_DESC; | 3295 | reg &= ~PCI_REV_DESC; |
3313 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); | 3296 | sky2_pci_write32(hw, PCI_DEV_REG2, reg); |
3314 | } | 3297 | } |
3315 | #endif | 3298 | #endif |